summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2022-05-13KVM: PPC: Book3S HV P9: Move cede logic out of XIVE escalation rearmingNicholas Piggin
Move the cede abort logic out of xive escalation rearming and into the caller to prepare for handling a similar case with nested guest entry. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220303053315.1056880-4-npiggin@gmail.com
2022-05-13KVM: PPC: Book3S HV P9: Inject pending xive interrupts at guest entryNicholas Piggin
If there is a pending xive interrupt, inject it at guest entry (if MSR[EE] is enabled) rather than take another interrupt when the guest is entered. If xive is enabled then LPCR[LPES] is set so this behaviour should be expected. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220303053315.1056880-3-npiggin@gmail.com
2022-05-13KVM: PPC: Book3S HV: Remove KVMPPC_NR_LPIDSNicholas Piggin
KVMPPC_NR_LPIDS no longer represents any size restriction on the LPID space and can be removed. A CPU with more than 12 LPID bits implemented will now be able to create more than 4095 guests. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220123120043.3586018-7-npiggin@gmail.com
2022-05-13KVM: PPC: Book3S Nested: Use explicit 4096 LPID maximumNicholas Piggin
Rather than tie this to KVMPPC_NR_LPIDS which is becoming more dynamic, fix it to 4096 (12-bits) explicitly for now. kvmhv_get_nested() does not have to check against KVM_MAX_NESTED_GUESTS because the L1 partition table registration hcall already did that, and it checks against the partition table size. This patch also puts all the partition table size calculations into the same form, using 12 for the architected size field shift and 4 for the shift corresponding to the partition table entry size. Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-of-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220123120043.3586018-6-npiggin@gmail.com
2022-05-13KVM: PPC: Book3S HV Nested: Change nested guest lookup to use idrNicholas Piggin
This removes the fixed sized kvm->arch.nested_guests array. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220123120043.3586018-5-npiggin@gmail.com
2022-05-13KVM: PPC: Book3S HV: Use IDA allocator for LPID allocatorNicholas Piggin
This removes the fixed-size lpid_inuse array. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220123120043.3586018-4-npiggin@gmail.com
2022-05-13KVM: PPC: Book3S HV: Update LPID allocator init for POWER9, NestedNicholas Piggin
The LPID allocator init is changed to: - use mmu_lpid_bits rather than hard-coding; - use KVM_MAX_NESTED_GUESTS for nested hypervisors; - not reserve the top LPID on POWER9 and newer CPUs. The reserved LPID is made a POWER7/8-specific detail. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220123120043.3586018-3-npiggin@gmail.com
2022-05-13KVM: PPC: Remove kvmppc_claim_lpidNicholas Piggin
Removing kvmppc_claim_lpid makes the lpid allocator API a bit simpler to change the underlying implementation in a future patch. The host LPID is always 0, so that can be a detail of the allocator. If the allocator range is restricted, that can reserve LPIDs at the top of the range. This allows kvmppc_claim_lpid to be removed. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220123120043.3586018-2-npiggin@gmail.com
2022-05-13KVM: PPC: Book3S HV P9: Optimise loads around context switchNicholas Piggin
It is better to get all loads for the register values in flight before starting to switch LPID, PID, and LPCR because those mtSPRs are expensive and serialising. This also just tidies up the code for a potential future change to the context switching sequence. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220123114725.3549202-1-npiggin@gmail.com
2022-05-13KVM: PPC: Book3S HV: HFSCR[PREFIX] does not existNicholas Piggin
This facility is controlled by FSCR only. Reserved bits should not be set in the HFSCR register (although it's likely harmless as this position would not be re-used, and the L0 is forgiving here too). Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220122105639.3477407-1-npiggin@gmail.com
2022-05-13arm64: dts: mt8192: Follow binding order for SCP registersNícolas F. R. A. Prado
The dt-binding for SCP documents the reg-names order as sram, cfg, l1tcm. Update the SCP node on the mt8192 devicetree to follow that order, which gets rid of a dtbs_check warning. This doesn't change any behavior since the SCP driver accesses the memory regions through the names anyway. Fixes: c63556ec6bfe ("arm64: dts: mt8192: Add SCP node") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220504214516.2957504-1-nfraprado@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-05-13arm64: dts: mediatek: add mtk-snfi for mt7622Chuanhong Guo
This patch adds a device-tree node for the MTK SPI-NAND Flash Interface for MT7622 device tree. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Link: https://lore.kernel.org/r/20220424032527.673605-6-gch981213@gmail.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-05-13arm64: dts: mediatek: mt8195-demo: enable uart1Fabien Parent
The UART1 is exposed on a header. Enable the uart1 node to be able to use it. Signed-off-by: Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20220426134106.242353-8-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-05-13arm64: dts: mediatek: mt8195-demo: Remove input-name propertyFabien Parent
This property doesn't seem to exist in the documentation nor in source code, let's remove it from the device-tree. Signed-off-by: Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20220426134106.242353-7-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-05-13arm64: dts: mediatek: mt8183-pumpkin: fix bad thermistor node nameFabien Parent
Fix the following dtbs_check error by using the correct node name: /home/fabo/build/linux/mt8183-pumpkin/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dtb: ntc: $nodename:0: 'ntc' does not match '^thermistor(.*)?$' From schema: /home/fabo/devel/baylibre/linux-mainline/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/20220426164755.435372-1-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-05-13arm64: dts: mt7622: specify the L2 cache topologyRui Salvaterra
On an MT7622 system, the kernel complains of not being able to detect the cache hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in order to fix this. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com> Link: https://lore.kernel.org/r/20220428225755.785153-1-rsalvaterra@gmail.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-05-13arm64: dts: mt7622: specify the number of DMA requestsRui Salvaterra
The MT7622 device tree never bothered to specify the number of virtual DMA channels for the HSDMA controller, always falling back to the default value of 3. Make this value explicit, in order to avoid the following dmesg notification: mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com> Link: https://lore.kernel.org/r/20220429084225.298213-1-rsalvaterra@gmail.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-05-13arm64: dts: mediatek: pumpkin: Remove input-name propertyDang Huynh
This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh <danct12@riseup.net> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/20220425064850.246228-1-danct12@riseup.net Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-05-13x86/prctl: Remove pointless task argumentThomas Gleixner
The functions invoked via do_arch_prctl_common() can only operate on the current task and none of these function uses the task argument. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/r/87lev7vtxj.ffs@tglx
2022-05-13x86/mm: Fix marking of unused sub-pmd rangesAdrian-Ken Rueegsegger
The unused part precedes the new range spanned by the start, end parameters of vmemmap_use_new_sub_pmd(). This means it actually goes from ALIGN_DOWN(start, PMD_SIZE) up to start. Use the correct address when applying the mark using memset. Fixes: 8d400913c231 ("x86/vmemmap: handle unpopulated sub-pmd ranges") Signed-off-by: Adrian-Ken Rueegsegger <ken@codelabs.ch> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Oscar Salvador <osalvador@suse.de> Reviewed-by: David Hildenbrand <david@redhat.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220509090637.24152-2-ken@codelabs.ch
2022-05-13Merge tag 'v5.19-rockchip-soc32-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/soc Comment typo fix. * tag 'v5.19-rockchip-soc32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: rockchip: fix typos in comments Link: https://lore.kernel.org/r/4421093.ElGaqSPkdT@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13Merge tag 'visconti-arm-dt-for-v5.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti into arm/dt Visconti device tree updates for 5.19 - Update the clock providers for PCIe host controller - Update the clock providers for ethernet device - Update the clock providers for SPI - Update the clock providers for watchdog timer - Update the clock providers for I2C - Update the clock providers for UART - Add clock controller support for TMPV7708 * tag 'visconti-arm-dt-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti: arm64: dts: visconti: Update the clock providers for PCIe host controller arm64: dts: visconti: Update the clock providers for ethernet device arm64: dts: visconti: Update the clock providers for SPI arm64: dts: visconti: Update the clock providers for watchdog timer arm64: dts: visconti: Update the clock providers for I2C arm64: dts: visconti: Update the clock providers for UART arm64: dts: visconti: Add clock controller support for TMPV7708 Link: https://lore.kernel.org/r/TYWPR01MB94201E842A2F8E5E9EBF740D92C99@TYWPR01MB9420.jpnprd01.prod.outlook.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13Merge tag 'v5.19-rockchip-dts32-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt Naming and flag corrections. * tag 'v5.19-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: rename pcfg_pull_default node name on rk3036 ARM: dts: rockchip: use generic node name for dma rk3036/rk322x ARM: dts: rockchip: correct interrupt flags on rk3188 boards Link: https://lore.kernel.org/r/6919636.31r3eYUQgx@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13Merge tag 'v5.19-rockchip-dts64-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt New peripherals supported on rk356x: sfc, usb3, sata and the video-decoder on rk3328. RK3399 received some improvements and nodes for the memory controller. Additional peripherals for PineNote, Gru and BananaPi-R2-Pro. New boards are the Firefly Station M2, Pine64 SoQuartz SOM and Quartz64 model B as well as the Radxa Rock3 model A. * tag 'v5.19-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (32 commits) arm64: dts: rockchip: enable otg/drd operation of usb_host0_xhci in rk356x arm64: dts: rockchip: rename HDMI ref clock to 'ref' on rk3399 arm64: dts: rockchip: add dts for Firefly Station M2 rk3566 arm64: dts: rockchip: add SoQuartz CM4IO dts arm64: dts: rockchip: add Pine64 Quartz64-B device tree dt-bindings: arm: rockchip: Add Firefly Station M2 dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B arm64: dts: rockchip: enable usb hub on the radxa rock3 model a arm64: dts: rockchip: add usb3 support to the radxa rock3 model a arm64: dts: rockchip: add rk356x sfc support arm64: dts: rockchip: Add USB and TCPC to rk3566-pinenote arm64: dts: rockchip: Add accelerometer to rk3566-pinenote arm64: dts: rockchip: add an input enable pinconf to rk3399 arm64: dts: rockchip: Add vdec support for RK3328 arm64: dts: rockchip: Rename vdec_mmu node for RK3328 arm64: dts: rockchip: Enable dmc and dfi nodes on gru arm64: dts: rockchip: Add dfi and dmc nodes to rk3399 arm64: dts: rockchip: add clocks property to cru nodes rk3399 arm64: dts: rockchip: use generic node name for pmucru on rk3399 ... Link: https://lore.kernel.org/r/7748558.DvuYhMxLoT@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13Revert "ARM: dts: BCM5301X: Fix DTC warning for NAND node"Arnd Bergmann
This reverts commit 90103611d573, which caused a new DTC warning arch/arm/boot/dts/bcm953012hr.dts:57.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@0:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dts:62.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@200000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dts:66.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@600000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dts:70.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@1000000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm953012hr.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm953012hr.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm953012hr.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13crypto: s390 - add crypto library interface for ChaCha20Vladis Dronov
Implement a crypto library interface for the s390-native ChaCha20 cipher algorithm. This allows us to stop to select CRYPTO_CHACHA20 and instead select CRYPTO_ARCH_HAVE_LIB_CHACHA. This allows BIG_KEYS=y not to build a whole ChaCha20 crypto infrastructure as a built-in, but build a smaller CRYPTO_LIB_CHACHA instead. Make CRYPTO_CHACHA_S390 config entry to look like similar ones on other architectures. Remove CRYPTO_ALGAPI select as anyway it is selected by CRYPTO_SKCIPHER. Add a new test module and a test script for ChaCha20 cipher and its interfaces. Here are test results on an idle z15 machine: Data | Generic crypto TFM | s390 crypto TFM | s390 lib size | enc dec | enc dec | enc dec -----+--------------------+------------------+---------------- 512b | 1545ns 1295ns | 604ns 446ns | 430ns 407ns 4k | 9536ns 9463ns | 2329ns 2174ns | 2170ns 2154ns 64k | 149.6us 149.3us | 34.4us 34.5us | 33.9us 33.1us 6M | 23.61ms 23.11ms | 4223us 4160us | 3951us 4008us 60M | 143.9ms 143.9ms | 33.5ms 33.2ms | 32.2ms 32.1ms Signed-off-by: Vladis Dronov <vdronov@redhat.com> Reviewed-by: Harald Freudenberger <freude@linux.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-05-13Merge branch 'asm-generic-headers-cleanup' into asm-genericArnd Bergmann
A series from Masahiro Yamada to clean up the uapi headers, making sure they can actually be included from user space without additional dependencies on either kernel headers or specific libc versions. * asm-generic-headers-cleanup: sparc: add asm/stat.h to UAPI compile-test coverage powerpc: add asm/stat.h to UAPI compile-test coverage mips: add asm/stat.h to UAPI compile-test coverage riscv: add linux/bpf_perf_event.h to UAPI compile-test coverage kbuild: prevent exported headers from including <stdlib.h>, <stdbool.h> agpgart.h: do not include <stdlib.h> from exported header
2022-05-13sparc: add asm/stat.h to UAPI compile-test coverageMasahiro Yamada
asm/stat.h is currently excluded from the UAPI compile-test for ARCH=sparc because of the errors like follows: In file included from <command-line>: ./usr/include/asm/stat.h:11:2: error: unknown type name 'ino_t' 11 | ino_t st_ino; | ^~~~~ HDRTEST usr/include/asm/param.h ./usr/include/asm/stat.h:12:2: error: unknown type name 'mode_t' 12 | mode_t st_mode; | ^~~~~~ ./usr/include/asm/stat.h:14:2: error: unknown type name 'uid_t' 14 | uid_t st_uid; | ^~~~~ ./usr/include/asm/stat.h:15:2: error: unknown type name 'gid_t' 15 | gid_t st_gid; | ^~~~~ The errors can be fixed by prefixing the types with __kernel_. Then, remove the no-header-test entry from user/include/Makefile. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Christoph Hellwig <hch@lst.de>
2022-05-13powerpc: add asm/stat.h to UAPI compile-test coverageMasahiro Yamada
asm/stat.h is currently excluded from the UAPI compile-test for ARCH=powerpc because of the errors like follows: HDRTEST usr/include/asm/stat.h In file included from <command-line>:32: ./usr/include/asm/stat.h:32:2: error: unknown type name 'ino_t' 32 | ino_t st_ino; | ^~~~~ ./usr/include/asm/stat.h:35:2: error: unknown type name 'mode_t' 35 | mode_t st_mode; | ^~~~~~ ./usr/include/asm/stat.h:40:2: error: unknown type name 'uid_t' 40 | uid_t st_uid; | ^~~~~ ./usr/include/asm/stat.h:41:2: error: unknown type name 'gid_t' 41 | gid_t st_gid; | ^~~~~ The errors can be fixed by prefixing the types with __kernel_. Then, remove the no-header-test entry from user/include/Makefile. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Christoph Hellwig <hch@lst.de>
2022-05-13mips: add asm/stat.h to UAPI compile-test coverageMasahiro Yamada
asm/stat.h is currently excluded from the UAPI compile-test for ARCH=mips because of the errors like follows: HDRTEST usr/include/asm/stat.h In file included from <command-line>:32: ./usr/include/asm/stat.h:22:2: error: unknown type name 'ino_t' 22 | ino_t st_ino; | ^~~~~ ./usr/include/asm/stat.h:23:2: error: unknown type name 'mode_t' 23 | mode_t st_mode; | ^~~~~~ ./usr/include/asm/stat.h:25:2: error: unknown type name 'uid_t' 25 | uid_t st_uid; | ^~~~~ ./usr/include/asm/stat.h:26:2: error: unknown type name 'gid_t' 26 | gid_t st_gid; | ^~~~~ ./usr/include/asm/stat.h:58:2: error: unknown type name 'mode_t' 58 | mode_t st_mode; | ^~~~~~ ./usr/include/asm/stat.h:61:2: error: unknown type name 'uid_t' 61 | uid_t st_uid; | ^~~~~ ./usr/include/asm/stat.h:62:2: error: unknown type name 'gid_t' 62 | gid_t st_gid; | ^~~~~ The errors can be fixed by prefixing the types with __kernel_. Then, remove the no-header-test entry from user/include/Makefile. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Christoph Hellwig <hch@lst.de>
2022-05-13csky: Move $(core-y) into arch/csky/KbuildMasahiro Yamada
Use the standard obj-y form to specify the sub-directories under arch/csky/. Only leave core-y += arch/csky/$(CSKYABI)/ there. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Guo Ren <guoren@kernel.org>
2022-05-13csky: Remove unused core-y for dtsMasahiro Yamada
This line was used for embedding a DT into vmlinux. Since commit c4c14c3bd177 ("csky: remove builtin-dtb Kbuild"), DT for csky is just a separate blob. It is covered by the generic rule in the top Makefile: ifdef CONFIG_OF_EARLY_FLATTREE all: dtbs endif Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2022-05-13csky: Remove unused $(dtb-y) from boot/MakefileMasahiro Yamada
arch/csky/boot/Makefile does not build DTB, arch/csky/boot/dts/Makefile does. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Guo Ren <guoren@kernel.org>
2022-05-12ia64: mca: drop redundant spinlock initializationHaowen Bai
mlogbuf_rlock has declared and initialized by DEFINE_SPINLOCK, so we don't need to spin_lock_init again, drop it. Link: https://lkml.kernel.org/r/1652176897-4754-1-git-send-email-baihaowen@meizu.com Signed-off-by: Haowen Bai <baihaowen@meizu.com> Reviewed-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2022-05-12Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
No conflicts. Build issue in drivers/net/ethernet/sfc/ptp.c 54fccfdd7c66 ("sfc: efx_default_channel_type APIs can be static") 49e6123c65da ("net: sfc: fix memory leak due to ptp channel") https://lore.kernel.org/all/20220510130556.52598fe2@canb.auug.org.au/ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-05-12Merge tag 'v5.18-rockchip-dtsfixes1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes Fixes for the mass-production version of BananaPi R2-Pro. The mass market version received some changes compared to preproduction versions and especially the io-domain setting could affect the lifespan of the board if the wrong dt gets booted on it. * tag 'v5.18-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Add gmac1 and change network settings of bpi-r2-pro arm64: dts: rockchip: Change io-domains of bpi-r2-pro Link: https://lore.kernel.org/r/2300256.NG923GbCHz@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-12riscv: support for Svpbmt and D1 memory typesPalmer Dabbelt
Adds support for Svpbmt, the "Supervisor-mode: page-based memory types" extension, which allows pages to be marked as non-cacheable and/or I/O. This also includes support for the Allwinner D1's page table attributes via the alternatives framework, which differ from Svpbmt in various ways but are necessary to make the D1 function. * palmer/riscv-d1: riscv: add memory-type errata for T-Head riscv: don't use global static vars to store alternative data riscv: remove FIXMAP_PAGE_IO and fall back to its default value riscv: add RISC-V Svpbmt extension support riscv: Fix accessing pfn bits in PTEs for non-32bit variants riscv: move boot alternatives to after fill_hwcap riscv: prevent compressed instructions in alternatives riscv: extend concatenated alternatives-lines to the same length riscv: implement ALTERNATIVE_2 macro riscv: implement module alternatives riscv: allow different stages with alternatives riscv: integrate alternatives better into the main architecture
2022-05-12MIPS: Sibyte: remove unnecessary return variableGuo Zhengkui
Fix the following coccicheck warning: arch/mips/sibyte/bcm1480/setup.c:37:5-8: Unneeded variable: "ret". Return "0" on line 67. Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-05-12MIPS: Use NOKPROBE_SYMBOL() instead of __kprobes annotationTiezhu Yang
If define CONFIG_KPROBES, __kprobes annotation forces the whole function into the ".kprobes.text" section, NOKPROBE_SYMBOL() only stores the given function address in the "_kprobe_blacklist" section which is introduced to maintain kprobes blacklist. Modify the related code to use NOKPROBE_SYMBOL() to protect functions from kprobes instead of __kprobes annotation under arch/mips. No obvious functional change in this patch, some more work needs to be done to fix the kernel panic when execute the following testcase on mips: # cd tools/testing/selftests/ftrace # ./ftracetest test.d/kprobe/multiple_kprobes.tc Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-05-12MIPS: tools: no need to initialise statics to 0Jason Wang
Static variables do not need to be initialised to 0, because compiler will initialise all uninitialised statics to 0. Thus, remove the unneeded initializations. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-05-12MIPS: VR41xx: Drop redundant spinlock initializationHaowen Bai
slot_errbuf_lock has declared and initialized by DEFINE_SPINLOCK, so we don't need to spin_lock_init again, drop it. Signed-off-by: Haowen Bai <baihaowen@meizu.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-05-12MIPS: smp: optimization for flush_tlb_mm when exitingMao Bibo
When process exits or execute new binary, it will call function exit_mmap with old mm, there is such function call trace: exit_mmap(struct mm_struct *mm) --> tlb_finish_mmu(&tlb, 0, -1) --> arch_tlb_finish_mmu(tlb, start, end, force) --> tlb_flush_mmu(tlb); --> tlb_flush(struct mmu_gather *tlb) --> flush_tlb_mm(tlb->mm) It is not necessary to flush tlb since oldmm is not used anymore by the process, there is similar operations on IA64/ARM64 etc, this patch adds such optimization on MIPS. Signed-off-by: Mao Bibo <maobibo@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2022-05-12perf/x86/amd: Remove unused variable 'hwc'Zucheng Zheng
'hwc' is never used in amd_pmu_enable_all(), so remove it. Signed-off-by: Zucheng Zheng <zhengzucheng@huawei.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20220421111031.174698-1-zhengzucheng@huawei.com
2022-05-12ARM: dts: socfpga: align SPI NOR node name with dtschemaKrzysztof Kozlowski
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-05-12KVM: x86/mmu: Update number of zapped pages even if page list is stableSean Christopherson
When zapping obsolete pages, update the running count of zapped pages regardless of whether or not the list has become unstable due to zapping a shadow page with its own child shadow pages. If the VM is backed by mostly 4kb pages, KVM can zap an absurd number of SPTEs without bumping the batch count and thus without yielding. In the worst case scenario, this can cause a soft lokcup. watchdog: BUG: soft lockup - CPU#12 stuck for 22s! [dirty_log_perf_:13020] RIP: 0010:workingset_activation+0x19/0x130 mark_page_accessed+0x266/0x2e0 kvm_set_pfn_accessed+0x31/0x40 mmu_spte_clear_track_bits+0x136/0x1c0 drop_spte+0x1a/0xc0 mmu_page_zap_pte+0xef/0x120 __kvm_mmu_prepare_zap_page+0x205/0x5e0 kvm_mmu_zap_all_fast+0xd7/0x190 kvm_mmu_invalidate_zap_pages_in_memslot+0xe/0x10 kvm_page_track_flush_slot+0x5c/0x80 kvm_arch_flush_shadow_memslot+0xe/0x10 kvm_set_memslot+0x1a8/0x5d0 __kvm_set_memory_region+0x337/0x590 kvm_vm_ioctl+0xb08/0x1040 Fixes: fbb158cb88b6 ("KVM: x86/mmu: Revert "Revert "KVM: MMU: zap pages in batch""") Reported-by: David Matlack <dmatlack@google.com> Reviewed-by: Ben Gardon <bgardon@google.com> Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com> Message-Id: <20220511145122.3133334-1-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-05-12KVM: x86/mmu: Speed up slot_rmap_walk_next for sparsely populated rmapsVipin Sharma
Avoid calling handlers on empty rmap entries and skip to the next non empty rmap entry. Empty rmap entries are noop in handlers. Signed-off-by: Vipin Sharma <vipinsh@google.com> Suggested-by: Sean Christopherson <seanjc@google.com> Message-Id: <20220502220347.174664-1-vipinsh@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-05-12KVM: VMX: Include MKTME KeyID bits in shadow_zero_checkKai Huang
Intel MKTME KeyID bits (including Intel TDX private KeyID bits) should never be set to SPTE. Set shadow_me_value to 0 and shadow_me_mask to include all MKTME KeyID bits to include them to shadow_zero_check. Signed-off-by: Kai Huang <kai.huang@intel.com> Message-Id: <27bc10e97a3c0b58a4105ff9107448c190328239.1650363789.git.kai.huang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-05-12KVM: x86/mmu: Add shadow_me_value and repurpose shadow_me_maskKai Huang
Intel Multi-Key Total Memory Encryption (MKTME) repurposes couple of high bits of physical address bits as 'KeyID' bits. Intel Trust Domain Extentions (TDX) further steals part of MKTME KeyID bits as TDX private KeyID bits. TDX private KeyID bits cannot be set in any mapping in the host kernel since they can only be accessed by software running inside a new CPU isolated mode. And unlike to AMD's SME, host kernel doesn't set any legacy MKTME KeyID bits to any mapping either. Therefore, it's not legitimate for KVM to set any KeyID bits in SPTE which maps guest memory. KVM maintains shadow_zero_check bits to represent which bits must be zero for SPTE which maps guest memory. MKTME KeyID bits should be set to shadow_zero_check. Currently, shadow_me_mask is used by AMD to set the sme_me_mask to SPTE, and shadow_me_shadow is excluded from shadow_zero_check. So initializing shadow_me_mask to represent all MKTME keyID bits doesn't work for VMX (as oppositely, they must be set to shadow_zero_check). Introduce a new 'shadow_me_value' to replace existing shadow_me_mask, and repurpose shadow_me_mask as 'all possible memory encryption bits'. The new schematic of them will be: - shadow_me_value: the memory encryption bit(s) that will be set to the SPTE (the original shadow_me_mask). - shadow_me_mask: all possible memory encryption bits (which is a super set of shadow_me_value). - For now, shadow_me_value is supposed to be set by SVM and VMX respectively, and it is a constant during KVM's life time. This perhaps doesn't fit MKTME but for now host kernel doesn't support it (and perhaps will never do). - Bits in shadow_me_mask are set to shadow_zero_check, except the bits in shadow_me_value. Introduce a new helper kvm_mmu_set_me_spte_mask() to initialize them. Replace shadow_me_mask with shadow_me_value in almost all code paths, except the one in PT64_PERM_MASK, which is used by need_remote_flush() to determine whether remote TLB flush is needed. This should still use shadow_me_mask as any encryption bit change should need a TLB flush. And for AMD, move initializing shadow_me_value/shadow_me_mask from kvm_mmu_reset_all_pte_masks() to svm_hardware_setup(). Signed-off-by: Kai Huang <kai.huang@intel.com> Message-Id: <f90964b93a3398b1cf1c56f510f3281e0709e2ab.1650363789.git.kai.huang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-05-12KVM: x86/mmu: Rename reset_rsvds_bits_mask()Kai Huang
Rename reset_rsvds_bits_mask() to reset_guest_rsvds_bits_mask() to make it clearer that it resets the reserved bits check for guest's page table entries. Signed-off-by: Kai Huang <kai.huang@intel.com> Message-Id: <efdc174b85d55598880064b8bf09245d3791031d.1650363789.git.kai.huang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-05-12KVM: x86: a vCPU with a pending triple fault is runnablePaolo Bonzini
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit (git 2.34.1) at 2025-09-23 17:27:45 +0000