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2014-05-28MIPS: smp-cps: set a coherent default CCAPaul Burton
This patch sets a default CCA suited for use with multi-core SMP on all current MIPS CPS based systems. It may still be overriden by the cca= argument on the kernel command line. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: smp-cps: prevent multi-core SMP with unsuitable CCAPaul Burton
If the user or bootloader sets the CCA to a value which is not suited for multi-core SMP (ie. anything non-coherent) then limit the system to using only a single core and warn the user. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: smp-cps: hotplug supportPaul Burton
This patch adds support for offlining CPUs via hotplug when using the CONFIG_MIPS_CPS SMP implementation. When a CPU is offlined one of 2 things will happen: - If the CPU is part of a core which implements the MT ASE and there is at least one other VPE online within that core then the VPE will be halted by settings its TCHalt bit. - Otherwise if supported the core will be powered down via the CPC. - Otherwise the CPU will hang by executing an infinite loop. Bringing CPUs back online is then a process of either clearing the appropriate VPEs TCHalt bit or powering up the appropriate core via the CPC. Throughout the process the struct core_boot_config vpe_mask field must be maintained such that mips_cps_boot_vpes will start & stop the correct VPEs. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: pm-cps: add PM state entry code for CPS systemsPaul Burton
This patch adds code to generate entry & exit code for various low power states available on systems based around the MIPS Coherent Processing System architecture (ie. those with a Coherence Manager, Global Interrupt Controller & for >=CM2 a Cluster Power Controller). States supported are: - Non-coherent wait. This state first leaves the coherent domain and then executes a regular MIPS wait instruction. Power savings are found from the elimination of coherency interventions between the core and any other coherent requestors in the system. - Clock gated. This state leaves the coherent domain and then gates the clock input to the core. This removes all dynamic power from the core but leaves the core at the mercy of another to restart its clock. Register state is preserved, but the core can not service interrupts whilst its clock is gated. - Power gated. This deepest state removes all power input to the core. All register state is lost and the core will restart execution from its BEV when another core powers it back up. Because register state is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP implementation in order for the core to exit the state successfully. The code will detect which states are available on the current system during boot & generate the entry/exit code for those states. This will be used by cpuidle & hotplug implementations. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: smp-cps: use CPC core-other lockingPaul Burton
The core which the CPC core-other region relates to is based upon the core-local core-other addressing register. As its name suggests this register is shared between all VPEs within a core, and if there is a possibility that multiple VPEs within a core will attempt to access another core simultaneously then locking is required. This wasn't previously a problem with the only user being cpu0 during boot, but will be an issue once hotplug is implemented & may race with other users such as cpuidle. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: smp-cps: flush cache after patching mips_cps_core_entryPaul Burton
The start of mips_cps_core_entry is patched in order to provide the code with the address of the CM register region at a point where it will be running non-coherent with the rest of the system. However the cache wasn't being flushed after that patching which could in principle lead to secondary cores using an invalid CM base address. The patching is moved to cps_prepare_cpus since local_flush_icache_range has not been initialised at the point cps_smp_setup is called. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: smp-cps: function to determine whether CPS SMP is in usePaul Burton
The core power down state for cpuidle will require that the CPS SMP implementation is in use. This patch provides a mips_cps_smp_in_use function which determines whether or not the CPS SMP implementation is currently in use. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: smp-cps: rework core/VPE initialisationPaul Burton
When hotplug and/or a powered down idle state are supported cases will arise where a non-zero VPE must be brought online without VPE 0, and it where multiple VPEs must be onlined simultaneously. This patch prepares for that by: - Splitting struct boot_config into core & VPE boot config structures, allocated one per core or VPE respectively. This allows for multiple VPEs to be onlined simultaneously without clobbering each others configuration. - Indicating which VPEs should be online within a core at any given time using a bitmap. This allows multiple VPEs to be brought online simultaneously and also indicates to VPE 0 whether it should halt after starting any non-zero VPEs that should be online within the core. For example if all VPEs within a core are offlined via hotplug and the user onlines the second VPE within that core: 1) The core will be powered up. 2) VPE 0 will run from the BEV (ie. mips_cps_core_entry) to initialise the core. 3) VPE 0 will start VPE 1 because its bit is set in the cores bitmap. 4) VPE 0 will halt itself because its bit is clear in the cores bitmap. - Moving the core & VPE initialisation to assembly code which does not make any use of the stack. This is because if a non-zero VPE is to be brought online in a powered down core then when VPE 0 of that core runs it may not have a valid stack, and even if it did then it's messy to run through parts of generic kernel code on VPE 0 before starting the correct VPE. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: uasm: add MT ASE yield instructionPaul Burton
This patch allows use of the MT ASE yield instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: uasm: add wait instructionPaul Burton
This patch allows use of the wait instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: uasm: add sync instructionPaul Burton
This patch allows use of the sync instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: uasm: add jalr instructionPaul Burton
This patch allows use of the jalr instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: uasm: add a label variant of beqPaul Burton
This patch allows for use of the beq instruction with labels from uasm, much as bne & others already do. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: inst.h: define microMIPS wait opPaul Burton
The opcode for the wait instruction within POOL32AXf was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: inst.h: define microMIPS sync opPaul Burton
The opcode for the sync instruction within POOL32AXf was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: inst.h: define MT yield opPaul Burton
The opcode for the MT ASE yield instruction within the spec3 group was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: inst.h: define COP0 wait opPaul Burton
The func field for the wait instruction was missing from inst.h - this patch adds it. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: MT: define write_c0_tchalt macroPaul Burton
Define a macro to write to the current TCs TCHalt register. This will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28MIPS: add kmap_noncoherent to wire a cached non-coherent TLB entryPaul Burton
This is identical to kmap_coherent apart from the cache coherency attribute used for the TLB entry, so kmap_coherent is abstracted to kmap_prot which is then called for both kmap_coherent & kmap_noncoherent. This will be used by a subsequent patch. Suggested-by: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-05-28Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull kvm fixes from Paolo Bonzini: "Small fixes for x86, slightly larger fixes for PPC, and a forgotten s390 patch. The PPC fixes are important because they fix breakage that is new in 3.15" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: s390: announce irqfd capability KVM: x86: disable master clock if TSC is reset during suspend KVM: vmx: disable APIC virtualization in nested guests KVM guest: Make pv trampoline code executable KVM: PPC: Book3S: ifdef on CONFIG_KVM_BOOK3S_32_HANDLER for 32bit KVM: PPC: Book3S HV: Add missing code for transaction reclaim on guest exit KVM: PPC: Book3S: HV: make _PAGE_NUMA take effect
2014-05-28Merge branch 'merge' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc Pull two powerpc fixes from Ben Herrenschmidt: "Here's a pair of powerpc fixes for 3.15 which are also going to stable. One's a fix for building with newer binutils (the problem currently only affects the BookE kernels but the affected macro might come back into use on BookS platforms at any time). Unfortunately, the binutils maintainer did a backward incompatible change to a construct that we use so we have to add Makefile check. The other one is a fix for CPUs getting stuck in kexec when running single threaded. Since we routinely use kexec on power (including in our newer bootloaders), I deemed that important enough" * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc, kexec: Fix "Processor X is stuck" issue during kexec from ST mode powerpc: Fix 64 bit builds with binutils 2.24
2014-05-28ARM: dts: omap2 clock dataTero Kristo
This patch creates a unique node for each clock in the OMAP2 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-05-28ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clockPeter Ujfalusi
To allign the name with the other atl clock names: atlclkin3_ck -> atl_clkin3_ck Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-05-28ARM: OMAP2: clock: add DT boot support for cpufreq_ckTero Kristo
The clock and clkdev for this are added manually. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-05-28CLK: TI: interface: add support for omap2430 specific interface clockTero Kristo
OMAP2430 I2CHS modules require specific hardware ops to be used, so added a new compatible string for this. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-05-28CLK: TI: APLL: add support for omap2 apllsTero Kristo
This patch adds support for omap2 type aplls, which have gating and autoidle functionality. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-05-28CLK: TI: DPLL: add support for omap2 core dpllTero Kristo
OMAP2 has slightly different DPLL compared to later OMAP generations. This patch adds support for the ti,omap2-dpll-core-clock and also adds the bindings documentation. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-05-28MIPS: R46000: Fix Micro-assembler field overflow for R4600 V2Thomas Bogendoerfer
Fix uasm warning, which triggered because of workaround for R4600 V2 CPUs. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6716/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-28MIPS: SNI: Remove USE_GENERIC_EARLY_PRINTK_8250Thomas Bogendoerfer
SNI RM code has its own EARLY_PRINTK support no need for some generic 8250 stuff. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6715/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-28MIPS: Alchemy: Default to noncoherent IO on Au1200 ABManuel Lauss
CONFIG_DMA_COHERENT is no longer set; default to noncoherent io on Au1200 revision AB to make USB work. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6745/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-28MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq()Eunbong Song
In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 functionality fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid octeon_dma_bar_type" message. This patch solve this problem. Signed-off-by: Eunbong Song <eunb.song@samsung.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6747/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-28MIPS: ptrace: Avoid smp_processor_id() in preemptible codeAlex Smith
ptrace_{get,set}_watch_regs access current_cpu_data to get the watch register count/masks, which calls smp_processor_id(). However they are run in preemptible context and therefore trigger warnings like so: [ 6340.092000] BUG: using smp_processor_id() in preemptible [00000000] code: gdb/367 [ 6340.092000] caller is ptrace_get_watch_regs+0x44/0x220 Since the watch register count/masks should be the same across all CPUs, use boot_cpu_data instead. Note that this may need to change in future should a heterogenous system be supported where the count/masks are not the same across all CPUs (the current code is also incorrect for this scenario - current_cpu_data here would not necessarily be correct for the CPU that the target task will execute on). Signed-off-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6879/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-28MIPS: defconfigs: add MTD_SPI_NOR (new dependency for M25P80)Brian Norris
These defconfigs contain the CONFIG_M25P80 symbol, which is now dependent on the MTD_SPI_NOR symbol. Add CONFIG_MTD_SPI_NOR to satisfy the new dependency. At the same time, drop the now-nonexistent CONFIG_MTD_CHAR symbol. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Huang Shijie <b32955@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: linux-mtd@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/6878/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-28MIPS: Add __SANE_USERSPACE_TYPES__ to asm/types.h for LL64Aaro Koskinen
Allow 64-bit userspace programs to use ll64 types. The define name comes from commit 2c9c6ce0199a4d252e20c531cfdc9d24e39235c0 (powerpc: Add __SANE_USERSPACE_TYPES__ to asm/types.h for LL64). The patch allows to compile perf on MIPS64 and eliminates the following warnings: tests/attr.c:74:4: error: format '%llu' expects argument of type 'long long unsigned int', but argument 6 has type '__u64' [-Werror=format=] Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6890/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-28MIPS: Lemote 2F: cs5536: mfgpt: depend on !highresSebastian Andrzej Siewior
This timer does not support oneshot mode and as such the system remains in periodic mode and won't support high res timers. This patch adds a note about this in Kconfig and lets it depend on !highres so users which want to use high timers don' stuck with this timer. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: linux-mips@linux-mips.org Cc: Hua Yan <yanh@lemote.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Hongliang Tao <taohl@lemote.com> Cc: Wu Zhangjin <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6935/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-28MIPS: Lemote 2F: cs5536: mfgpt: use raw locksSebastian Andrzej Siewior
The lock is taken in the raw irq path and therefore a rawlock should be used instead of a normal spinlock. While here I drop the export symbol on that variable since there are no other users. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: linux-mips@linux-mips.org Cc: Hua Yan <yanh@lemote.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Hongliang Tao <taohl@lemote.com> Cc: Wu Zhangjin <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6936/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-28s390/lowcore: replace lowcore irb array with a per-cpu variableMartin Schwidefsky
Remove the 96-byte irb array from the lowcore and create a per-cpu variable instead. That way we will pick up any change in the definition of the struct irb automatically. Acked-By: Sebastian Ott <sebott@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-05-28s390/lowcore: reserve 96 bytes for IRB in lowcoreChristian Borntraeger
The IRB might be 96 bytes if the extended-I/O-measurement facility is used. This feature is currently not used by Linux, but struct irb already has the emw defined. So let's make the irb in lowcore match the size of the internal data structure to be future proof. We also have to add a pad, to correctly align the paste. The bigger irb field also circumvents a bug in some QEMU versions that always write the emw field on test subchannel and therefore destroy the paste definitions of this CPU. Running under these QEMU version broke some timing functions in the VDSO and all users of these functions, e.g. some JREs. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Sebastian Ott <sebott@linux.vnet.ibm.com> Cc: Cornelia Huck <cornelia.huck@de.ibm.com> Cc: stable@vger.kernel.org
2014-05-28s390/facilities: remove extract-cpu-time facility checkHeiko Carstens
Remove the check for the extract-cpu-time facility within early startup code. Both kernel and user space work if the facility is not installed. The vdso code has a run time check if the ectg is available. Besides that there is no known user. Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-05-28m68k/hp300: Convert printk to pr_foo()Fabian Frederick
This patch also fixes some checkpatch warnings This is untested Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2014-05-28m68k/apollo: Convert printk to pr_foo()Fabian Frederick
no level printk converted to pr_info This is untested Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2014-05-28m68k/amiga: Convert printk(foo to pr_foo()Fabian Frederick
-no level printk converted to pr_warn/pr_info -fixed a small identation problem This is untested Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2014-05-28m68k: Increase initial mapping to 8 or 16 MiB if possibleAndreas Schwab
If the size of the first memory chunk is at least 8 or 16 MiB increase the initial mapping to 8 resp. 16 MiB instead of 4 MiB. This makes it possible to 1. Map more memory in the first node without running out of space for the page tables, 2. Boot kernels that don't fit in 4 MiB (e.g. multi_defconfig). Signed-off-by: Andreas Schwab <schwab@linux-m68k.org> - Add support for 8 MiB, - Store initial mapping size in head.S for later reuse, - Add comment about large kernels. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2014-05-28m68k: Update defconfigs for v3.15-rc2Geert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2014-05-28m68k/atari: fix SCC initialization for debug consoleFinn Thain
Fix SCC initialization for Atari as was previously fixed for Mac. It's probably not practical to share more code but some attempt is made to align the Mac and Atari variants. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2014-05-28m68k/mvme16x: Adopt common boot consoleFinn Thain
In a multi-platform kernel binary we only need one early console instance. The difficulty here is that the common early console is started by early_param(), whereas the MVME16x instance is started later by config_mvme16x(). That means some interrupt setup must be done earlier. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Tested-by: Stephen N Chivers <schivers@csc.com.au> [Geert] Tag debug_cons_write() with __ref to kill section mismatch warning Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2014-05-28m68k: Multi-platform EARLY_PRINTKFinn Thain
Make the boot console available to more m68k platforms by leveraging the head.S debug console. The boot console is enabled by the "earlyprintk" command line argument which is how most other architectures do this. This is a change of behaviour for the Mac but does not negatively impact the common use-case which is not debugging. This is also a change of behaviour for other platforms because it means the serial port stays quiet when CONFIG_EARLY_PRINTK is not enabled. This is also an improvement for the common use-case. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Tested-by: Stephen N Chivers <schivers@csc.com.au> [Geert: CONSOLE_DEBUG should depend on CONFIG_FONT_SUPPORT] Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2014-05-28MIPS: SB1: Fix excessive kernel warnings.Ralf Baechle
A kernel build with binutils 2.24 is going to emit warnings like CC kernel/sys.o {standard input}: Assembler messages: {standard input}:701: Warning: the 32-bit MIPS architecture does not support the `mdmx' extension {standard input}:701: Warning: the `mdmx' extension requires 64-bit FPRs {standard input}:701: Warning: the `mips3d' extension requires MIPS32 revision 2 or greater {standard input}:701: Warning: the `mips3d' extension requires 64-bit FPRs for almost every file. This is caused by changes to gas' interpretation of .set semantics. Fixed by explicitly disabling MIPS3D and MDMX for Sibyte builds. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-28OMAPDSS: move 'compatible' converter to omapdss driverTomi Valkeinen
Move the panel/encoder driver compatible-string converter from arch/arm/mach-omap2/display.c to omapdss driver. That is a more logical place for it, as it's really an omapdss internal hack. The code is rewritten to follow the video node graph, starting from omapdss. This removes the need to have the device compatible-string database. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-05-28ARM: shmobile: armadillo800eva: fixup HDMI sound flags settingKuninori Morimoto
c7a507eea1db1430476289f525f9c853d5d485e8 (ASoC: fsi: fixup SND_SOC_DAIFMT_CBx_CFx flags) fixuped FSI driver's behavior which didn't match to ALSA flags. But, it didn't care about armadillo800eva HDMI sound flags. This patch fixed it. Reported-by: Bui Duc Phuc(Fukuda) <bd-phuc@jinso.co.jp> Reported-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>