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MOV CR/DR instructions ignore the mod field (in the ModR/M byte). As the SDM
states: "The 2 bits in the mod field are ignored". Accordingly, the second
operand of these instructions is always a general purpose register.
The current emulator implementation does not do so. If the mod bits do not
equal 3, it expects the second operand to be in memory.
Signed-off-by: Nadav Amit <namit@cs.technion.ac.il>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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When Hyper-V enlightenments are in effect, Windows prefers to issue an
Hyper-V MSR write to issue an EOI rather than an x2apic MSR write.
The Hyper-V MSR write is not handled by the processor, and besides
being slower, this also causes bugs with APIC virtualization. The
reason is that on EOI the processor will modify the highest in-service
interrupt (SVI) field of the VMCS, as explained in section 29.1.4 of
the SDM; every other step in EOI virtualization is already done by
apic_send_eoi or on VM entry, but this one is missing.
We need to do the same, and be careful not to muck with the isr_count
and highest_isr_cache fields that are unused when virtual interrupt
delivery is enabled.
Cc: stable@vger.kernel.org
Reviewed-by: Yang Zhang <yang.z.zhang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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By reading the touchscreen configuration from the settings that the
maXTouch chip is actually using, we can remove some platform data.
The matrix size is not used for anything, and results in some rather
confusing code to re-read it because it may change when configuration
is downloaded, so don't print it out.
Signed-off-by: Nick Dyer <nick.dyer@itdev.co.uk>
Acked-by: Benson Leung <bleung@chromium.org>
Acked-by: Yufeng Shen <miletus@chromium.org>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
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'pci/resource' into next
* dma-api:
iommu/exynos: Remove unnecessary "&" from function pointers
DMA-API: Update dma_pool_create ()and dma_pool_alloc() descriptions
DMA-API: Fix duplicated word in DMA-API-HOWTO.txt
DMA-API: Capitalize "CPU" consistently
sh/PCI: Pass GAPSPCI_DMA_BASE CPU & bus address to dma_declare_coherent_memory()
DMA-API: Change dma_declare_coherent_memory() CPU address to phys_addr_t
DMA-API: Clarify physical/bus address distinction
* pci/virtualization:
PCI: Mark RTL8110SC INTx masking as broken
* pci/msi:
PCI/MSI: Remove pci_enable_msi_block()
* pci/misc:
PCI: Remove pcibios_add_platform_entries()
s390/pci: use pdev->dev.groups for attribute creation
PCI: Move Open Firmware devspec attribute to PCI common code
* pci/resource:
PCI: Add resource allocation comments
PCI: Simplify __pci_assign_resource() coding style
PCI: Change pbus_size_mem() return values to be more conventional
PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources
PCI: Support BAR sizes up to 8GB
resources: Clarify sanity check message
PCI: Don't add disabled subtractive decode bus resources
PCI: Don't print anything while decoding is disabled
PCI: Don't set BAR to zero if dma_addr_t is too small
PCI: Don't convert BAR address to resource if dma_addr_t is too small
PCI: Reject BAR above 4GB if dma_addr_t is too small
PCI: Fail safely if we can't handle BARs larger than 4GB
x86/gart: Tidy messages and add bridge device info
x86/gart: Replace printk() with pr_info()
x86/PCI: Move pcibios_assign_resources() annotation to definition
x86/PCI: Mark ATI SBx00 HPET BAR as IORESOURCE_PCI_FIXED
x86/PCI: Don't try to move IORESOURCE_PCI_FIXED resources
x86/PCI: Fix Broadcom CNB20LE unintended sign extension
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git://git.rocketboards.org/linux-socfpga-next into next/dt
Merge "SOCFPGA DTS updates for 3.16, take 2-version 2" from Dinh Nguyen:
Add the gpio and watchdog dts entries for the SOCFPGA platform.
* tag 'socfpga_dt_updates-for-3.16_take_2_version_2' of git://git.rocketboards.org/linux-socfpga-next:
ARM: socfpga: dts: add watchdog0+1
ARM: dts: socfpga: add gpio pieces
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux into next/dt
Merge "ARM: sirf: dts update for 3.16" from Barry Son:
some minor cleanup and add some missed nodes:
1. move dma channel descriptions to generic dma properity
2. add resets properity for some nodes;
3. add missed pinctrl groups.
* tag 'sirf-dts-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux:
ARM: dts: sirf: add resets for dspif, gps and dsp nodes
ARM: dts: atlas6: add cortex-a9-pmu compatible PMU node
ARM: dts: sirf: move to use generic dma dt-binding for spi
ARM: dts: sirf: add pin group for USP0 with only RX or TX frame sync for atlas6
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers
Merge "DaVinci EDMA clean-up for v3.16" from Sekhar Nori:
This series makes edma use configuration information available within
the IP instead of reading it from platform data or DT. Some other useful
clean-ups are included too.
* tag 'davinci-for-v3.16/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: (34 commits)
ARM: edma: Remove redundant/unused parameters from edma_soc_info
ARM: davinci: Remove redundant/unused parameters for edma
ARM: dts: am4372: Remove obsolete properties from edma node
ARM: dts: am33xx: Remove obsolete properties from edma node
dt/bindings: ti,edma: Remove redundant properties from documentation
ARM: edma: Get IP configuration from HW (number of channels, tc, etc)
ARM: edma: Save number of regions from pdata to struct edma
ARM: edma: Remove num_cc member from struct edma
ARM: edma: Remove queue_tc_mapping data from edma_soc_info
ARM: davinci: Remove eDMA3 queue_tc_mapping data from edma_soc_info
ARM: edma: Do not change TC -> Queue mapping, leave it to default.
ARM: edma: Take the number of tc from edma_soc_info (pdata)
ARM: edma: No need to clean the pdata in edma_of_parse_dt()
ARM: edma: Clean up and simplify the code around irq request
dmaengine: edma: update DMA memcpy to use new param element
dmaengine: edma: Document variables used for residue accounting
dmaengine: edma: Provide granular accounting
dmaengine: edma: Make reading the position of active channels work
dmaengine: edma: Store transfer data in edma_desc and edma_pset
dmaengine: edma: Create private pset struct
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers
The patch fixes EDMA crossbar mapping to actually
make it work. The patch has been tagged for stable.
* tag 'davinci-fixes-for-v3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: common: edma: Fix xbar mapping
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next/soc
Merge "Xilinx Zynq changes for v3.16" from Michal Simek:
arm: Xilinx Zynq cleanup patches for v3.16
- Add support for BIG Endian
- Add SOC_BUS support
- Sort Kconfig options
- Fix early console
* tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: Enable big-endian
ARM: zynq: Fix uart0 early console virtual address
clocksource: cadence_ttc: Use readl/writel_relaxed instead of __raw
ARM: zynq: Sort Kconfig options
ARM: zynq: Add support for SOC_BUS
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/boards
Merge "DaVinci board changes for v3.16" from Sekhar Nori:
This patch clean-up an unused #define from code.
* tag 'davinci-for-v3.16/board' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: remove checks for CONFIG_USB_MUSB_PERIPHERAL
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "arm: Xilinx Zynq dt patches for v3.16" from Michal Simek:
- Cleanup GIC mode
- Cleanup node names
- Add regulators
* tag 'zynq-dt-for-3.16' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: dt: Add a fixed regulator for CPU voltage
ARM: zynq: dt: Clean up device tree
ARM: dts: zynq: drop address cells from GIC node
Signed-off-by: Olof Johansson <olof@lixom.net>
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Code subject to #ifdef CONSOLE is made more generic, as was apparently
intended by the original author.
Remove console_put_stats() routine. If it should be somehow useful, it
should also be useful on platforms without framebuffer debug logging. The
present implementation is only built #if defined CONFIG_MAC && defined
CONSOLE even though puts() works everywhere.
Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
Tested-by: Stephen N Chivers <schivers@csc.com.au>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
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With the kernel loaded to FastRAM (TT-RAM), none of the ST-RAM
address range is mapped by init_mem, and ST-RAM is not accessible
through the normal allocation pathways as a result.
Implement ST-RAM pool allocation to be based on physical addresses
always (it already was when the kernel was loaded in ST-RAM).
Return kernel virtual addresses as per normal.
The current test for the kernel residing in ST-RAM always returns
true. Use the bootinfo memory chunk order instead - with the kernel
in FastRAM, ST-RAM (phys. 0x0) is not the first chunk.
In case the kernel is running from FastRAM, delay mapping of ST-RAM
pool until after mem_init.
Provide helper functions for those users of ST-RAM that need
to be aware of the backing physical addresses.
Kudos to Geert for his hints on getting this started.
Signed-off-by: Michael Schmitz <schmitz@debian.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
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into next/soc
Merge "ARM: berlin: SoC changes for v3.16" from Sebastian Hesselbart:
Despite relatively young Berlin SoC support, we already have support
for a BG2Q SoC provided by Alexandre Belloni and Antoine Tenart. Also,
we gained support for DW gpio and a pinctrl driver.
* tag 'berlin-soc-3.16' of https://github.com/shesselba/linux-berlin:
ARM: berlin: add the pinctrl dependency for the Marvell Berlin SoCs
ARM: berlin: add the LIBGPIO as a dependency for the BG2Q
ARM: berlin: add MACH_BERLIN_BG2Q symbol
ARM: berlin: add Marvell Armada 1500 pro to Marvell doc
Signed-off-by: Olof Johansson <olof@lixom.net>
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next/dt
Merge "ARM: berlin: DT changes for v3.16" from Sebastian Hesselbart:
Quite a lot changes but it looks like DT approach is really paying off.
BG2Q joins Berlin SoC family with corresponding development board, DW
gpio nodes for all SoCs. Most notably, we have settled clock bindings
to allow us to continue on drivers requiring clocks and pinctrl bindings.
Last but not least, BG2Q gained SDHCI support and is able to properly
boot into userspace.
* tag 'berlin-dt-3.16' of https://github.com/shesselba/linux-berlin:
ARM: dts: berlin: enable SD card reader and eMMC for the BG2Q DMP
ARM: dts: berlin: add the SDHCI nodes for the BG2Q
ARM: dts: berlin: add the pinctrl node and muxing setup for uarts
dt-binding: ARM: add pinctrl binding docs for Marvell Berlin2 SoCs
ARM: dts: berlin: convert BG2Q to DT clock nodes
ARM: dts: berlin: convert BG2 to DT clock nodes
ARM: dts: berlin: convert BG2CD to DT clock nodes
clk: berlin: add binding include for Berlin SoC clock ids
dt-binding: ARM: add clock binding docs for Marvell Berlin2 SoCs
ARM: dts: berlin: add the BG2CD GPIO nodes
ARM: dts: berlin: add the BG2 GPIO nodes
ARM: dts: berlin: add the BG2Q GPIO nodes
ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2Q
ARM: dts: berlin: add the Marvell BG2-Q DMP device tree
ARM: dts: berlin: add the Marvell Armada 1500 pro
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Merge "ARM: omap pm changes for v3.16 merge window, resend" from Tony Lindgren:
PM related fixes for omap3 that were discovered during omap3
conversion to device tree. This series sets up the PMIC signaling
in a way where we can test for PM regressions easily by
looking at state of the the sys_clkreq and sys_off_mode pins.
Note that this series alone does not make omap3 PM to cut
off core voltage during off-idle, changes to twl4030-power.c
configurations are still needed. Those will be posted
separately.
* tag 'omap-for-v3.16/pm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Enable CPUidle in omap2plus_defconfig
ARM: dts: Enable N900 keyboard sleep leds by default
ARM: OMAP2+: Fix voltage scaling init for device tree
ARM: dts: Configure omap3 twl4030 I2C4 pins by default
ARM: OMAP3: Fix voltage control for deeper idle states
ARM: OMAP3: Disable broken omap3_set_off_timings function
ARM: OMAP3: Fix idle mode signaling for sys_clkreq and sys_off_mode
ARM: dts: Fix omap serial wake-up when booted with device tree
mfd: twl-core: Fix idle mode signaling for omaps when booted with device tree
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical
Merge "ARM: omap non urgent fixes for v3.16 merge window, resend" from Tony
Lindgren:
Non urgent omap fixes for v3.16 merge window.
* tag 'omap-for-v3.16/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition
ARM: dts: am335x-boneblack: remove use of ti,vcc-aux-disable-is-sleep
ARM: OMAP2+: free use_gptimer_clksrc variable after boot
ARM: OMAP5: Redo THUMB mode switch on secondary CPU
ARM: dts: AM4372: add l3-noc information
ARM: dts: DRA7: Use dra7-l3-noc instead of omap4-l3-noc
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Merge "ARM: omap dt changes for v3.16 merge window, part 2" From Tony Lindgren:
Device tree related changes for omaps.
* tag 'omap-for-v3.16/dt-part2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (49 commits)
ARM: dts: Enable mcpdm and mcbsp1 on DuoVero
ARM: dts: Convert DuoVero Parlor to use IOPAD macro
ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition
ARM: dts: dra7: add support for parallel NAND flash
ARM: dts: am437x-gp-evm: Add ethernet support for GP EVM
ARM: dts: am4372: Add cpsw phy sel dt node
ARM: OMAP2+: Use pdata quirks for wl12xx on VAR-STK/DVK-OM44
ARM: dts: Add VAR-SOM-OM44 WLAN nodes
ARM: dts: Add support for OMAP4 VAR-DVK-OM44
ARM: dts: Add support for OMAP4 Variscite OM44 family
ARM: dts: Change IOPAD macro's for OMAP4/5
ARM: dts: AM33XX: fix ethernet and mdio default state
ARM: dts: am4372: Add hdq device tree data
ARM: omap2+: skip device build from platform code for dt
dts: dra7-evm: add USB support
ARM: dts: dra7: Add USB related nodes
ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate
ARM: dts: omap4+: Add clocks to USB2 PHY node
ARM: dts: dra7: add OCP2SCP3 and SATA nodes
ARM: dts: omap5: add sata node
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merging in a local copy from the next/soc branch to avoid some annoying
context conflicts in the dts Makefile.
* mvebu/soc-orion5x: (29 commits)
ARM: orion: remove no longer needed gpio DT code
ARM: orion: remove no longer needed DT IRQ code
ARM: orion5x: convert Maxtor Shared Storage II to the Device Tree
ARM: orion5x: convert d2net to Device Tree
ARM: orion5x: convert RD-88F5182 to Device Tree
ARM: orion5x: remove unneeded code for edmini_v2
ARM: orion5x: keep TODO list in edmini_v2 DT
ARM: orion5x: use DT to describe NOR on edmini_v2
ARM: orion5x: use DT to describe EHCI on edmini_v2
ARM: orion5x: use DT to describe I2C devices on edmini_v2
ARM: orion5x: convert edmini_v2 to DT pinctrl
ARM: orion5x: add standard pinctrl configs for sata0 and sata1
ARM: orion5x: add Device Bus description at SoC level
ARM: orion5x: update I2C description at SoC level
ARM: orion5x: enable pinctrl driver at SoC level
ARM: orion5x: switch to DT interrupts and timer
ARM: orion: switch to a per-platform handle_irq() function
ARM: orion5x: convert to use 'clocks' property for UART controllers
ARM: orion5x: switch to use the clock driver for DT platforms
ARM: orion5x: add interrupt for Ethernet in Device Tree
...
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/boards
Merge "ARM: omap board changes for v3.16 merge window" from Tony Lindgren:
Board related changes for omaps.
* tag 'omap-for-v3.16/board-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP: replace checks for CONFIG_USB_GADGET_OMAP
ARM: OMAP: AM3517EVM: remove check for CONFIG_PANEL_SHARP_LQ043T1DG01
ARM: OMAP: SX1: remove check for CONFIG_SX1_OLD_FLASH
ARM: OMAP: remove some dead code
ARM: OMAP: omap3stalker: remove two Kconfig macros
ARM: OMAP2+: Add support for RNG on DT booted N900
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
Merge "ARM: omap prcm changes for v3.16 merge window" from Tony Lindgren:
PRCM changes for omaps. I ended up merging these with the
big endian changes because of the merge conflicts for read
and write operations. Via Paul Walmsley <paul@pwsan.com>:
Some OMAP PRCM cleanup patches. These help prepare to convert the PRCM
code into drivers.
Basic build, boot, and PM test results are available here:
http://www.pwsan.com/omap/testlogs/prcm-cleanup-v3.16/20140515213244/
* tag 'omap-for-v3.16/prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4: PRCM: remove references to cm-regbits-44xx.h from PRCM core files
ARM: OMAP3/4: PRM: add support of late_init call to prm_ll_ops
ARM: OMAP3/OMAP4: PRM: add prm_features flags and add IO wakeup under it
ARM: OMAP3/4: PRM: provide io chain reconfig function through irq setup
ARM: OMAP2+: PRM: remove unnecessary cpu_is_XXX calls from prm_init / exit
ARM: OMAP2+: PRCM: cleanup some header includes
ARM: OMAP4: CM: use cm_base* in register address calculations
ARM: OMAP2/3: CM: remove some external dependencies
ARM: OMAP2+: prcm: add omap_test_timeout to prcm-common.h
ARM: OMAP3: CM: remove a few OMAP34XX_CM_REGADDR defines
ARM: OMAP: debug-leds: raw read and write endian fix
ARM: OMAP: counter-32k: raw read and write endian fix
ARM: OMAP: dmtimer: raw read and write endian fix
ARM: OMAP2+: raw read and write endian fix
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Pull "ARM: omap soc changes for v3.16 merge window" from Tony Lindgren:
SoC related changes for omaps.
* tag 'omap-for-v3.16/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA752: add detection of SoC information
ARM: OMAP2+: Remove suspend_set_ops from common pm late init
ARM: OMAP2+: hwmod: OMAP5 DSS hwmod data
ARM: omap4: hwmod_data: Clean up audio related structures (remove/merge them)
Signed-off-by: Olof Johansson <olof@lixom.net>
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The sunxi reset controller code is only used with sun6i (a31).
After the platform has been split up into per-soc options, it's
now possible to build it without the reset controller code, so
the base platform init must not call into the reset driver
if that is turned off at compile time.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The versatile express changes for 3.16 introduced a number of
build regressions for randconfig kernels by not tracking dependencies
between the components right.
This patch tries to rectify that:
* the mach-vexpress code cannot link without the syscfg driver,
which in turn needs MFD_VEXPRESS_SYSREG
* various drivers call devm_regmap_init_vexpress_config(), which
has to be exported so it can be used by loadable modules
* the configuration bus uses OF DT helper functions that are not
available to platforms disable CONFIG_OF
* The sysreg driver exports GPIOs through gpiolib, which can
be disabled on some platforms.
* The clocksource code cannot be built on platforms that don't
use modern timekeeping but rely on gettimeoffset.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
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patch 37ebbcff7837 ("arm: iop13xx: Use sparse irqs for MSI") moved
iop13xx over to sparse IRQ support, but this broke the build for the
msi.c file, which now has to include mach/irqs.h itself.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/12285212.fBJyVfk69p@wuerfel
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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A few platforms lack a 'device_type = "memory"' for their memory
nodes, relying on an old ppc quirk in order to discover its memory.
Add the missing data so that all parsing code can find memory nodes
correctly.
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: <stable@vger.kernel.org>
Cc: gaurav.minocha@alumni.ubc.ca
Patchwork: https://patchwork.linux-mips.org/patch/6989/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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This patch moves data allocated using kzalloc to managed data allocated
using devm_kzalloc and cleans now unnecessary kfrees in probe and remove
functions. Also, the now unnecessary labels out_mem and out are done
away with. The error handling code is moved under if and return 0 is now
at the end of the function.
The following Coccinelle semantic patch was used for making the change:
@platform@
identifier p, probefn, removefn;
@@
struct platform_driver p = {
.probe = probefn,
.remove = removefn,
};
@prb@
identifier platform.probefn, pdev;
expression e, e1, e2;
@@
probefn(struct platform_device *pdev, ...) {
<+...
- e = kzalloc(e1, e2)
+ e = devm_kzalloc(&pdev->dev, e1, e2)
...
?-kfree(e);
...+>
}
@rem depends on prb@
identifier platform.removefn;
expression e;
@@
removefn(...) {
<...
- kfree(e);
...>
}
Signed-off-by: Himangi Saraogi <himangi774@gmail.com>
Acked-by: Julia Lawall <julia.lawall@lip6.fr>
Tested-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6977/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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The parent field of the 'rc32434_res_pci_mem1' resource points to
the resource itself which is obviously wrong. Due to the broken
initialitazion, the PCI devices on the Mikrotik RB532 boards are
not working since commit 22283178 (MIPS: avoid possible resource
conflict in register_pci_controller).
Remove the field initialization to fix the issue.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Reported-by: Waldemar Brodkorb <wbx@openadk.org>
Cc: linux-mips@linux-mips.org
Cc: Gabor Juhos <juhosg@openwrt.org>
Patchwork: https://patchwork.linux-mips.org/patch/6940/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Singed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Singed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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dependent upon the value to output!
Singed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Singed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Move the check for the QSPI config option inside the function body. If the
option is not enabled, the compiler will optimize away the empty function
body so we can remove the other check for the config option.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Use the correct base address for the QSPI module on the 5249/525x.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Since we now have fake clks on devices without real clocks, we need clks
defined for qspi for the qspi driver to work on those devices.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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In file included from arch/m68k/kernel/setup.c:4:0:
arch/m68k/kernel/setup_no.c:70:0: warning: "CPU_NAME" redefined [enabled by default]
#define CPU_NAME "MC68VZ328"
^
arch/m68k/kernel/setup_no.c:61:0: note: this is the location of the previous definition
#define CPU_NAME "MC68000"
^
Signed-off-by: Daniel Palmer <danieruru@gmail.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Signed-off-by: Daniel Palmer <danieruru@gmail.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The Cortex-A17 PMU is identical to that of the A12, so wire up a new
compatible string to the existing event structures.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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On CPUs with virtualization extensions the kernel installs HYP mode
configuration on both primary and secondary cpus upon cold boot.
On platforms where CPUs are shutdown in idle paths (ie CPU core gating),
when a CPU resumes from low-power states it currently does not execute
code that reinstalls the HYP configuration, which means that the kernel
cannot run eg KVM properly on such machines.
This patch, mirroring cold-boot behaviour, executes position independent
code that reinstalls HYP configuration and drops to SVC mode safely on
warmboot, so that deep idle states can be enabled in kernel running as
hosts on platforms with power management HW.
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Dave Martin <dave.martin@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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After instruction write into xol area, on ARM V7
architecture code need to flush dcache and icache to sync
them up for given set of addresses. Having just
'flush_dcache_page(page)' call is not enough - it is
possible to have stale instruction sitting in icache
for given xol area slot address.
Introduce arch_uprobe_ixol_copy weak function
that by default calls uprobes copy_to_page function and
than flush_dcache_page function and on ARM define new one
that handles xol slot copy in ARM specific way
flush_uprobe_xol_access function shares/reuses implementation
with/of flush_ptrace_access function and takes care of writing
instruction to user land address space on given variety of
different cache types on ARM CPUs. Because
flush_uprobe_xol_access does not have vma around
flush_ptrace_access was split into two parts. First that
retrieves set of condition from vma and common that receives
those conditions as flags.
Note ARM cache flush function need kernel address
through which instruction write happened, so instead
of using uprobes copy_to_page function changed
code to explicitly map page and do memcpy.
Note arch_uprobe_copy_ixol function, in similar way as
copy_to_user_page function, has preempt_disable/preempt_enable.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Oleg Nesterov <oleg@redhat.com>
Reviewed-by: David A. Long <dave.long@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The name "power_down_finish" seems to be causing some confusion,
because it suggests that this function is responsible for taking
some action to cause the specified CPU to complete its power down.
This patch renames the affected functions to "wait_for_powerdown"
and similar, since this function's intended purpose is just to wait
for the hardware to finish a powerdown initiated by a previous
cpu_power_down.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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dsb st can be used to ensure completion of pending cache maintenance
operations, so use it for the v7 cache maintenance operations.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Cortex-A17 has identical initialisation requirements to Cortex-A12, so
hook it up in proc-v7.S in the same way.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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With large kernel builds such as allyesconfig exceeding maximum relative
branch offsets, the init section will be too far away to branch to
directly. This causes veneers to be added by the linker, but veneers
don't work before the MMU is enabled. Fix this by moving __fixup_smp to
the .head.text section as it is not very big.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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According to the ARM ARM, the behaviour is UNPREDICTABLE if the PC read
from the exception return stack is not half word aligned. See the
pseudo code for ExceptionReturn() and PopStack().
The signal handler's address has the bit 0 set, and setup_return()
directly writes this to regs->ARM_pc. Current hardware happens to
discard this bit, but QEMU's emulation doesn't and this makes processes
crash. Mask out bit 0 before the exception return in order to get
predictable behaviour.
Fixes: 19c4d593f0b4 ("ARM: ARMv7-M: Add support for exception handling")
Cc: stable@kernel.org
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The arm EABI states that unwind opcode 10100nnn means pop register r4-4[4+nnn],aditionally there is a similar unwind opcode: 10101nnn which means the same thing plus popping r14. Those two cases are handled by the unwind_exec_pop_r4_to_rN function which checks whether the 4th bit is set and does r14 popping.
However, up until now it has been checking whether the 8th bit was set (mask & 0x80) instead of the 4th (mask & 0x8), a simple to make typo but this meant that we were always popping r14 even if we had the former opcode.
This patch changes the mask so that the 2 unwind opcodes are being handled correctly.
Signed-off-by: Nikolay Borisov <Nikolay.Borisov@arm.com>
Reviewed-by: Anurag Aggarwal <anurag19aggarwal@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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According to arm procedure call standart r2 register is call-cloberred.
So after the result of x expression was put into r2 any following
function call in p may overwrite r2. To fix this, the result of p
expression must be saved to the temporary variable before the
assigment x expression to __r2.
Signed-off-by: Andrey Ryabinin <a.ryabinin@samsung.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Cc: stable@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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__v7m_setup_stack currently sits in the .proc.info.init section, and
thus creates a bogus proc info entry (which by the way matches any
unknown CPU IDs, due to the entry's mask being 0). Move it out of
there.
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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A look at the code reveals use of S5P_VA_SYSRAM macro, in case of certain SoC
revisions, which is not valid any longer, after SYSRAM started to be mapped
dynamically. The new dynamic mapping is stored in sysram_base_addr variable,
which is declared static in platsmp.c
This fix makes sysram_base_addr non-static, declared it in common.h and used
in pm.c instead of S5P_VA_SYSRAM.
Suggested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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