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2020-01-16Merge tag 'sunxi-dt-for-5.6-2' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt This is our usual set of DT patches for the Allwinner SoCs. It's fairly big this time, but the highlights are: - Enable cpufreq and CPU thermal throttling on the A64 - CLK_CPUX macro usage removed (changed from first pull request) - CSI0 support on the R40 - CSI1 support on the A10 and A20 - SPI support on the R40 - PMU support on the H3, H5, H6 and R40 - MIPI-DSI support on the A64 - PWM support on the H6 - Thermal sensor on the A64, A83t, H3, H5, H6 and R40 - More DT schemas fixes and conversions - New boards: LibreComputer ALL-H5-CC H5, LibreComputer ALL-H3-IT H5, Pine64 H64 Model B, Neutis N5H3 * tag 'sunxi-dt-for-5.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (52 commits) arm64: dts: allwinner: a64: enable DVFS arm64: dts: allwinner: a64: add dtsi with CPU operating points arm64: dts: allwinner: a64: add cooling maps and thermal tripping points arm64: dts: allwinner: a64: add CPU clock to CPU0-3 nodes arm64: dts: allwinner: sun50i-a64: Use macros for newly exported clocks ARM: dts: sunxi: Use macros for references to CCU clocks arm64: dts: allwinner: h5: Add Libre Computer ALL-H5-CC H5 board ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes arm64: dts: allwinner: a64: pinebook: Fix lid wakeup ARM: dts: sun8i: r40: Add device node for CSI0 ARM: dts: sun7i: Add CSI1 controller and pinmux options ARM: dts: sun4i: Add CSI1 controller and pinmux options ARM: dts: sunxi: Add missing LVDS resets and clocks ARM: dts: sun8i: r40: Use tcon top clock index macros ARM: dts: sun8i: R40: Add PMU node ARM: dts: sun8i: R40: Upgrade GICC reg size to 8K arm64: dts: allwinner: h6: Add thermal sensor and thermal zones ARM: dts: sunxi: Add Libre Computer ALL-H3-IT H5 board arm64: dts: allwinner: a64: Add MIPI DSI pipeline arm64: dts: allwinner: a64: Add thermal sensors and thermal zones ... Link: https://lore.kernel.org/r/20200113095555.GA29848@wens.csie.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'soc-fsl-next-v5.6' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers NXP/FSL SoC driver updates for v5.6 QUICC Engine drivers - Improve the QE drivers to be compatible with ARM/ARM64/PPC64 architectures - Various cleanups to the QE drivers * tag 'soc-fsl-next-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: (49 commits) soc: fsl: qe: remove set but not used variable 'mm_gc' soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE soc: fsl: qe: remove unused #include of asm/irq.h from ucc.c net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32 net/wan/fsl_ucc_hdlc: reject muram offsets above 64K net/wan/fsl_ucc_hdlc: fix reading of __be16 registers net/wan/fsl_ucc_hdlc: avoid use of IS_ERR_VALUE() soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c soc: fsl: qe: drop pointless check in qe_sdma_init() soc: fsl: qe: drop use of IS_ERR_VALUE in qe_sdma_init() soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c soc: fsl: qe: refactor cpm_muram_alloc_common to prevent BUG on error path soc: fsl: qe: drop broken lazy call of cpm_muram_init() soc: fsl: qe: make cpm_muram_free() ignore a negative offset soc: fsl: qe: make cpm_muram_free() return void soc: fsl: qe: change return type of cpm_muram_alloc() to s32 serial: ucc_uart: access __be32 field using be32_to_cpu serial: ucc_uart: limit brg-frequency workaround to PPC32 serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe() serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32 ... Link: https://lore.kernel.org/r/1578608351-23289-1-git-send-email-leoyang.li@nxp.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16MIPS: vdso: Define BUILD_VDSO32 when building a 32bit kernelThomas Gleixner
The confinement of the 32bit specific VDSO functions missed to define BUILD_VDSO32 when building a 32bit MIPS kernel: arch/mips/vdso/vgettimeofday.c: In function __vdso_clock_gettime: arch/mips/vdso/vgettimeofday.c:17:9: error: implicit declaration of function __cvdso_clock_gettime32 arch/mips/vdso/vgettimeofday.c: In function __vdso_clock_getres: arch/mips/vdso/vgettimeofday.c:39:9: error: implicit declaration of function __cvdso_clock_getres_time32 Force the define for 32bit builds in the VDSO Makefile. Fixes: bf279849ad59 ("lib/vdso: Build 32 bit specific functions in the right context") Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Paul Burton <paulburton@kernel.org> Link: https://lore.kernel.org/r/87d0bjfaqa.fsf@nanos.tec.linutronix.de
2020-01-16x86/CPU/AMD: Ensure clearing of SME/SEV features is maintainedTom Lendacky
If the SME and SEV features are present via CPUID, but memory encryption support is not enabled (MSR 0xC001_0010[23]), the feature flags are cleared using clear_cpu_cap(). However, if get_cpu_cap() is later called, these feature flags will be reset back to present, which is not desired. Change from using clear_cpu_cap() to setup_clear_cpu_cap() so that the clearing of the flags is maintained. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: <stable@vger.kernel.org> # 4.16.x- Link: https://lkml.kernel.org/r/226de90a703c3c0be5a49565047905ac4e94e8f3.1579125915.git.thomas.lendacky@amd.com
2020-01-16Merge tag 'imx-defconfig-5.6' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfig i.MX defconfig update for 5.6: - Enable i.MX8MP clock driver in arm64 defconfig. - Enable Crypto CAAM driver support as module in arm64 defconfig. - Enable ILI210X touch driver, USB CDC ACM function, NFS_V4 support and TFP410 DVI bridge driver support in arm32 imx_v6_v7_defconfig. * tag 'imx-defconfig-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: defconfig: Enable CONFIG_CLK_IMX8MP by default arm64: defconfig: Enable CRYPTO_DEV_FSL_CAAM ARM: imx_v6_v7_defconfig: Select the TFP410 driver ARM: imx_v6_v7_defconfig: Enable NFS_V4_1 and NFS_V4_2 support ARM: configs: imx_v6_v7_defconfig: enable USB ACM ARM: imx_v6_v7_defconfig: Enable TOUCHSCREEN_ILI210X Link: https://lore.kernel.org/r/20200113034006.17430-6-shawnguo@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'imx-dt64-5.6' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX arm64 device tree update for 5.6: - New board support: i.MX8MQ based Thor96 board, Google i.MX8MQ Phanbell board, LX2160A based Solidrun Clearfog CX and Honeycomb boards. - Add eLCDIF controller and missing SAI nodes for i.MX8MQ SoC. - Add Crypto CAAM support for i.MX8MM and i.MX8MN. - Drop unneeded "simple-bus" from anatop node on i.MX8MM and i.MX8MN. - Drop unused/undocumented "fsl,aips-bus" and "fsl,imx8mq-aips-bus" compatibles from i.MX8M SoCs. - Add DDR controller nodes for i.MX8M devices. - Add EEPROM description for imx8mq-hummingboard-pulse and imx8mq-sr-som boards. - Enable USB1 and TypeC support for imx8mn-evk board. - Add FlexSPI and QSPI support for a few Layerscape SoCs and boards. - Add External MDIO1 node and the two RGMII PHYs connected on LX2160A. - Add missing SAI devices and set SAIs into async mode on LS1028A. - Other random device additions and enhancement for various platforms. * tag 'imx-dt64-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (35 commits) arm64: dts: imx8mn: Memory node should be in board DT arm64: dts: imx8mm: Memory node should be in board DT arm64: dts: imx8mn: add crypto node arm64: dts: imx8mq-hummingboard-pulse: add eeprom description arm64: dts: imx8mq-sr-som: add eeprom description arm64: dts: ls208xa: Update qspi node properties for LS2088ARDB arm64: dts: freescale: Add devicetree support for Thor96 board arm64: dts: imx8mq-librem5-devkit: add accelerometer and gyro sensor arm64: dts: imx8mm: Add Crypto CAAM support arm64: dts: freescale: add initial support for Google i.MX 8MQ Phanbell arm64: dts: ls1028a-rdb: enable emmc hs400 mode arm64: dts: ls1028a: Update edma compatible to fit eDMA driver arm64: dts: imx8m: drop "fsl,aips-bus" and "fsl,imx8mq-aips-bus" arm64: dts: imx8mm: Add missing mux options for UART1 and UART2 signals arm64: dts: lx2160a: add dts for CEX7 platforms arm64: dts: lx2160a: add emdio2 node arm64: dts: ls1028a: put SAIs into async mode arm64: dts: ls1028a: add missing sai nodes arm64: dts: imx8mn-evk: enable usb1 and typec support arm64: dts: imx8mn: Remove setting for IMX8MN_CLK_USB_CORE_REF ... Link: https://lore.kernel.org/r/20200113034006.17430-5-shawnguo@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'imx-dt-5.6' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX device tree update for 5.6: - New board support: i.MX6SL based Tolino Shine 3 eBook reader, i.MX7ULP Embedded Artists COM Board, i.MX6Q/DL based Gateworks Ventana Boards. - A couple of series from Andrey Smirnov to enhance i.MX6 RDU2 and VF610 ZII boards. - Add revision in board compatible string for imx6sx-sdb-reva and imx7d-sdb-reva board. - A fixup on imx6sl-tolino-shine3 board to remove incorrect power supply assignment. - Set initial buck regulator modes explicitly for phycore-imx6 board, so that a wrong initial mode set by bootloader does not interfere. - Add Add LCD support for imx7d-pico board. - A couple of patches from Michael Grzeschik to enhance USB Host support on i.MX25. - A couple of patches from Michael Trimarchi to remove duplicate Ethernet PHY reset properties on imx6qdl-icore and switch to phy-handle. - A couple of changes to add extirq node support on LS1021A SoC and make use of it on the LS1021A-TSN board. - A few random device additions and improvements on various boards. * tag 'imx-dt-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (33 commits) ARM: dts: imx: Add GW5912 board support ARM: dts: imx: Add GW5913 board support ARM: dts: imx: Add GW5910 board support ARM: dts: imx: Add GW5907 board support ARM: dts: imx6ul-14x14-evk: Pass the "broken-cd" property ARM: dts: imx6sl-tolino-shine3: Remove incorrect power supply assignment ARM: dts: imx7d-pico: Add LCD support ARM: dts: imx6qdl-icore: Add fec phy-handle ARM: dts: imx6qdl-icore-1.5: Remove duplicate phy reset methods ARM: dts: imx7: Unify temp-grade and speed-grade nodes ARM: dts: imx6: phycore-som: add pmic onkey device ARM: dts: imx51-babbage: Fix the DVI output description ARM: dts: imx6qdl-apalis: mux HDMI CEC pin ARM: dts: imx6sll: add PXP module ARM: dts: colibri-imx6ull: correct wrong pinmuxing and add comments ARM: dts: vf610-zii-scu4-aib: Add node for switch watchdog ARM: dts: vf610-zii-scu4-aib: Use generic names for DT nodes ARM: dts: vf610-zii-dev-rev-b: Drop redundant I2C properties ARM: dts: phycore-imx6: set buck regulator modes explicitly ARM: dts: imx6: rdu2: Limit USBH1 to Full Speed ... Link: https://lore.kernel.org/r/20200113034006.17430-4-shawnguo@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'imx-soc-5.6' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/soc i.MX SoC changes for 5.6: - Add support for reading serial number from OCOTP on i.MX7ULP. - A patch from Anson to enable ARM_ERRATA_814220 for i.MX6UL & i.MX7D, and a fixup patch from Arnd to select the option only for ARMv7-A. * tag 'imx-soc-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: only select ARM_ERRATA_814220 for ARMv7-A ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D ARM: imx: Add i.MX7ULP SoC serial number support ARM: imx: Fix boot crash if ocotp is not found ARM: imx_v6_v7_defconfig: Explicitly restore CONFIG_DEBUG_FS ARM: dts: imx6ul-evk: Fix peripheral regulator arm64: dts: ls1028a: fix reboot node arm64: dts: ls1028a: fix typo in TMU calibration data ARM: imx: Correct ocotp id for serial number support of i.MX6ULL/ULZ SoCs ARM: dts: e60k02: fix power button ARM: dts: imx6ul: imx6ul-14x14-evk.dtsi: Fix SPI NOR probing Link: https://lore.kernel.org/r/20200113034006.17430-2-shawnguo@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'mvebu-dt64-5.6-1' of git://git.infradead.org/linux-mvebu into arm/dtOlof Johansson
mvebu dt64 for 5.6 (part 1) micro-DPU (uDPU) board changes (Armada 3270 based board): - Fix broken ethernet - Remove i2c-fast-mode property - Indicate that SFP cages support 3W modules SolidRun Clearfog GT 8K (Armada 8040 base board): - Fix switch cpu port node * tag 'mvebu-dt64-5.6-1' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: clearfog-gt-8k: fix switch cpu port node arm64: dts: uDPU: SFP cages support 3W modules arm64: dts: uDPU: remove i2c-fast-mode arm64: dts: uDPU: fix broken ethernet Link: https://lore.kernel.org/r/871rs53nu5.fsf@FE-laptop Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'mvebu-dt-5.6-1' of git://git.infradead.org/linux-mvebu into arm/dtOlof Johansson
mvebu dt for 5.6 (part 1) - Add support for SolidRun Clearfog GTR (Armada 385 based board) - Move i2c0 to the SoliRrun Microsom dtsi (Armada 38x based) - Add EEPROM node on SoliRrun Microsom (rev 2.1) - Add EEPROM node on SoliRrun ClearFog Pro * tag 'mvebu-dt-5.6-1' of git://git.infradead.org/linux-mvebu: ARM: dts: armada-388-clearfog: add eeprom ARM: dts: armada-38x-solidrun-microsom: add eeprom ARM: armada-38x-solidrun-microsom: move i2c0 to SOM DT ARM: dts: mvebu: add support for SolidRun Clearfog GTR Link: https://lore.kernel.org/r/874kx13nvh.fsf@FE-laptop Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'tegra-for-5.6-arm64-defconfig' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/defconfig arm64: tegra: Default configuration updates for v5.6-rc1 This enables the USB GPIO connector and Tegra XUDC drivers in the default configuration. * tag 'tegra-for-5.6-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: defconfig: Enable tegra XUDC support Link: https://lore.kernel.org/r/20200111005526.2413959-1-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'tegra-for-5.6-arm64-dt' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Device tree changes for v5.6-rc1 These patches do some cleanup to existing nodes, add the memory subsystem on Tegra186 and Tegra194 as well as the FUSE and APB MISC nodes on Tegra194. There are also a few additions to the Jetson Nano device tree to enable additional features and the force recovery button on the Jetson AGX Xavier now produces a key code that is actually valid. Finally, an alias is added for the Ethernet card on Jetson TX2 to allow firmware to find it and pass a MAC address via device tree. * tag 'tegra-for-5.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Allow bootloader to configure Ethernet MAC on Jetson TX2 arm64: tegra: Redefine force recovery key on Jetson AGX Xavier arm64: tegra: Enable SDIO on Jetson Nano M.2 Key E arm64: tegra: Enable PWM fan on Jetson Nano arm64: tegra: Add fuse/apbmisc node on Tegra194 arm64: tegra: Make XUSB node consistent with the rest arm64: tegra: Add the memory subsystem on Tegra194 arm64: tegra: Add external memory controller on Tegra186 arm64: tegra: Add interrupt for memory controller on Tegra186 arm64: tegra: Rename EMC on Tegra132 arm64: tegra: Let the EMC hardware use the EMC clock Link: https://lore.kernel.org/r/20200111003553.2411874-7-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'tegra-for-5.6-arm-dt' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt ARM: tegra: Device tree changes for v5.6-rc1 This adds memory timings for the PAZ100 and does some minor cleanup for the external memory controller device tree node on Tegra124. * tag 'tegra-for-5.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: dts: tegra20: paz00: Add memory timings ARM: tegra: Rename EMC on Tegra124 ARM: tegra: Let the EMC hardware use the EMC clock Link: https://lore.kernel.org/r/20200111003553.2411874-6-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16Merge tag 'tegra-for-5.6-arm-core' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc ARM: tegra: Core changes for v5.6-rc1 Contains a couple of fixes for RAM repair on Tegra124. * tag 'tegra-for-5.6-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Use clk_m CPU on Tegra124 LP1 resume ARM: tegra: Modify reshift divider during LP1 ARM: tegra: Enable PLLP bypass during Tegra124 LP1 Link: https://lore.kernel.org/r/20200111003553.2411874-5-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-16arm64: kernel: avoid x18 in __cpu_soft_restartArd Biesheuvel
The code in __cpu_soft_restart() uses x18 as an arbitrary temp register, which will shortly be disallowed. So use x8 instead. Link: https://patchwork.kernel.org/patch/9836877/ Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> [Sami: updated commit message] Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16arm64: kvm: stop treating register x18 as caller saveArd Biesheuvel
In preparation of reserving x18, stop treating it as caller save in the KVM guest entry/exit code. Currently, the code assumes there is no need to preserve it for the host, given that it would have been assumed clobbered anyway by the function call to __guest_enter(). Instead, preserve its value and restore it upon return. Link: https://patchwork.kernel.org/patch/9836891/ Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> [Sami: updated commit message, switched from x18 to x29 for the guest context] Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16arm64/lib: copy_page: avoid x18 register in assembler codeArd Biesheuvel
Register x18 will no longer be used as a caller save register in the future, so stop using it in the copy_page() code. Link: https://patchwork.kernel.org/patch/9836869/ Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> [Sami: changed the offset and bias to be explicit] Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16arm64: mm: avoid x18 in idmap_kpti_install_ng_mappingsSami Tolvanen
idmap_kpti_install_ng_mappings uses x18 as a temporary register, which will result in a conflict when x18 is reserved. Use x16 and x17 instead where needed. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16arm64: fix alternatives with LLVM's integrated assemblerSami Tolvanen
LLVM's integrated assembler fails with the following error when building KVM: <inline asm>:12:6: error: expected absolute expression .if kvm_update_va_mask == 0 ^ <inline asm>:21:6: error: expected absolute expression .if kvm_update_va_mask == 0 ^ <inline asm>:24:2: error: unrecognized instruction mnemonic NOT_AN_INSTRUCTION ^ LLVM ERROR: Error parsing inline asm These errors come from ALTERNATIVE_CB and __ALTERNATIVE_CFG, which test for the existence of the callback parameter in inline assembly using the following expression: " .if " __stringify(cb) " == 0\n" This works with GNU as, but isn't supported by LLVM. This change splits __ALTERNATIVE_CFG and ALTINSTR_ENTRY into separate macros to fix the LLVM build. Link: https://github.com/ClangBuiltLinux/linux/issues/472 Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16arm64: lse: fix LSE atomics with LLVM's integrated assemblerSami Tolvanen
Unlike gcc, clang considers each inline assembly block to be independent and therefore, when using the integrated assembler for inline assembly, any preambles that enable features must be repeated in each block. This change defines __LSE_PREAMBLE and adds it to each inline assembly block that has LSE instructions, which allows them to be compiled also with clang's assembler. Link: https://github.com/ClangBuiltLinux/linux/issues/671 Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Tested-by: Andrew Murray <andrew.murray@arm.com> Tested-by: Kees Cook <keescook@chromium.org> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16arm64: defconfig: Enable Broadcom's STB PCIe controllerNicolas Saenz Julienne
For now mainly used in the Raspberry Pi 4. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-16x86/amd_nb: Add Family 19h PCI IDsYazen Ghannam
Add the new PCI Device 18h IDs for AMD Family 19h systems. Note that Family 19h systems will not have a new PCI root device ID. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200110015651.14887-4-Yazen.Ghannam@amd.com
2020-01-16x86/MCE/AMD, EDAC/mce_amd: Add new Load Store unit McaTypeYazen Ghannam
Add support for a new version of the Load Store unit bank type as indicated by its McaType value, which will be present in future SMCA systems. Add the new (HWID, MCATYPE) tuple. Reuse the same name, since this is logically the same to the user. Also, add the new error descriptions to edac_mce_amd. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200110015651.14887-2-Yazen.Ghannam@amd.com
2020-01-16arm64: Implement optimised checksum routineRobin Murphy
Apparently there exist certain workloads which rely heavily on software checksumming, for which the generic do_csum() implementation becomes a significant bottleneck. Therefore let's give arm64 its own optimised version - for ease of maintenance this foregoes assembly or intrisics, and is thus not actually arm64-specific, but does rely heavily on C idioms that translate well to the A64 ISA and the typical load/store capabilities of most ARMv8 CPU cores. The resulting increase in checksum throughput scales nicely with buffer size, tending towards 4x for a small in-order core (Cortex-A53), and up to 6x or more for an aggressive big core (Ampere eMAG). Reported-by: Lingyan Huang <huanglingyan2@huawei.com> Tested-by: Lingyan Huang <huanglingyan2@huawei.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16ARM: dts: at91: sam9x60: add device tree for soc and boardSandeep Sheriker Mallikarjun
Add device tree files for SAM9X60 SoC and SAM9X60-EK board. Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/1579085987-13976-6-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-01-16arm64: context: Free up kernel ASIDs if KPTI is not in useVladimir Murzin
We can extend user ASID space if it turns out that system does not require KPTI. We start with kernel ASIDs reserved because CPU caps are not finalized yet and free them up lazily on the next rollover if we confirm than KPTI is not in use. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16arm64: Workaround for Cortex-A55 erratum 1530923Steven Price
Cortex-A55 erratum 1530923 allows TLB entries to be allocated as a result of a speculative AT instruction. This may happen in the middle of a guest world switch while the relevant VMSA configuration is in an inconsistent state, leading to erroneous content being allocated into TLBs. The same workaround as is used for Cortex-A76 erratum 1165522 (WORKAROUND_SPECULATIVE_AT_VHE) can be used here. Note that this mandates the use of VHE on affected parts. Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Steven Price <steven.price@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16arm64: Rename WORKAROUND_1319367 to SPECULATIVE_AT_NVHESteven Price
To match SPECULATIVE_AT_VHE let's also have a generic name for the NVHE variant. Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Steven Price <steven.price@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16arm64: Rename WORKAROUND_1165522 to SPECULATIVE_AT_VHESteven Price
Cortex-A55 is affected by a similar erratum, so rename the existing workaround for errarum 1165522 so it can be used for both errata. Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Steven Price <steven.price@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-16crypto: {arm,arm64,mips}/poly1305 - remove redundant non-reduction from emitJason A. Donenfeld
This appears to be some kind of copy and paste error, and is actually dead code. Pre: f = 0 ⇒ (f >> 32) = 0 f = (f >> 32) + le32_to_cpu(digest[0]); Post: 0 ≤ f < 2³² put_unaligned_le32(f, dst); Pre: 0 ≤ f < 2³² ⇒ (f >> 32) = 0 f = (f >> 32) + le32_to_cpu(digest[1]); Post: 0 ≤ f < 2³² put_unaligned_le32(f, dst + 4); Pre: 0 ≤ f < 2³² ⇒ (f >> 32) = 0 f = (f >> 32) + le32_to_cpu(digest[2]); Post: 0 ≤ f < 2³² put_unaligned_le32(f, dst + 8); Pre: 0 ≤ f < 2³² ⇒ (f >> 32) = 0 f = (f >> 32) + le32_to_cpu(digest[3]); Post: 0 ≤ f < 2³² put_unaligned_le32(f, dst + 12); Therefore this sequence is redundant. And Andy's code appears to handle misalignment acceptably. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Tested-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-01-16crypto: x86/poly1305 - wire up faster implementations for kernelJason A. Donenfeld
These x86_64 vectorized implementations support AVX, AVX-2, and AVX512F. The AVX-512F implementation is disabled on Skylake, due to throttling, but it is quite fast on >= Cannonlake. On the left is cycle counts on a Core i7 6700HQ using the AVX-2 codepath, comparing this implementation ("new") to the implementation in the current crypto api ("old"). On the right are benchmarks on a Xeon Gold 5120 using the AVX-512 codepath. The new implementation is faster on all benchmarks. AVX-2 AVX-512 --------- ----------- size old new size old new ---- ---- ---- ---- ---- ---- 0 70 68 0 74 70 16 92 90 16 96 92 32 134 104 32 136 106 48 172 120 48 184 124 64 218 136 64 218 138 80 254 158 80 260 160 96 298 174 96 300 176 112 342 192 112 342 194 128 388 212 128 384 212 144 428 228 144 420 226 160 466 246 160 464 248 176 510 264 176 504 264 192 550 282 192 544 282 208 594 302 208 582 300 224 628 316 224 624 318 240 676 334 240 662 338 256 716 354 256 708 358 272 764 374 272 748 372 288 802 352 288 788 358 304 420 366 304 422 370 320 428 360 320 432 364 336 484 378 336 486 380 352 426 384 352 434 390 368 478 400 368 480 408 384 488 394 384 490 398 400 542 408 400 542 412 416 486 416 416 492 426 432 534 430 432 538 436 448 544 422 448 546 432 464 600 438 464 600 448 480 540 448 480 548 456 496 594 464 496 594 476 512 602 456 512 606 470 528 656 476 528 656 480 544 600 480 544 606 498 560 650 494 560 652 512 576 664 490 576 662 508 592 714 508 592 716 522 608 656 514 608 664 538 624 708 532 624 710 552 640 716 524 640 720 516 656 770 536 656 772 526 672 716 548 672 722 544 688 770 562 688 768 556 704 774 552 704 778 556 720 826 568 720 832 568 736 768 574 736 780 584 752 822 592 752 826 600 768 830 584 768 836 560 784 884 602 784 888 572 800 828 610 800 838 588 816 884 628 816 884 604 832 888 618 832 894 598 848 942 632 848 946 612 864 884 644 864 896 628 880 936 660 880 942 644 896 948 652 896 952 608 912 1000 664 912 1004 616 928 942 676 928 954 634 944 994 690 944 1000 646 960 1002 680 960 1008 646 976 1054 694 976 1062 658 992 1002 706 992 1012 674 1008 1052 720 1008 1058 690 This commit wires in the prior implementation from Andy, and makes the following changes to be suitable for kernel land. - Some cosmetic and structural changes, like renaming labels to .Lname, constants, and other Linux conventions, as well as making the code easy for us to maintain moving forward. - CPU feature checking is done in C by the glue code. - We avoid jumping into the middle of functions, to appease objtool, and instead parameterize shared code. - We maintain frame pointers so that stack traces make sense. - We remove the dependency on the perl xlate code, which transforms the output into things that assemblers we don't care about use. Importantly, none of our changes affect the arithmetic or core code, but just involve the differing environment of kernel space. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Samuel Neves <sneves@dei.uc.pt> Co-developed-by: Samuel Neves <sneves@dei.uc.pt> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-01-16crypto: x86/poly1305 - import unmodified cryptogams implementationJason A. Donenfeld
These x86_64 vectorized implementations come from Andy Polyakov's CRYPTOGAMS implementation, and are included here in raw form without modification, so that subsequent commits that fix these up for the kernel can see how it has changed. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-01-16crypto: poly1305 - add new 32 and 64-bit generic versionsJason A. Donenfeld
These two C implementations from Zinc -- a 32x32 one and a 64x64 one, depending on the platform -- come from Andrew Moon's public domain poly1305-donna portable code, modified for usage in the kernel. The precomputation in the 32-bit version and the use of 64x64 multiplies in the 64-bit version make these perform better than the code it replaces. Moon's code is also very widespread and has received many eyeballs of scrutiny. There's a bit of interference between the x86 implementation, which relies on internal details of the old scalar implementation. In the next commit, the x86 implementation will be replaced with a faster one that doesn't rely on this, so none of this matters much. But for now, to keep this passing the tests, we inline the bits of the old implementation that the x86 implementation relied on. Also, since we now support a slightly larger key space, via the union, some offsets had to be fixed up. Nonce calculation was folded in with the emit function, to take advantage of 64x64 arithmetic. However, Adiantum appeared to rely on no nonce handling in emit, so this path was conditionalized. We also introduced a new struct, poly1305_core_key, to represent the precise amount of space that particular implementation uses. Testing with kbench9000, depending on the CPU, the update function for the 32x32 version has been improved by 4%-7%, and for the 64x64 by 19%-30%. The 32x32 gains are small, but I think there's great value in having a parallel implementation to the 64x64 one so that the two can be compared side-by-side as nice stand-alone units. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-01-16Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Herbert Xu
Merge crypto tree to pick up hisilicon patch.
2020-01-16powerpc/64s: Reimplement power4_idle code in CNicholas Piggin
This implements the tricky tracing and soft irq handling bits in C, leaving the low level bit to asm. A functional difference is that this redirects the interrupt exit to a return stub to execute blr, rather than the lr address itself. This is probably barely measurable on real hardware, but it keeps the link stack balanced. Tested with QEMU. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Move power4_fixup_nap back into exceptions-64s.S] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190711022404.18132-1-npiggin@gmail.com
2020-01-16powerpc: Remove STRICT_KERNEL_RWX incompatibility with RELOCATABLERussell Currey
I have tested this with the Radix MMU and everything seems to work, and the previous patch for Hash seems to fix everything too. STRICT_KERNEL_RWX should still be disabled by default for now. Please test STRICT_KERNEL_RWX + RELOCATABLE! Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20191224064126.183670-2-ruscur@russell.cc
2020-01-16powerpc/book3s64/hash: Disable 16M linear mapping size if not alignedRussell Currey
With STRICT_KERNEL_RWX on in a relocatable kernel under the hash MMU, if the position the kernel is loaded at is not 16M aligned things go horribly wrong. Specifically hash__mark_initmem_nx() will call hash__change_memory_range() which then aligns down the start address, and due to the text not being 16M aligned causes some of the kernel text to be marked non-executable. We can avoid this when selecting the linear mapping size, so do so and print a warning. I tested this for various alignments and as long as the position is 64K aligned it's fine (the base requirement for powerpc). Signed-off-by: Russell Currey <ruscur@russell.cc> [mpe: Add details of the failure mode] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20191224064126.183670-1-ruscur@russell.cc
2020-01-15riscv: make sure the cores stay looping in .Lsecondary_parkGreentime Hu
The code in secondary_park is currently placed in the .init section. The kernel reclaims and clears this code when it finishes booting. That causes the cores parked in it to go to somewhere unpredictable, so we move this function out of init to make sure the cores stay looping there. The instruction bgeu a0, t0, .Lsecondary_park may have "a relocation truncated to fit" issue during linking time. It is because that sections are too far to jump. Let's use tail to jump to the .Lsecondary_park. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Anup Patel <anup.patel@sifive.com> Cc: Andreas Schwab <schwab@suse.de> Cc: stable@vger.kernel.org Fixes: 76d2a0493a17d ("RISC-V: Init and Halt Code") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2020-01-15ARC: wireup clone3 syscallVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2020-01-15ARM: dts: bcm2711: Enable PCIe controllerNicolas Saenz Julienne
This enables bcm2711's PCIe bus, which is hardwired to a VIA Technologies XHCI USB 3.0 controller. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-15ARM: dts: bcm283x: Unify CMA configurationNicolas Saenz Julienne
With the introduction of the Raspberry Pi 4 we were forced to explicitly configure CMA's location, since arm64 defaults it into the ZONE_DMA32 memory area, which is not good enough to perform DMA operations on that device. To bypass this limitation a dedicated CMA DT node was created, explicitly indicating the acceptable memory range and size. That said, compatibility between boards is a must on the Raspberry Pi ecosystem so this creates a common CMA DT node so as for DT overlays to be able to update CMA's properties regardless of the board being used. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Phil Elwell <phil@raspberrypi.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-15MIPS: CU1000-Neo: Refresh defconfig to support HWMON and WiFi.周琰杰 (Zhou Yanjie)
Refresh CU1000-Neo's defconfig to support ADS7830 based HWMON and AP6212A WiFi module. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: robh+dt@kernel.org Cc: paul.burton@mips.com Cc: jhogan@kernel.org Cc: mark.rutland@arm.com Cc: syq@debian.org Cc: ralf@linux-mips.org Cc: rick.tyliu@ingenic.com Cc: jason@lakedaemon.net Cc: keescook@chromium.org Cc: geert+renesas@glider.be Cc: krzk@kernel.org Cc: paul@crapouillou.net Cc: prasannatsmkumar@gmail.com Cc: sernia.zhou@foxmail.com Cc: zhenwenjin@gmail.com Cc: ebiederm@xmission.com
2020-01-15MIPS: Ingenic: Add missing nodes for X1000 and CU1000-Neo.周琰杰 (Zhou Yanjie)
Add I2C0/I2C1/I2C2 nodes for X1000 and add I2C0, ADS7830, MSC1, AP6212A, wlan_pwrseq nodes for CU1000-Neo. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: robh+dt@kernel.org Cc: paul.burton@mips.com Cc: jhogan@kernel.org Cc: mark.rutland@arm.com Cc: syq@debian.org Cc: ralf@linux-mips.org Cc: rick.tyliu@ingenic.com Cc: jason@lakedaemon.net Cc: keescook@chromium.org Cc: geert+renesas@glider.be Cc: krzk@kernel.org Cc: paul@crapouillou.net Cc: prasannatsmkumar@gmail.com Cc: sernia.zhou@foxmail.com Cc: zhenwenjin@gmail.com Cc: ebiederm@xmission.com
2020-01-15mips/vdso: Support mremap() for vDSOGuoyun Sun
vDSO VMA address is saved in mm_context for the purpose of using restorer from vDSO page to return to userspace after signal handling. In Checkpoint Restore in Userspace (CRIU) project we place vDSO VMA on restore back to the place where it was on the dump. Make vDSO code track the VMA address by supplying .mremap() fops the same way it's done for x86 and arm by: commit b059a453b1cf ("x86/vdso: Add mremap hook to vm_special_mapping") commit 739586951b8a ("arm64/vdso: Support mremap() for vDSO"). Signed-off-by: Guoyun Sun <sunguoyun@loongson.cn> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Allison Randal <allison@lohutok.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2020-01-15arm64: Use register field helper in kaslr_requires_kpti()Will Deacon
Rather than open-code the extraction of the E0PD field from the MMFR2 register, we can use the cpuid_feature_extract_unsigned_field() helper instead. Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-15arm64: Simplify early check for broken TX1 when KASLR is enabledWill Deacon
Now that the decision to use non-global mappings is stored in a variable, the check to avoid enabling them for the terminally broken ThunderX1 platform can be simplified so that it is only keyed off the MIDR value. Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-15arm64: Turn "broken gas inst" into real config optionVladimir Murzin
Use the new 'as-instr' Kconfig macro to define CONFIG_BROKEN_GAS_INST directly, making it available everywhere. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> [will: Drop redundant 'y if' logic] Signed-off-by: Will Deacon <will@kernel.org>
2020-01-15arm64: Use a variable to store non-global mappings decisionMark Brown
Refactor the code which checks to see if we need to use non-global mappings to use a variable instead of checking with the CPU capabilities each time, doing the initial check for KPTI early in boot before we start allocating memory so we still avoid transitioning to non-global mappings in common cases. Since this variable always matches our decision about non-global mappings this means we can also combine arm64_kernel_use_ng_mappings() and arm64_unmap_kernel_at_el0() into a single function, the variable simply stores the result and the decision code is elsewhere. We could just have the users check the variable directly but having a function makes it clear that these uses are read-only. The result is that we simplify the code a bit and reduces the amount of code executed at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-15arm64: Don't use KPTI where we have E0PDMark Brown
Since E0PD is intended to fulfil the same role as KPTI we don't need to use KPTI on CPUs where E0PD is available, we can rely on E0PD instead. Change the check that forces KPTI on when KASLR is enabled to check for E0PD before doing so, CPUs with E0PD are not expected to be affected by meltdown so should not need to enable KPTI for other reasons. Since E0PD is a system capability we will still enable KPTI if any of the CPUs in the system lacks E0PD, this will rewrite any global mappings that were established in systems where some but not all CPUs support E0PD. We may transiently have a mix of global and non-global mappings while booting since we use the local CPU when deciding if KPTI will be required prior to completing CPU enumeration but any global mappings will be converted to non-global ones when KPTI is applied. KPTI can still be forced on from the command line if required. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-15arm64: Factor out checks for KASLR in KPTI code into separate functionMark Brown
In preparation for integrating E0PD support with KASLR factor out the checks for interaction between KASLR and KPTI done in boot context into a new function kaslr_requires_kpti(), in the process clarifying the distinction between what we do in boot context and what we do at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-16 12:53:11 +0000