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2020-01-08ARM: dts: aspeed: rainier: Fix fan fault and presenceBrandon Wyman
The PCA9552 used for fan fault and presence information is at address 61h, not 60h. Fixes: 2efc118ce3c3 ("ARM: dts: aspeed: rainier: Add i2c devices") Signed-off-by: Brandon Wyman <bjwyman@gmail.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-08ARM: dts: aspeed: rainier: Remove duplicate i2c bussesJoel Stanley
This is a revert of "ARM: dts: aspeed: rainier: Add i2c devices", which was already applied to the tree. Fixes: 9c44db7096e0 ("ARM: dts: aspeed: rainier: Add i2c devices") Reviewed-by: Jim Wright <wrightj@linux.vnet.ibm.com> Tested-by: Jim Wright <wrightj@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-08ARM: dts: aspeed: tacoma: Remove duplicate flash nodesJoel Stanley
This is a revert of "ARM: dts: aspeed: tacoma: Enable FMC and SPI devices" which was already applied as part of "ARM: dts: aspeed: Add Tacoma machine". Fixes: 8737481e381c ("ARM: dts: aspeed: tacoma: Enable FMC and SPI devices") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-08ARM: dts: aspeed: tacoma: Remove duplicate i2c bussesJoel Stanley
This is a revert of "ARM: dts: aspeed: tacoma: Enable I2C busses", which was already applied as part of "ARM: dts: aspeed: Add Tacoma machine". Fixes: 606bcdde6724 ("ARM: dts: aspeed: tacoma: Enable I2C busses") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-08ARM: dts: aspeed: tacoma: Fix fsi master nodeJoel Stanley
This was broken when applying "ARM: dts: aspeed: tacoma: Add host FSI description". Fixes: a981c93300ef ("ARM: dts: aspeed: tacoma: Add host FSI description") Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-08ARM: dts: aspeed-g6: Fix FSI master locationJoel Stanley
The FIS nodes were placed incorrectly in the device tree. Fixes: 0fe4e304782c ("ARM: dts: aspeed-g6: Describe FSI masters") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-07arm64: dts: apq8096-db820c: Fix VDD core voltageLoic Poulain
APQ8096 has its VDD APC (Power for quad Kryo applications microprocessors) powered by PM8996 PMIC S9, S10, S11 tri-phase regulators (gang). The bootloader may have configured these regulators with non sustainable default values, leading to sporadic hangs under CPU stress tests (cpufreq-bench). Ideally we should enable voltage scaling along with frequency scaling, but for now just set the regulator gang value to a sane voltage, capable of supporting highest frequencies (turbo). Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1578401755-26211-1-git-send-email-loic.poulain@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07arm64: dts: qcom: qcs404-evb: Set vdd_apc regulator in high power modeNiklas Cassel
vdd_apc is the regulator that supplies the main CPU cluster. At sudden CPU load changes, we have noticed invalid page faults on addresses with all bits shifted, as well as on addresses with individual bits flipped. By putting the vdd_apc regulator in high power mode, the voltage drops during sudden load changes will be less severe, and we have not been able to reproduce the invalid page faults with the regulator in this mode. Fixes: 8faea8edbb35 ("arm64: dts: qcom: qcs404-evb: add spmi regulators") Cc: stable@vger.kernel.org Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20191014120920.12691-1-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07arm64: dts: qcom: msm8998-mtp: Add alias for blsp1_uart3Bjorn Andersson
The msm_serial driver has a predefined set of uart ports defined, which is allocated either by reading aliases or if no match is found a simple counter, starting at index 0. But there's no logic in place to prevent these two allocation mechanism from colliding. As a result either none or all of the active msm_serial instances must be listed as aliases. Define blsp1_uart3 as "serial1" to mitigate this problem. Fixes: 4cffb9f2c700 ("arm64: dts: qcom: msm8998-mtp: Enable bluetooth") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20191119011823.379100-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07arm64: dts: rockchip: rk3399-hugsun-x99: remove supports-sd and ↵Johan Jonker
supports-emmc options The entries "supports-sd" and "supports-emmc" are not a valid Linux option in relation with SD card or eMMC, so remove them. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20191231175054.4929-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-07arm64: dts: rockchip: rk3399-firefly: remove num-slots from &sdio0 nodeJohan Jonker
The option "num-slots" was deprecated long time ago, so remove it. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20191231191154.5587-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-07ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tigerMatthias Kaehlcke
The flash write protect pin is currently named 'FW_WP_AP', which is how the signal is called in the schematics. The Chrome OS ABI requires the pin to be named 'AP_FLASH_WP_L', which is also how it is called on all other veyron devices. Rename the pin to match the ABI. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200106135142.1.I3f99ac8399a564c88ff48ae6290cc691b47c16ae@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-07ARM: dts: samsung: Rename Samsung and Exynos to lowercaseKrzysztof Kozlowski
Fix up inconsistent usage of upper and lowercase letters in "Samsung" and "Exynos" names. "SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked names. Therefore they should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Although advertisement materials usually use uppercase "SAMSUNG", the lowercase version is used in all legal aspects (e.g. on Wikipedia and in privacy/legal statements on https://www.samsung.com/semiconductor/privacy-global/). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-01-07ARM: samsung: Rename Samsung and Exynos to lowercaseKrzysztof Kozlowski
Fix up inconsistent usage of upper and lowercase letters in "Samsung" and "Exynos" names. "SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked names. Therefore they should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Although advertisement materials usually use uppercase "SAMSUNG", the lowercase version is used in all legal aspects (e.g. on Wikipedia and in privacy/legal statements on https://www.samsung.com/semiconductor/privacy-global/). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-01-07ARM: exynos: Correct the help text for platform Kconfig optionKrzysztof Kozlowski
ARCH_EXYNOS option is used for entire ARMv7 Exynos family, including also Exynos3 SoCs. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-01-07Merge tag 'omap-for-v5.6/ti-sysc-drop-pdata-signed' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Drop more legacy platform data for omaps for v5.6 merge window We can now probe devices with ti-sysc interconnect driver and dts data, and can continue dropping the related platform data and custom ti,hwmods dts property for various devices. And related to that, we finally can remove the legacy sdma support in favor of using the dmaengine driver only. I was planning to send the sdma changes separately, but that would have produced a pile of pointless merge conflicts, so I decided it's best to resolve it locally. After all, the sdma series also ends up removing the related platform data. Note that this series is based on omap-for-v5.6/ti-sysc-dt-signed branch as it depends for dts data being in place. * tag 'omap-for-v5.6/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (56 commits) ARM: OMAP2+: Drop legacy platform data for sdma ARM: OMAP2+: Drop legacy init for sdma dmaengine: ti: omap-dma: Use cpu notifier to block idle for omap2 dmaengine: ti: omap-dma: Allocate channels directly dmaengine: ti: omap-dma: Pass sdma auxdata to driver and use it dmaengine: ti: omap-dma: Configure global priority register directly ARM: OMAP5: hwmod-data: remove OMAP5 IOMMU hwmod data ARM: OMAP4: hwmod-data: remove OMAP4 IOMMU hwmod data ARM: OMAP2+: Drop legacy platform data for omap4 fdif ARM: OMAP2+: Drop legacy platform data for omap4 slimbus ARM: OMAP2+: Drop legacy platform data for omap5 kbd ARM: OMAP2+: Drop legacy platform data for omap4 kbd ARM: OMAP2+: Drop legacy platform data for dra7 smartreflex ARM: OMAP2+: Drop legacy platform data for omap4 smartreflex ARM: OMAP2+: Drop legacy platform data for omap4 hsi ARM: OMAP2+: Drop legacy platform data for am4 vpfe ARM: OMAP2+: Drop legacy platform data for dra7 ocp2scp ARM: OMAP2+: Drop legacy platform data for omap5 ocp2scp ARM: OMAP2+: Drop legacy platform data for omap4 ocp2scp ARM: OMAP2+: Drop legacy platform data for am4 ocp2scp ... Link: https://lore.kernel.org/r/pull-1578420398-290837@atomide.com-4 Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07Merge branch 'omap/soc' into arm/dtOlof Johansson
Bringing in to resolve soc -> add/add conflicts locally * omap/soc: ARM: OMAP2+: use separate IOMMU pdata to fix DRA7 IPU1 boot ARM: OMAP2+: omap-iommu.c conversion to ti-sysc ARM: OMAP2+: Add workaround for DRA7 DSP MStandby errata i879 ARM: OMAP4+: remove pdata quirks for omap4+ iommus ARM: OMAP2+: pdata-quirks: add PRM data for reset support ARM: OMAP2+: am43xx: Add lcdc clockdomain Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07Merge tag 'omap-for-v5.6/ti-sysc-dt-signed' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt dts changes for omaps for ti-sysc driver for v5.6 merge window Devicetree changes for omaps to configure more devices to probe with ti-sysc interconnect target module: - Configure am4 qspi - Configure aes, des and sham accelerators for am3, 4 and dra7 - Configure iommus for omap4, 5 and dra7 - Add a generic compatible for sdma, and configure omap2 and 3 sdma * tag 'omap-for-v5.6/ti-sysc-dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (24 commits) ARM: dts: omap5: convert IOMMUs to use ti-sysc ARM: dts: omap4: convert IOMMUs to use ti-sysc ARM: dts: dra74x: convert IOMMUs to use ti-sysc ARM: dts: dra7: convert IOMMUs to use ti-sysc ARM: dts: Configure interconnect target module for dra7 des ARM: dts: Configure interconnect target module for am4 des ARM: dts: Configure interconnect target module for dra7 aes ARM: dts: Configure interconnect target module for am4 aes ARM: dts: Configure interconnect target module for am3 aes ARM: dts: Configure interconnect target module for dra7 sham ARM: dts: Configure interconnect target module for am4 sham ARM: dts: Configure interconnect target module for am3 sham ARM: dts: Configure interconnect target module for am4 qspi ARM: dts: Configure interconnect target module for omap3 sdma ARM: dts: Configure interconnect target module for omap2 sdma ARM: dts: Add generic compatible for omap sdma instances bus: ti-sysc: Fix iterating over clocks ARM: OMAP2+: Fix ti_sysc_find_one_clockdomain to check for to_clk_hw_omap bus: ti-sysc: Fix missing reset delay handling ARM: dts: am437x-gp/epos-evm: fix panel compatible ... Link: https://lore.kernel.org/r/pull-1578420398-290837@atomide.com-3 Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07Merge tag 'omap-for-v5.6/dt-signed' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes for omaps for v5.6 merge window Devicetree changes for omaps for v5.6 to configure more devices and update boards to use generic lcd panels: - Configure HDMI for dra76-evm and am57xx-idk - Correct node name for am3517 mdio - Convert am335x-evm, am335x-evmsk, and am335x-icev2 to use generic panels * tag 'omap-for-v5.6/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am335x-icev2: Add support for OSD9616P0899-10 at i2c0 ARM: dts: am335x-evmsk: Use drm simple-panel instead of tilcdc-panel ARM: dts: am335x-evm: Use drm simple-panel instead of tilcdc-panel ARM: dts: omap3: name mdio node properly ARM: dts: am57xx-idk-common: add HDMI to the common dtsi ARM: dts: dra76-evm: add HDMI output Link: https://lore.kernel.org/r/pull-1578420398-290837@atomide.com-2 Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07Merge tag 'omap-for-v5.6/soc-signed' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc SoC changes for omaps for v5.6 merge window SoC related changes for omaps that mostly relate to making iommus to start probing with ti-sysc interconnect target module driver: - Add missing lcdc clockdomain for am43xx - Pass auxdata for reset control driver - Remove old pdata quirks for iommus - Add workaround for dra7 dsp mstandby errata - Convert iommu platform code to probe with ti-sysc - Use sperate iommu auxdata for ipu1 * tag 'omap-for-v5.6/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: use separate IOMMU pdata to fix DRA7 IPU1 boot ARM: OMAP2+: omap-iommu.c conversion to ti-sysc ARM: OMAP2+: Add workaround for DRA7 DSP MStandby errata i879 ARM: OMAP4+: remove pdata quirks for omap4+ iommus ARM: OMAP2+: pdata-quirks: add PRM data for reset support ARM: OMAP2+: am43xx: Add lcdc clockdomain Link: https://lore.kernel.org/r/pull-1578420398-290837@atomide.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07Merge tag 'omap-for-v5.5/fixes-rc5' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes Fixes for omaps for v5.5-rc cycle Here are few fixes for v5.5-rc cycle: - Two corner case fixes related to ti-sysc driver clock issues - Fixes for am57xx dts for pcie gpios - Beagle-x15 regulator dts fix - Fix for wkup_m3_ipc driver race * tag 'omap-for-v5.5/fixes-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: soc: ti: wkup_m3_ipc: Fix race condition with rproc_boot ARM: dts: beagle-x15-common: Model 5V0 regulator ARM: dts: am571x-idk: Fix gpios property to have the correct gpio number ARM: dts: am57xx-beagle-x15/am57xx-idk: Remove "gpios" for endpoint dt nodes bus: ti-sysc: Fix iterating over clocks ARM: OMAP2+: Fix ti_sysc_find_one_clockdomain to check for to_clk_hw_omap Link: https://lore.kernel.org/r/pull-1578418121-413328@atomide.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07ARM: dts: bcm2711: Enable HWRNG supportStephen Brennan
This enables hardware random number generator support for the BCM2711 on the Raspberry Pi 4 board. Signed-off-by: Stephen Brennan <stephen@brennan.io> Acked-by: Stefan Wahren <wahrenst@gmx.net> [nsaenzjulienne@suse.de: remove unnecessary status="okay"] Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
2020-01-07ARM: dts: bcm2835: Move rng definition to common locationStephen Brennan
BCM2711 inherits from BCM283X, but has an incompatible HWRNG. Move this node to bcm2835-common.dtsi, so that BCM2711 can define its own. Signed-off-by: Stephen Brennan <stephen@brennan.io> Acked-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
2020-01-07x86/fpu: Deactivate FPU state after failure during state loadSebastian Andrzej Siewior
In __fpu__restore_sig(), fpu_fpregs_owner_ctx needs to be reset if the FPU state was not fully restored. Otherwise the following may happen (on the same CPU): Task A Task B fpu_fpregs_owner_ctx *active* A.fpu __fpu__restore_sig() ctx switch load B.fpu *active* B.fpu fpregs_lock() copy_user_to_fpregs_zeroing() copy_kernel_to_xregs() *modify* copy_user_to_xregs() *fails* fpregs_unlock() ctx switch skip loading B.fpu, *active* B.fpu In the success case, fpu_fpregs_owner_ctx is set to the current task. In the failure case, the FPU state might have been modified by loading the init state. In this case, fpu_fpregs_owner_ctx needs to be reset in order to ensure that the FPU state of the following task is loaded from saved state (and not skipped because it was the previous state). Reset fpu_fpregs_owner_ctx after a failure during restore occurred, to ensure that the FPU state for the next task is always loaded. The problem was debugged-by Yu-cheng Yu <yu-cheng.yu@intel.com>. [ bp: Massage commit message. ] Fixes: 5f409e20b7945 ("x86/fpu: Defer FPU state load until return to userspace") Reported-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jann Horn <jannh@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com> Cc: Rik van Riel <riel@surriel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: x86-ml <x86@kernel.org> Link: https://lkml.kernel.org/r/20191220195906.plk6kpmsrikvbcfn@linutronix.de
2020-01-07um: Implement copy_thread_tlsAmanieu d'Antras
This is required for clone3 which passes the TLS value through a struct rather than a register. Signed-off-by: Amanieu d'Antras <amanieu@gmail.com> Cc: linux-um@lists.infradead.org Cc: <stable@vger.kernel.org> # 5.3.x Link: https://lore.kernel.org/r/20200104123928.1048822-1-amanieu@gmail.com Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com>
2020-01-07xtensa: Implement copy_thread_tlsAmanieu d'Antras
This is required for clone3 which passes the TLS value through a struct rather than a register. Signed-off-by: Amanieu d'Antras <amanieu@gmail.com> Cc: linux-xtensa@linux-xtensa.org Cc: <stable@vger.kernel.org> # 5.3.x Link: https://lore.kernel.org/r/20200102172413.654385-7-amanieu@gmail.com Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com>
2020-01-07riscv: Implement copy_thread_tlsAmanieu d'Antras
This is required for clone3 which passes the TLS value through a struct rather than a register. Signed-off-by: Amanieu d'Antras <amanieu@gmail.com> Cc: linux-riscv@lists.infradead.org Cc: <stable@vger.kernel.org> # 5.3.x Link: https://lore.kernel.org/r/20200102172413.654385-6-amanieu@gmail.com Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com>
2020-01-07parisc: Implement copy_thread_tlsAmanieu d'Antras
This is required for clone3 which passes the TLS value through a struct rather than a register. Signed-off-by: Amanieu d'Antras <amanieu@gmail.com> Cc: linux-parisc@vger.kernel.org Cc: <stable@vger.kernel.org> # 5.3.x Link: https://lore.kernel.org/r/20200102172413.654385-5-amanieu@gmail.com Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com>
2020-01-07arm: Implement copy_thread_tlsAmanieu d'Antras
This is required for clone3 which passes the TLS value through a struct rather than a register. Signed-off-by: Amanieu d'Antras <amanieu@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: <stable@vger.kernel.org> # 5.3.x Link: https://lore.kernel.org/r/20200102172413.654385-4-amanieu@gmail.com Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com>
2020-01-07arm64: Implement copy_thread_tlsAmanieu d'Antras
This is required for clone3 which passes the TLS value through a struct rather than a register. Signed-off-by: Amanieu d'Antras <amanieu@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: <stable@vger.kernel.org> # 5.3.x Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20200102172413.654385-3-amanieu@gmail.com Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com>
2020-01-07arm64: Move __ARCH_WANT_SYS_CLONE3 definition to uapi headersAmanieu d'Antras
Previously this was only defined in the internal headers which resulted in __NR_clone3 not being defined in the user headers. Signed-off-by: Amanieu d'Antras <amanieu@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: <stable@vger.kernel.org> # 5.3.x Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200102172413.654385-2-amanieu@gmail.com Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com>
2020-01-07powerpc/mpc85xx: also write addr_h to spin table for 64bit boot entryBai Yingjie
CPU like P4080 has 36bit physical address, its DDR physical start address can be configured above 4G by LAW registers. For such systems in which their physical memory start address was configured higher than 4G, we need also to write addr_h into the spin table of the target secondary CPU, so that addr_h and addr_l together represent a 64bit physical address. Otherwise the secondary core can not get correct entry to start from. Signed-off-by: Bai Yingjie <byj.tea@gmail.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200106042957.26494-2-yingjie_bai@126.com
2020-01-07powerpc32/booke: consistently return phys_addr_t in __pa()Bai Yingjie
When CONFIG_RELOCATABLE=y is set, VIRT_PHYS_OFFSET is a 64bit variable, thus __pa() returns as 64bit value. But when CONFIG_RELOCATABLE=n, __pa() returns 32bit value. When CONFIG_PHYS_64BIT is set, __pa() should consistently return as 64bit value irrelevant to CONFIG_RELOCATABLE. So we'd make __pa() consistently return phys_addr_t, which is 64bit when CONFIG_PHYS_64BIT is set. Signed-off-by: Bai Yingjie <byj.tea@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200106042957.26494-1-yingjie_bai@126.com
2020-01-07powerpc/powernv: use resource_sizeJulia Lawall
Use resource_size rather than a verbose computation on the end and start fields. The semantic patch that makes these changes is as follows: (http://coccinelle.lip6.fr/) <smpl> @@ struct resource ptr; @@ - (ptr.end - ptr.start + 1) + resource_size(&ptr) </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1577900990-8588-11-git-send-email-Julia.Lawall@inria.fr
2020-01-07powerpc/83xx: use resource_sizeJulia Lawall
Use resource_size rather than a verbose computation on the end and start fields. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) <smpl> @@ struct resource ptr; @@ - (ptr.end - ptr.start + 1) + resource_size(&ptr) </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1577900990-8588-6-git-send-email-Julia.Lawall@inria.fr
2020-01-07powerpc/mpic: constify copied structureJulia Lawall
The mpic_ipi_chip and mpic_irq_ht_chip structures are only copied into other structures, so make them const. The opportunity for this change was found using Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1577864614-5543-10-git-send-email-Julia.Lawall@inria.fr
2020-01-07x86/unwind/orc: Fix !CONFIG_MODULES build warningShile Zhang
To fix follwowing warning due to ORC sort moved to build time: arch/x86/kernel/unwind_orc.c:210:12: warning: ‘orc_sort_cmp’ defined but not used [-Wunused-function] arch/x86/kernel/unwind_orc.c:190:13: warning: ‘orc_sort_swap’ defined but not used [-Wunused-function] Signed-off-by: Shile Zhang <shile.zhang@linux.alibaba.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/c9c81536-2afc-c8aa-c5f8-c7618ecd4f54@linux.alibaba.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2020-01-07x86/context-tracking: Remove exception_enter/exit() from ↵Frederic Weisbecker
KVM_PV_REASON_PAGE_NOT_PRESENT async page fault This is a leftover. Page faults, just like most other exceptions, are protected inside user_exit() / user_enter() calls in x86 entry code when we fault from userspace. So this pair of calls is now superfluous. Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Jim Mattson <jmattson@google.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Sean Christopherson <sean.j.christopherson@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vitaly Kuznetsov <vkuznets@redhat.com> Cc: Wanpeng Li <wanpengli@tencent.com> Link: https://lkml.kernel.org/r/20191227163612.10039-3-frederic@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2020-01-07x86/context-tracking: Remove exception_enter/exit() from do_page_fault()Frederic Weisbecker
do_page_fault(), like other exceptions, is already covered by user_enter() and user_exit() when the exception triggers in userspace. As explained in: 8c84014f3bbb11 ("x86/entry: Remove exception_enter() from most trap handlers") exception_enter/exit() only remained to handle possible page fault from kernel mode while context tracking is in CONTEXT_USER mode, ie: on kernel entry before we manage to call user_exit(). The only known offender was do_fast_syscall_32() fetching EBP register from where vDSO stashed it. Meanwhile this got fixed in: 9999c8c01f34c9 ("x86/entry: Call enter_from_user_mode() with IRQs off") that moved enter_from_user_mode() before the call to get_user(). So we can safely remove it now. Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Jim Mattson <jmattson@google.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Sean Christopherson <sean.j.christopherson@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vitaly Kuznetsov <vkuznets@redhat.com> Cc: Wanpeng Li <wanpengli@tencent.com> Link: https://lkml.kernel.org/r/20191227163612.10039-2-frederic@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2020-01-06arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS ↵Rajeshwari
in SC7180 Added critical interrupt support in TSENS node and cooling maps in Thermal-zones node. Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Rajeshwari <rkambl@codeaurora.org> Link: https://lore.kernel.org/r/1578317369-16045-2-git-send-email-rkambl@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-06arm64: dts: allwinner: sun50i-a64: Use macros for newly exported clocksChen-Yu Tsai
A few clocks from the CCU were exported later, and references to them in the device tree were using raw numbers. Now that the DT binding header changes are in as well, switch to the macros for more clarity. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06ARM: dts: sunxi: Use macros for references to CCU clocksChen-Yu Tsai
A few clocks from the CCU were exported later, and references to them in the device tree were using raw numbers. Now that the DT binding header changes are in as well, switch to the macros for more clarity. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06arm64: dts: allwinner: h5: Add Libre Computer ALL-H5-CC H5 boardChen-Yu Tsai
The Libre Computer ALL-H5-CC board is an upgraded version of the ALL-H3-CC. Changes include: - Gigabit Ethernet via external RTL8211E Ethernet PHY - 16 MiB SPI NOR flash memory - PoE tap header - Line out jack removed Only H5 variant test samples were made available, and the vendor is not certain whether other SoC variants would be made or not. Furthermore the board is a minor upgrade compared to the ALL-H3-CC. Thus the device tree simply includes the one for the ALL-H3-CC, and adds the changes on top. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxesAndre Przywara
The Allwinner R40 SoC contains four SPI controllers, using the newer sun6i design (but at the legacy addresses). The controller seems to be fully compatible to the A64 one, so no driver changes are necessary. The first three controllers can be used on two sets of pins, but SPI3 is only routed to one set on Port A. Only the pin groups for SPI0 on PortC and SPI1 on PortI are added here, because those seem to be the only one exposed on the Bananapi boards. Tested by connecting a SPI flash to a Bananapi M2 Berry SPI0 and SPI1 header pins. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06Merge branch 'mmp/hsic' into arm/dtOlof Johansson
* mmp/hsic: ARM: dts: mmp3: Fix typos
2020-01-06ARM: dts: mmp3: Fix typosOlof Johansson
Fixes build failures due to syntax errors. Fixes: 3240d5b872f2 ("ARM: dts: mmp3: Add HSIC controllers") Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06arm64: dts: qcom: msm8996: Fix venus iommu nodename errorStanimir Varbanov
Fix the following error/warn seen with make dtbs_check arm,smmu-venus@d40000: $nodename:0: 'arm,smmu-venus@d40000' does not match '^iommu@[0-9a-f]*' arm,smmu-venus@d40000: clock-names:0: 'bus' was expected arm,smmu-venus@d40000: clock-names:1: 'iface' was expected by rename nodename to "iommu". Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Link: https://lore.kernel.org/r/20200106102305.27059-1-stanimir.varbanov@linaro.org [bjorn: Added padding of address to 8 digits] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-06Merge tag 'arc-5.5-rc6' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC fixes from Vineet Gupta: "Kconfig warning, stale define, duplicate asm-offset entry ..." * tag 'arc-5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: pt_regs: remove hardcoded registers offset ARC: asm-offsets: remove duplicate entry ARC: mm: drop stale define of __ARCH_USE_5LEVEL_HACK arc: eznps: fix allmodconfig kconfig warning
2020-01-06arm64: Revert support for execute-only user mappingsCatalin Marinas
The ARMv8 64-bit architecture supports execute-only user permissions by clearing the PTE_USER and PTE_UXN bits, practically making it a mostly privileged mapping but from which user running at EL0 can still execute. The downside, however, is that the kernel at EL1 inadvertently reading such mapping would not trip over the PAN (privileged access never) protection. Revert the relevant bits from commit cab15ce604e5 ("arm64: Introduce execute-only page access permissions") so that PROT_EXEC implies PROT_READ (and therefore PTE_USER) until the architecture gains proper support for execute-only user mappings. Fixes: cab15ce604e5 ("arm64: Introduce execute-only page access permissions") Cc: <stable@vger.kernel.org> # 4.9.x- Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2020-01-06x86/fpu/xstate: Make xfeature_is_supervisor()/xfeature_is_user() return boolYu-cheng Yu
Have both xfeature_is_supervisor()/xfeature_is_user() return bool because they are used only in boolean context. Suggested-by: Borislav Petkov <bp@suse.de> Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com> Cc: Rik van Riel <riel@surriel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: x86-ml <x86@kernel.org> Link: https://lkml.kernel.org/r/20191212210855.19260-3-yu-cheng.yu@intel.com