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2016-05-11powerpc/mm: Add radix support for hugetlbAneesh Kumar K.V
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: Fix vma_mmu_pagesize() for radixAneesh Kumar K.V
Radix doesn't use the slice framework to find the page size. Hence use vma to find the page size. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: pte_frag abstractionAneesh Kumar K.V
In this patch we make the number of pte fragments per level 4 page table page a variable. Radix level 4 table size is 256 bytes and hence we can have 256 fragments per level 4 page. We don't update the fragment count in this patch. We need to do performance measurements to find the right value for fragment count. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/radix: Update MMU cacheAneesh Kumar K.V
With radix there is no MMU cache. Hence we don't need to do anything in update_mmu_cache(). Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: vmalloc abstraction in preparation for radixAneesh Kumar K.V
The vmalloc range differs between hash and radix config. Hence make VMALLOC_START and related constants a variable which will be runtime initialized depending on whether hash or radix mode is active. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [mpe: Fix missing init of ioremap_bot in pgtable_64.c for ppc64e] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: Update pte filter for radixAneesh Kumar K.V
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: Add radix pgalloc detailsAneesh Kumar K.V
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: Make 4K and 64K use pte_t for pgtable_tAneesh Kumar K.V
This patch switches 4K Linux page size config to use pte_t * type instead of struct page * for pgtable_t. This simplifies the code a lot and helps in consolidating both 64K and 4K page allocator routines. The changes should not have any impact, because we already store physical address in the upper level page table tree and that implies we already do struct page * to physical address conversion. One change to note here is we move the pgtable_page_dtor() call for nohash to pte_fragment_free_mm(). The nohash related change is due to the related changes in pgtable_64.c. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: Rename function to indicate we are allocating fragmentsAneesh Kumar K.V
Only code cleanup. No functionality change. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: Simplify the code dropping 4-level table #ifdefAneesh Kumar K.V
Simplify the code by dropping 4-level page table #ifdef. We are always 4-level now. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: Revert changes made to nohash pgalloc-64.hAneesh Kumar K.V
This reverts pgalloc related changes WRT implementing 4-level page table for 64K Linux page size and storing of physical address in higher level page tables since they are only applicable to book3s64 variant and we now have a separate copy for book3s64. This helps to keep these headers simpler. Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: Copy pgalloc (part 2)Aneesh Kumar K.V
This moves the nohash variant of pgalloc headers to nohash/ directory Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: Make a copy of pgalloc.h for 32 and 64 book3sAneesh Kumar K.V
This patch start to make a book3s variant for pgalloc headers. We have multiple book3s specific changes such as: * 4 level page table * store physical address in higher level table * use pte_t * for pgtable_t Having a book3s64 specific variant helps to keep code simpler and remove lots of #ifdef around code. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm/radix: Update PTCR on secondary CPUsAneesh Kumar K.V
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm/radix: Pick the address layout for radix configAneesh Kumar K.V
Hash needs special get_unmapped_area() handling because of limitations around base page size, so we have to set HAVE_ARCH_UNMAPPED_AREA. With radix we don't have such restrictions, so we could use the generic code. But because we've set HAVE_ARCH_UNMAPPED_AREA (for hash), we have to re-implement the same logic as the generic code. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm/radix: Limit paca allocation in radixAneesh Kumar K.V
On return from RTAS we access the paca variables and we have 64 bit disabled. This requires us to limit paca in 32 bit range. Fix this by setting ppc64_rma_size to first_memblock_size/1G range. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm/radix: Add checks in slice code to catch radix usageAneesh Kumar K.V
Radix doesn't need slice support. Catch incorrect usage of slice code when radix is enabled. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm/radix: Isolate hash table function from pseries guest codeAneesh Kumar K.V
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm/radix: Use STD_MMU_64 to properly isolate hash related codeAneesh Kumar K.V
We also use MMU_FTR_RADIX to branch out from code path specific to hash. No functionality change. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11MIPS: do away with ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIBLinus Walleij
This replaces: - "select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB" as this can now be selected directly. - "select ARCH_WANT_OPTIONAL_GPIOLIB" with no dependency: GPIOLIB is now selectable by everyone, so we need not declare our intent to select it. When ordering the symbols the following rationale was used: if the selects were in alphabetical order, I moved select GPIOLIB to be in alphabetical order, but if the selects were not maintained in alphabetical order, I just replaced "select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB". Cc: Michael Büsch <m@bues.ch> Cc: linux-mips@linux-mips.org Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-11powerpc/mm/radix: Add MMU_FTR_RADIXAneesh Kumar K.V
We are going to add asm changes in the follow up patches. Add the feature bit now so that we can get it all build. mpe: When CONFIG_PPC_RADIX_MMU=n we omit MMU_FTR_RADIX from the MMU_FTRS_POSSIBLE mask. This allows the compiler to work out that those checks will always be false and so the code can be elided completely. Note we do *not* define MMU_FTR_RADIX to 0 in the RADIX_MMU=n case, because that doesn't work with the ASM_FTR patching. In particular an IF_SET section will result in a mask and value of zero, which is always true, meaning the section *won't* be patched, which is the opposite of what we want. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11powerpc/mm: Add mask of possible MMU featuresMichael Ellerman
Follow the example of the cpu feature code, and add a mask of possible MMU features, MMU_FTRS_POSSIBLE. This is used in mmu_has_feature(), which allows the possible mask to act as a shortcut for any features that are not possible, but still allows the feature bit itself to be defined. We will use this in the next commit to allow MMU_FTR_RADIX checks to be elided when MMU_FTR_RADIX is not possible. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-05-11KVM: PPC: Book3S HV: Fix build error in book3s_hv.cGavin Shan
When CONFIG_KVM_XICS is enabled, CPU_UP_PREPARE and other macros for CPU states in linux/cpu.h are needed by arch/powerpc/kvm/book3s_hv.c. Otherwise, build error as below is seen: gwshan@gwshan:~/sandbox/l$ make arch/powerpc/kvm/book3s_hv.o : CC arch/powerpc/kvm/book3s_hv.o arch/powerpc/kvm/book3s_hv.c: In function ‘kvmppc_cpu_notify’: arch/powerpc/kvm/book3s_hv.c:3072:7: error: ‘CPU_UP_PREPARE’ \ undeclared (first use in this function) This fixes the issue introduced by commit <6f3bb80944> ("KVM: PPC: Book3S HV: kvmppc_host_rm_ops - handle offlining CPUs"). Fixes: 6f3bb8094414 Cc: stable@vger.kernel.org # v4.6 Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2016-05-11KVM: PPC: Fix emulated MMIO sign-extensionPaul Mackerras
When the guest does a sign-extending load instruction (such as lha or lwa) to an emulated MMIO location, it results in a call to kvmppc_handle_loads() in the host. That function sets the vcpu->arch.mmio_sign_extend flag and calls kvmppc_handle_load() to do the rest of the work. However, kvmppc_handle_load() sets the mmio_sign_extend flag to 0 unconditionally, so the sign extension never gets done. To fix this, we rename kvmppc_handle_load to __kvmppc_handle_load and add an explicit parameter to indicate whether sign extension is required. kvmppc_handle_load() and kvmppc_handle_loads() then become 1-line functions that just call __kvmppc_handle_load() with the extra parameter. Reported-by: Bin Lu <lblulb@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2016-05-11KVM: PPC: Fix debug macrosAlexey Kardashevskiy
When XICS_DBG is enabled, gcc produces format errors. This fixes formats to match passed values types. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2016-05-11KVM: PPC: Book3S PR: Manage single-step modeLaurent Vivier
Until now, when we connect gdb to the QEMU gdb-server, the single-step mode is not managed. This patch adds this, only for kvm-pr: If KVM_GUESTDBG_SINGLESTEP is set, we enable single-step trace bit in the MSR (MSR_SE) just before the __kvmppc_vcpu_run(), and disable it just after. In kvmppc_handle_exit_pr, instead of routing the interrupt to the guest, we return to host, with KVM_EXIT_DEBUG reason. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
2016-05-11arm64: kernel: Fix incorrect brk randomizationKees Cook
This fixes two issues with the arm64 brk randomziation. First, the STACK_RND_MASK was being used incorrectly. The original code was: unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1; STACK_RND_MASK is 0x7ff (32-bit) or 0x3ffff (64-bit), with 4K pages where PAGE_SHIFT is 12: #define STACK_RND_MASK (test_thread_flag(TIF_32BIT) ? \ 0x7ff >> (PAGE_SHIFT - 12) : \ 0x3ffff >> (PAGE_SHIFT - 12)) This means the resulting offset from base would be 0x7ff0001 or 0x3ffff0001, which is wrong since it creates an unaligned end address. It was likely intended to be: unsigned long range_end = base + ((STACK_RND_MASK + 1) << PAGE_SHIFT) Which would result in offsets of 0x800000 (32-bit) and 0x40000000 (64-bit). However, even this corrected 32-bit compat offset (0x00800000) is much smaller than native ARM's brk randomization value (0x02000000): unsigned long arch_randomize_brk(struct mm_struct *mm) { unsigned long range_end = mm->brk + 0x02000000; return randomize_range(mm->brk, range_end, 0) ? : mm->brk; } So, instead of basing arm64's brk randomization on mistaken STACK_RND_MASK calculations, just use specific corrected values for compat (0x2000000) and native arm64 (0x40000000). Reviewed-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Kees Cook <keescook@chromium.org> [will: use is_compat_task() as suggested by tixy] Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-05-11arm64: cpuinfo: Missing NULL terminator in compat_hwcap_strJulien Grall
The loop that browses the array compat_hwcap_str will stop when a NULL is encountered, however NULL is missing at the end of array. This will lead to overrun until a NULL is found somewhere in the following memory. In reality, this works out because the compat_hwcap2_str array tends to follow immediately in memory, and that *is* terminated correctly. Furthermore, the unsigned int compat_elf_hwcap is checked before printing each capability, so we end up doing the right thing because the size of the two arrays is less than 32. Still, this is an obvious mistake and should be fixed. Note for backporting: commit 12d11817eaafa414 ("arm64: Move /proc/cpuinfo handling code") moved this code in v4.4. Prior to that commit, the same change should be made in arch/arm64/kernel/setup.c. Fixes: 44b82b7700d0 "arm64: Fix up /proc/cpuinfo" Cc: <stable@vger.kernel.org> # v3.19+ (but see note above prior to v4.4) Signed-off-by: Julien Grall <julien.grall@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-05-11irqchip: Add LPC32xx interrupt controller driverVladimir Zapolskiy
The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2 interrupt controllers. This is a list of new features in comparison to the legacy driver: * irq types are taken from device tree settings, no more need to hardcode them, * old driver is based on irq_domain_add_legacy, which causes problems with handling MIC hardware interrupt 0 produced by SIC1, * there is one driver for MIC, SIC1 and SIC2, no more need to handle them separately, e.g. have two separate handlers for SIC1 and SIC2, * the driver does not have any dependencies on hardcoded register offsets, * the driver is much simpler for maintenance, * SPARSE_IRQS option is supported. Legacy LPC32xx interrupt controller driver was broken since commit 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which requires a private interrupt handler, otherwise any SIC1 generated interrupt (mapped to MIC hwirq 0) breaks the kernel with the message "unexpected IRQ trap at vector 00". The change disables compilation of a legacy driver found at arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate commit. Fixes: 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler") Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11arm64: secondary_start_kernel: Remove unnecessary barrierSuzuki K Poulose
Remove the unnecessary smp_wmb(), which was added to make sure that the update_cpu_boot_status() completes before we mark the CPU online. But update_cpu_boot_status() already has dsb() (required for the failing CPUs) to ensure the correct behavior. Cc: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Reported-by: Dennis Chen <dennis.chen@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-05-11s390/vmem: remove unused function parameterHeiko Carstens
vmem_pte_alloc() has an unused function parameter. Let's remove it. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-05-11s390/vmem: fix identity mappingHeiko Carstens
The identity mapping is suboptimal for the last 2GB frame. The mapping will be established with a mix of 4KB and 1MB mappings instead of a single 2GB mapping. This happens because of a off-by-one bug introduced with commit 50be63450728 ("s390/mm: Convert bootmem to memblock"). Currently the identity mapping looks like this: 0x0000000080000000-0x0000000180000000 4G PUD RW 0x0000000180000000-0x00000001fff00000 2047M PMD RW 0x00000001fff00000-0x0000000200000000 1M PTE RW With the bug fixed it looks like this: 0x0000000080000000-0x0000000200000000 6G PUD RW Fixes: 50be63450728 ("s390/mm: Convert bootmem to memblock") Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2016-05-10Merge tag 'imx-dt64-4.7' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Merge "The Freescale/NXP arm64 device tree updates for 4.7" from Shawn Guo: - New board support of LS1043a-QDS from Freescale/NXP - Add new compatible for LS1043A and LS2080A GPIO devices - Update device tree bindings and sources for LS2080A fsl-mc device - Update QSPI and DSPI support on LS1043A and LS2080A * tag 'imx-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls2080a: fsl-mc dt node updates Documentation: fsl-mc: binding updates for MSIs, ranges, PHYs arm64: dts: ls1043a: add the DTS node for QSPI support Documentation: fsl-quadspi: Add fsl,ls1043a-qspi compatible string arm64: dts: ls2080a: Add compatible "fsl,ls2080a-gpio" for ls2080a gpio nodes arm64: dts: ls1043a: Add compatible "fsl,qoriq-gpio" for ls1043a gpio nodes arm64: dts: ls2080a: update the DTS for QSPI and DSPI support Documentation: fsl: dspi: Add fsl,ls2080a-dspi compatible string arm64: dts: ls1043a-rdb: add the DTS for DSPI support arm64: dts: add LS1043a-QDS board support Documentation: DT: Add entry for Freescale LS1043a-QDS board
2016-05-10Merge tag 'v4.6-next-dts64' of https://github.com/mbgg/linux-mediatek into ↵Arnd Bergmann
next/dt64 Merge "ARM: mediatek: dts64 updates for v4.7" from Matthias Brugger: - add thermal and auxadc device nodes to mt8173 - add thermal zone nodes to mt8173 * tag 'v4.6-next-dts64' of https://github.com/mbgg/linux-mediatek: arm64: dts: mt8173: Add thermal zone node. ARM64: dts: mt8173: Add thermal/auxadc device nodes
2016-05-10Merge tag 'tegra-for-4.7-gm20b' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64 Merge "arm64: tegra: Enable GM20B GPU on Tegra210" from Thierry Reding: Complement the GM20B GPU device tree node on Tegra210 with missing properties to make it usable. * tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add IOMMU node to GM20B on Tegra210 arm64: tegra: Add reference clock to GM20B on Tegra210 dt-bindings: Add documentation for GM20B GPU dt-bindings: gk20a: Document iommus property dt-bindings: gk20a: Fix typo in compatible name
2016-05-10Merge tag 'mvebu-dt64-4.7-1' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann
next/dt64 Merge "mvebu dt64 for 4.7" from Gregory CLEMENT: - switch to label in the mvebu arm64 device tree - use new clock binding on Armada 7K/8K - improve SPI and I2C description on Armada 7K/8k - add CP110 block adding PCIe, SATA and USB3 - add XOR support on Armada 3700 - few more little fix * tag 'mvebu-dt64-4.7-1' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: add XOR node for Armada 3700 SoC arm64: dts: marvell: Use a SoC-specific compatible for xHCI on Armada37xx arm64: dts: marvell: Rename armada-37xx USB node arm64: dts: marvell: Clean up armada-3720-db arm64: dts: marvell: enable several CP interfaces on Armada 7040-DB arm64: dts: marvell: initial DT description of Armada 7K/8K CP110 master arm64: dts: marvell: use the proper I2C controller compatible string for 7K/8K arm64: dts: marvell: improve SPI flash description on Armada 7040-DB arm64: dts: marvell: use new clock binding on Armada AP806 arm64: dts: marvell: add UART aliases and define stdout-path arm64: dts: marvell: rename armada-ap806 XOR nodes arm64: dts: marvell: clean up armada-7040-db
2016-05-10Merge tag 'v4.7-rockchip-dts64-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64 Merge "Rockchip dts64 updates for v4.7 - part2" from Heiko Stübner: Adding the new rk3399 core devicetree support as well as a board dts for the evaluation board of this chip and similar to the arm32 side also move the rk3368 thermal data into the core soc dtsi, as there really is no need to keep it separate. * tag 'v4.7-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: document rockchip rk3399-evb board arm64: dts: rockchip: add dts file for RK3399 evaluation board arm64: dts: rockchip: add core dtsi file for RK3399 SoCs dt-bindings: rockchip-dw-mshc: add description for rk3399 clk: rockchip: export some necessary rk3399 clock ids clk: rockchip: rename rga clock-id on rk3399 clk: rockchip: add general gpu soft-reset on rk3399 arm64: dts: rockchip: move the rk3368 thermal data into rk3368.dtsi clk: rockchip: fix checkpatch errors in rk3399 dt-binding header clk: rockchip: add dt-binding header for rk3399
2016-05-10arm64/sunxi: 4.6-rc1: Add dependency on generic irq chipSuzuki K Poulose
Commit ce3dd55b99b1 ("arm64: Introduce Allwinner SoC config option"), added support for ARCH_SUNXI on arm64, but failed to select GENERIC_IRQ_CHIP, which is required for drivers/irqchip/irq-sunxi-nmi.c and causes build failures like : UPD include/generated/compile.h CC init/version.o LD init/built-in.o drivers/built-in.o: In function `sunxi_sc_nmi_set_type': drivers/irqchip/irq-sunxi-nmi.c:114: undefined reference to `irq_setup_alt_chip' drivers/built-in.o: In function `irq_domain_add_linear': include/linux/irqdomain.h:253: undefined reference to `irq_generic_chip_ops' include/linux/irqdomain.h:253: undefined reference to `irq_generic_chip_ops' drivers/built-in.o: In function `sunxi_sc_nmi_irq_init': drivers/irqchip/irq-sunxi-nmi.c:146: undefined reference to `irq_alloc_domain_generic_chips' drivers/irqchip/irq-sunxi-nmi.c:161: undefined reference to `irq_get_domain_generic_chip' drivers/irqchip/irq-sunxi-nmi.c:170: undefined reference to `irq_gc_mask_clr_bit' drivers/irqchip/irq-sunxi-nmi.c:171: undefined reference to `irq_gc_mask_set_bit' drivers/irqchip/irq-sunxi-nmi.c:172: undefined reference to `irq_gc_ack_set_bit' drivers/irqchip/irq-sunxi-nmi.c:170: undefined reference to `irq_gc_mask_clr_bit' Fixes: commit ce3dd55b99b1 ("arm64: Introduce Allwinner SoC config option") Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-05-10Merge branch 'x86-urgent-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Ingo Molnar: "Two topology corner case fixes, and a MAINTAINERS file update for mmiotrace maintenance" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/topology: Set x86_max_cores to 1 for CONFIG_SMP=n MAINTAINERS: Add mmiotrace entry x86/topology: Handle CPUID bogosity gracefully
2016-05-10kvmconfig: add more virtio driversAndrey Utkin
"make defconfig kvmconfig" is supposed to end up with usable kernel for KVM guest. In practice, it won't work for e.g. Hetzner VPS (KVM-based) unless you add these options. Signed-off-by: Andrey Utkin <andrey_utkin@fastmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-10x86/kvm: Add stack frame dependency to fastop() inline asmJosh Poimboeuf
The kbuild test robot reported this objtool warning [1]: arch/x86/kvm/emulate.o: warning: objtool: fastop()+0x69: call without frame pointer save/setup The issue seems to be caused by CONFIG_PROFILE_ALL_BRANCHES. With that option, for some reason gcc decides not to create a stack frame in fastop() before doing the inline asm call, which can result in a bad stack trace. Force a stack frame to be created if CONFIG_FRAME_POINTER is enabled by listing the stack pointer as an output operand for the inline asm statement. This change has no effect for !CONFIG_PROFILE_ALL_BRANCHES. [1] https://lists.01.org/pipermail/kbuild-all/2016-March/018249.html Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com> Acked-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-10Merge tag 'mvebu-defconfig64-4.7-1' of git://git.infradead.org/linux-mvebu ↵Arnd Bergmann
into next/arm64 Merge "mvebu defconfig for arm64 for 4.7" from Gregory CLEMENT: - update arm64 defconfig with options useful for Armada 7K/8K support * tag 'mvebu-defconfig64-4.7-1' of git://git.infradead.org/linux-mvebu: arm64: configs: add options useful for Armada 7K/8K support
2016-05-10Merge tag 'kvm-s390-next-4.7-2' of ↵Paolo Bonzini
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD KVM: s390: features and fixes for 4.7 part2 - Use hardware provided information about facility bits that do not need any hypervisor activitiy - Add missing documentation for KVM_CAP_S390_RI - Some updates/fixes for handling cpu models and facilities
2016-05-10Merge tag 'samsung-dt-devfreq-4.7' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late Merge "ARM: dts: exynos: Devfreq for v4.7: from Krzysztof Kozłowski: Topic branch for Device Tree changes adding new generic devfreq driver, for v4.7: 1. Add bus nodes for Exynos3250, Exynos4x12, Exynos4210 and Exynos542x. 2. Split out common PPMU (Performance Monitoring Unit) nodes into separate DTSI. The PPMU provides performance data for devfreq. 3. Add NoCP (Network on Chip Probe) node for Exynos542x. On this SoC, like PPMU on older designs, provides performance data for devfreq. 4. Enable DFVS (Dynamic Voltage and Frequency Scaling) on boards: - Exynos3250 Rinato, - Exynos4412 Odroid-X/X2/U3 and Trats2, - Exynos5422 Odroid XU3/XU3-Lite/XU4. * tag 'samsung-dt-devfreq-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3 ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250 ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk ARM: dts: exynos: Add DMC bus node for Exynos3250 clk: samsung: exynos542x: Add the clock id for ACLK dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC
2016-05-10Merge tag 'imx-dt-clkdep-4.7' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/late Merge "The i.MX device tree updates with new clocks for 4.7" from Shawn Guo: - Add LCDIF and FlexCAN device support for i.MX7D - New support i.MX7D based Nitrogen7 board from Boundary Devices - Add display support for vf610-colibri board * tag 'imx-dt-clkdep-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: vf610-colibri: enable display controller ARM: dts: vf610: add display nodes ARM: dts: imx: add Boundary Devices Nitrogen7 board ARM: dts: imx7d: add flexcan support ARM: dts: imx7d: add lcdif support clk: imx: vf610: fix whitespace in vf610-clock.h clk: imx: vf610: add TCON ipg clock clk: imx: vf610: fix DCU clock tree clk: imx: add ckil clock for i.MX7 clk: imx: vf610: add suspend/resume support clk: imx: vf610: add WKPU unit clk: imx: vf610: leave DDR clock on clk: imx: clk-gate2: allow custom gate configuration clk: imx6sx: Register SAI clocks as shared clocks
2016-05-10ARM: dts: tango4: Import watchdog nodeMarc Gonzalez
The device driver was added in v4.5 by commit dca536c433a2 ("watchdog: add support for Sigma Designs SMP86xx/SMP87xx") Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-05-10ARM: dts: tango4: Update cpus node for cpufreqMarc Gonzalez
This platform will use the new generic platdev driver. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-05-10ARM: dts: tango4: Update DT to match clk driverMarc Gonzalez
Commit fefe0535b74f ("clk: tango4: improve clkgen driver") added support for USB and SDIO clocks. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-05-10ARM: dts: tango4: Initial thermal supportMarc Gonzalez
Define the CPU temperature sensor, and critical trip point. Commit 799d71da471c ("add temperature sensor support for tango SoC") added the device driver. Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-05-10Merge tag 'sunxi-dt-for-4.7-2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt Merge "Allwinner DT changes for 4.7, round 2" from Maxime Ripard: Mostly DT patches to enable the new DRM driver on the CHIP, preliminary support for the A10 and A20, and a support for a new variant of the Olimex A20-Olinuxino-Lime2 featuring an eMMC * tag 'sunxi-dt-for-4.7-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: ARM: sun7i: dt: Add pll3 and pll7 clocks ARM: dts: sunxi: Add a olinuxino-lime2-emmc ARM: sun4i: dt: Add pll3 and pll7 clocks ARM: sun5i: chip: Enable the TV Encoder ARM: sun5i: r8: Add display blocks to the DTSI ARM: sun5i: a13: Add display and TCON clocks
generated by cgit (git 2.34.1) at 2025-09-12 17:20:22 +0000