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The <generated/utsrelease.h> defines UTS_RELEASE, but I do not
see any reference to it in arch/x86/boot/header.S.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1505921232-8960-1-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
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ARMv8-A adds a few optional features for ARMv8.2 and ARMv8.3.
Expose them to the userspace via HWCAPs and mrs emulation.
SHA2-512 - Instruction support for SHA512 Hash algorithm (e.g SHA512H,
SHA512H2, SHA512U0, SHA512SU1)
SHA3 - SHA3 crypto instructions (EOR3, RAX1, XAR, BCAX).
SM3 - Instruction support for Chinese cryptography algorithm SM3
SM4 - Instruction support for Chinese cryptography algorithm SM4
DP - Dot Product instructions (UDOT, SDOT).
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Dave Martin <dave.martin@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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All the A31/A31s devices I own have some kind of HDMI connector wired
to the dedicated HDMI pins on the SoC:
- A31 Hummingbird (standard HDMI connector, display already enabled)
- Sinlinx SinA31s (standard HDMI connector)
- MSI Primo81 tablet (micro HDMI connector)
Enable the display pipeline (if needed) and HDMI output for them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Now that we support the HDMI controller on the A31 SoC, we can add it
to the device tree.
This adds a device node for the HDMI controller, and the of_graph nodes
connecting it to the 2 TCONs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Add binding for tsensor on H3660, this tsensor is used for
SoC thermal control, it supports alarm interrupt.
Signed-off-by: Kevin Wangtao <kevin.wangtao@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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The gpio1 node's interrupt number should be 111.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Enable gpio and leds for socdk OOBE daughtercard.
pushbutton PB_SW0 = gpio1.io4
pushbutton PB_SW1 = gpio1.io5
LED HPS_LED0 = gpio1.io20
LED HPS_LED1 = gpio1.io19
LED HPS_LED2 = gpio1.io21
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Add the gpio header to the base stratix10 dtsi.
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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A bugfix for the SMP case broke the build for the UP case:
arch/arm/mach-shmobile/headsmp-apmu.o: In function `shmobile_boot_apmu':
(.text+0x34): undefined reference to `secondary_startup'
The assembler file mixes code that is used for SMP with code
that we also need on a single-CPU build, so I'm leaving it
always enabled in the Makefile, but enclose the SMP code
in an #ifdef.
Fixes: fd45a136ff6 ("ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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On some i.MX6 SoCs (like i.MX6SL, i.MX6SX and i.MX6UL) that do not have
speed grading check, opp table will not be created in platform code,
so cpufreq driver prints the following error message:
cpu cpu0: dev_pm_opp_get_opp_count: OPP table not found (-19)
However, this is not really an error in this case because the
imx6q-cpufreq driver first calls dev_pm_opp_get_opp_count()
and if it fails, it means that platform code does not provide
OPP and then dev_pm_opp_of_add_table() will be called.
In order to avoid such confusing error message, move the speed grading
check from platform code to the imx6q-cpufreq driver.
This way the imx6q-cpufreq no longer has to check whether OPP table
is supplied by platform code.
Tested on a i.MX6Q and i.MX6UL based boards.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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With all of mach-omap2 booting now in device tree only mode,
we can get the module IO range from device tree and just drop
the legacy hwmod struct omap_hwmod_addr_space.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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We have all of mach-omap2 booting in device tree only
mode now, and this data is populated from device tree.
Note that once we have removed support for the omap legacy
DMA, we can also drop struct omap_dma_dev_attr.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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With the previous patches removing the need for legacy IRQs
now that all of mach-omap2 is booting in device tree only mode,
we can drop struct omap_hwmod_irq_info.
Note that we can now also finally drop omap4_xlate_irq.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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We have the PRM IRQ mapped in device tree and this legacy code
is no longer needed.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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We have this coming from device tree and legacy booting is
no longer needed.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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We can handle the sysc interconnect target module in a generic way
for many TI SoCs. Initially let's just enable runtime PM with
autosuspend, and probe the children. This can already be used for
idling interconnect target modules that don't have any device driver
available for the child devices.
For now, the "ti,hwmods" custom binding is still required. That will
be eventually deprecated in later patches. And more features will be
added, such as parsing for sysc capabilities so we can continue
removing the legacy platform data.
Cc: Benoît Cousson <bcousson@baylibre.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Sakari Ailus <sakari.ailus@iki.fi>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
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We can populate the legacy resources needed by dma and smartreflex
from device tree in omap_device_build().
There should be no need to do this for other devices, and eventually
these two remaining users will be gone too. The legacy dma will be
dropped when the remaining users have been converted to use the
dmaengine driver, and smartreflex can now become just a regular
device driver with a few pdata callbacks.
This is needed in order to remove remaining device dma, irq and io
resources from the interconnect code.
And while at it, let's simplify things by removing otherwise
unused omap_device_build_ss() as we will never call it for more
than one hwmod.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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When removing legacy platform data for IO ranges for the hwmod
interconnect code, we still need to support the "ti,hwmods"
property.
And as we're going to use a generic sysc device driver to handle the
interconnect target instances, we can parse the information needed
for legacy "ti,hwmods" IO range from the dts. It's always the first
range the interconnect target module provides.
Note that we want to parse the range instead of the first child
device IO regs as the child device may not always be defined.
The child IP device node may not exist in cases where there is no
driver binding for the device, or when the child IP block may not
even be functional for some SoC revisions. But the IO range of the
interconnect target module is always known.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The TRM has marked dra7 SmartReflex as reserved and we should not
touch those registers as pointed out by Nishanth Menon <nm@ti.com>.
We do still want to idle the related interconnect target modules on
init though.
Let's do this by only configuring the generic interconnect target modules
and not add the child SmartReflex devices.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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On omap4 we are missing dts nodes for several interconnect target
modules that we are idling on init. This currently works with the
legacy platform data still around.
To fix this, let's add the interconnect target modules so we can
idle the unused interconnect target module on init.
Also note that adding the interconnect target module node does not
necessarily mean that there is a driver available for the child IP
block, or that the child IP block is even functional.
In the SGX case, the PowerVR driver is closed source. And McASP on
omap4 has at least the TX path disabled and is not supported by the
davinci-mcasp driver. For AESS there is old Android 3.4 kernel
driver available.
For smarflex, we are still probing with platform data and the
driver needs more work before we can add the device ip child nodes.
And finally, we're not yet using the interconnet ranges. I will
be posting separate patches for those later on.
Cc: Benoît Cousson <bcousson@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sakari Ailus <sakari.ailus@iki.fi>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add CPU idle state nodes to enable C1/C2 idle states.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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K2G EVM has n25q128a13 SPI NOR flash on SPI1. Enable SPI1 in the DT
node as well as add a subnode for the SPI NOR.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Add nodes for the various SPI instances.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Enable PWM ECAP0 which will be used for display backlight.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Add DT nodes for PWM ECAP IP present on 66AK2G SoC.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Enable USB 0 which will be used as a host port and USB 1 which will be
used in peripheral mode.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Add nodes for both USB instances supported by 66AK2G.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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K2G EVM has an onboard I2C EEPROM connected to I2C0. This patch adds
the necessary DT entry for the AT24CM01 EEPROM.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Add nodes for the various I2C instances.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Add three McASP nodes present on 66AK2G device.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Enable DRM_HISI_HIBMC as module for Hisilicon D03/D05 board.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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The hi6220-HiKey board started to name GPIO lines for
96boards, using just the plain names "GPIO-A" etc from the
96boards specification.
Poplar started to use an arbitrary "LS-GPIO-A" (etc) prefix
that is not part of the 96boards specification.
As the former notation arrived first, and we need
consistency among 96board, rectify the Poplar board to use
this too. This is important for userspace that wants to
look up GPIO names from these strings.
Cc: Jiancheng Xue <xuejiancheng@hisilicon.com>
Cc: Alex Elder <elder@linaro.org>
Cc: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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This adds line names for all the GPIOs I could identify on the HiKey960
schematic.
"GPIO-A" through "GPIO-L" are the most important since they give users
a handle to look up the standard 96boards GPIOs from the GPIO character
device.
The rest of the names are more informational, nice debug information
for "lsgpio" so you can see that the right line is taken for the right
function in the kernel for example.
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Zhangfei Gao <zhangfei.gao@hisilicon.com>
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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For detailed coresight topology, Hi6220 has 8xCA53 CPUs and each CPU
has one Embedded Trace Macrocell (ETM); the CPU trace data is output
to the cluster funnel. Due system has another CPU and one MCU, all of
them transfer the trace data through trace bus (ATB) to SoC funnel;
the SoC funnel is connected to Embedded Trace FIFO (ETF) with 8KB
buffer; an non-configurable replicator is used to output trace data
for two sinks, one is Embedded Trace Route (ETR) so trace data can be
saved into DRAM, another is Trace Port Interface Unit (TPIU) for
capturing trace data by external debugger.
According to the Hi6220 coresight topology, this patch is to add
coresight dt nodes.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Guodong Xu <guodong.xu@linaro.org>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com>
Signed-off-by: Li Zhong <lizhong11@hisilicon.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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is_last_gpte() is not equivalent to the pseudo-code given in commit
6bb69c9b69c31 ("KVM: MMU: simplify last_pte_bitmap") because an incorrect
value of last_nonleaf_level may override the result even if level == 1.
It is critical for is_last_gpte() to return true on level == 1 to
terminate page walks. Otherwise memory corruption may occur as level
is used as an index to various data structures throughout the page
walking code. Even though the actual bug would be wherever the MMU is
initialized (as in the previous patch), be defensive and ensure here
that is_last_gpte() returns the correct value.
This patch is also enough to fix CVE-2017-12188.
Fixes: 6bb69c9b69c315200ddc2bc79aee14c0184cf5b2
Cc: stable@vger.kernel.org
Cc: Andy Honig <ahonig@google.com>
Signed-off-by: Ladi Prosek <lprosek@redhat.com>
[Panic if walk_addr_generic gets an incorrect level; this is a serious
bug and it's not worth a WARN_ON where the recovery path might hide
further exploitable issues; suggested by Andrew Honig. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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The function updates context->root_level but didn't call
update_last_nonleaf_level so the previous and potentially wrong value
was used for page walks. For example, a zero value of last_nonleaf_level
would allow a potential out-of-bounds access in arch/x86/mmu/paging_tmpl.h's
walk_addr_generic function (CVE-2017-12188).
Fixes: 155a97a3d7c78b46cef6f1a973c831bc5a4f82bb
Signed-off-by: Ladi Prosek <lprosek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Use DMA for USART0 (which is used as ttyS1) as we have enough channels and to
show how to specify DMA use with serial nodes.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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Add the PWM0 interface and one output of channel 0 (on PC10) on this headless
board. The output conflicts with LCD and ISI, so only enable it for this
particular board of the series (ISI is enabled on at91sam9g25ek, as an example
but we can do the other way around).
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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As the CAN1 interface is not multiplexed with other peripherals on this
board, enable it so that it can be tested more easily.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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As the board have the proper pull-ups soldered on the data and CMD
lines we don't need them specified in the PADs. So remove the
"bias-pull-up" property and set "bias-disable".
This will also save some power.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[claudiu.beznea@microchip.com: change subject to match the desired prefix]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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Add pin muxing for pwm0 and set it as disabled since it is in conflict
with pins for leds.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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Set the PB_USER button as a wakeup source to resume from ulp0 mode.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
[claudiu.beznea@microchip.com: change subject to match the desired prefix]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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As the board have the proper pull-ups soldered on the data
and CMD lines we don't need them specified in the PADs. So remove
the "bias-pull-up" property and set "bias-disable".
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[claudiu.beznea@microchip.com: change subject to match the desired prefix]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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CAN0 is not connected on the sama5d27_som1_ek board, so remove
it from DT.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[claudiu.beznea@microchip.com: change subject to match the desired prefix]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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Add pin muxing for pwm0 and set it as disabled since it is in conflict
with the pins for leds.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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Add aliases for i2c devices to not rely on probe order for i2c device
numbering.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
[claudiu.beznea@microchip.com: remove i2c0, change subject]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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Set the USER button as a wakeup source to allow wakeup from ULP0.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
[claudiu.beznea@microchip.com: change subject to match the desired prefix]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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Overwrite sama5d2.dtsi aliases node to match the at91-sama5d27_som1_ek
board configuration. ttyS0 stands for DBGU, ttyS1 for the mikro BUS 1
serial lines and ttyS2 for the mikro BUS 2 serial lines.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
[claudiu.beznea@microchip.com: change subject to match the desired prefix]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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