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2022-09-28arm64: dts: uniphier: Rename pvtctl node to thermal-sensorKunihiko Hayashi
The pvtctl node belongs to thermal-sensor, so the node name should be renamed to thermal-sensor. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-2-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Remove compatible "snps,dw-pcie-ep" from pcie-ep nodeKunihiko Hayashi
The generic platform driver pcie-designware-plat.c doesn't work for UniPhier PCIe endpoint controller, because the controller has some necessary initialization sequence for the controller-specific logic. Currently the controller doesn't use "snps,dw-pcie-ep" compatible, so this is no longer needed. Remove the compatible string from the pcie-ep node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-10-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Move interrupt-parent property to each child node in ↵Kunihiko Hayashi
uniphier-support-card The dtschema warning: uniphier-ld11-ref.dt.yaml: system-bus@58c00000: 'interrupt-parent' does not match any of the regexes: '^.*@[1-5],[1-9a-f][0-9a-f]+$', 'pinctrl-[0-9]+' Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-9-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Add ahci controller nodes for PXs2Kunihiko Hayashi
Add ahci core controller and glue layer nodes including reset-controller and sata-phy. This supports for PXs2 and the boards without PXs2 vodka board that doesn't implement any SATA connectors. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-8-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Add ahci controller nodes for Pro4Kunihiko Hayashi
Add ahci controller, glue layer, and clock nodes for Pro4 SoC. The glue layer includes reset and phy, and the clock node is used for handling ahci clocks on SoC-glue. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-7-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Use GIC interrupt definitionsKunihiko Hayashi
Use human-readable definitions for GIC interrupt type and flag, instead of hard-coding the numbers. No functional change. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-6-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Rename gpio-hog nodeKunihiko Hayashi
According to gpio-hog schema, should add the suffix "-hog" to the node names including gpio-hog to fix the following warning. uniphier-pro4-ref.dtb: gpio@55000000: 'xirq2' does not match any of the regexes: '^.+-hog(-[0-9+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml This applies to the devicetree for LD4, LD6b, Pro4 and sLD8 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-5-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Rename usb-glue node for USB3 to usb-controllerKunihiko Hayashi
This "usb-glue" stands for an external controller associated with USB core, however, this is not common. So rename to "usb-controller". Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-4-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Rename usb-phy node for USB2 to usb-controllerKunihiko Hayashi
Actual phy nodes are each child node. The parent node should be usb-controller node as a representation of the phy integration. This applies to the devicetree for Pro4 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-3-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: uniphier: Rename pvtctl node to thermal-sensorKunihiko Hayashi
The pvtctl node belongs to thermal-sensor, so the node name should be renamed to thermal-sensor. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042249.4708-2-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: remove check for CONFIG_DEBUG_LL_SER3Paul Bolle
A check for CONFIG_DEBUG_LL_SER3 was added in v2.5.43. But the related symbol DEBUG_LL_SER3 was already removed in v2.5.8. This check has always evaluated to false. Remove it. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28Merge tag 'v6.1-rockchip-defconfig64-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/defconfig Enable Synopsys DWC MSHC (sdhci) driver in the defconfig. * tag 'v6.1-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: defconfig: Enable Synopsys DWC MSHC driver Link: https://lore.kernel.org/r/1989419.QkHrqEjB74@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28Merge tag 'aspeed-6.1-defconfig' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/defconfig ASPEED defconfig updates for 6.1 - A long awaited sync to make the config closer to that used by OpenBMC machines - Enable PECI to provide defconfig coverage for the subsystem * tag 'aspeed-6.1-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: config: aspeed_g5: Enable PECI ARM: configs: aspeed_g4: Remove appended DTB and ATAG ARM: configs: aspeed: Refresh defconfigs ARM: config: aspeed: Enable namespaces ARM: configs: aspeed_g4: Enable IPV6 options ARM: configs: aspeed_g4: Enable OCC and NBD drivers ARM: configs: aspeed_g5: Enable MCTP stack ARM: configs: aspeed_g5: Add PL2303 USB serial driver ARM: configs: aspeed_g5: Add TPM TIS I2C driver ARM: configs: aspeed_g5: Add mp5023 driver ARM: configs: aspeed: Add support for USB flash drives Link: https://lore.kernel.org/r/CACPK8XeLzL3hT8fwVw9fV7Ccduz_PNhZn_67z2yXefCEha6jJg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: aspeed: Kconfig: Fix indentationJuerg Haefliger
The convention for indentation seems to be a single tab. Help text is further indented by an additional two whitespaces. Fix the lines that violate these rules. Signed-off-by: Juerg Haefliger <juergh@canonical.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220523060532.7864-1-juergh@canonical.com Link: https://lore.kernel.org/r/20220928025926.2592030-1-joel@jms.id.au' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: Drop CMDLINE_* dependency on ATAGSGeert Uytterhoeven
On arm32, the configuration options to specify the kernel command line type depend on ATAGS. However, the actual CMDLINE cofiguration option does not depend on ATAGS, and the code that handles this is not specific to ATAGS (see drivers/of/fdt.c:early_init_dt_scan_chosen()). Hence users who desire to override the kernel command line on arm32 must enable support for ATAGS, even on a pure-DT system. Other architectures (arm64, loongarch, microblaze, nios2, powerpc, and riscv) do not impose such a restriction. Hence drop the dependency on ATAGS. Fixes: bd51e2f595580fb6 ("ARM: 7506/1: allow for ATAGS to be configured out when DT support is selected") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: Drop CMDLINE_FORCE dependency on !ARCH_MULTIPLATFORMGeert Uytterhoeven
On older platforms that boot an image with an appended DTB, or where the boot loader has no support for updating chosen/bootargs, it is common to rely on CMDLINE_FORCE. While a fixed command line can make the kernel unbootable on other platforms, it is not guaranteed to cause that. E.g. all Renesas boards use the same chosen/bootargs in upstream DTS, which works fine if your DHCP server hands out proper nfsroot parameters. Fixes: 84fc863606239d8b ("ARM: make ARCH_MULTIPLATFORM user-visible") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: s3c: remove orphan declarations from arch/arm/mach-s3c/devs.hGaosheng Cui
s3c64xx_device_spi1 and s3c64xx_device_spi2 were removed by commit f1ba938e4f98 ("spi: s3c64xx: Delete unused boardfile helpers"), so remove the declaration, too. Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220914034615.1240860-3-cuigaosheng1@huawei.com Link: https://lore.kernel.org/r/20220926104354.118578-3-krzysztof.kozlowski@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28ARM: dts: exynos: correct s5k6a3 reset polarity on Midas familyDmitry Torokhov
According to s5k6a3 driver code, the reset line for the chip appears to be active low. This also matches the typical polarity of reset lines in general. Let's fix it up as having correct polarity in DTS is important when the driver will be switched over to gpiod API. Fixes: b4fec64758ab ("ARM: dts: Add camera device nodes for Exynos4412 TRATS2 board") Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220913164104.203957-1-dmitry.torokhov@gmail.com Link: https://lore.kernel.org/r/20220926104354.118578-2-krzysztof.kozlowski@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28Merge tag 'aspeed-6.1-devicetree' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt ASPEED device tree updates for 6.1 - New machines * AMD's DaytonaX AST2600 BMC, for the amd64 server * Ampre's Mt. Mitchell AST2600 BMC, for the AmpereOne arm64 server - Fixes and updates for bletchley, mtjade, yosemitev2 and the ast2600-evb * tag 'aspeed-6.1-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: dts: aspeed: ast2600-evb-a1: Add compatible ARM: dts: aspeed: ast2600evb: Fix compatible string ARM: dts: aspeed: ast2600-evb: Enable Quad SPI RX tranfers ARM: dts: aspeed-g6: Enable more UART controllers ARM: dts: aspeed: yosemitev2: Disable the EEPROM driver ARM: dts: aspeed: Add AMD DaytonaX BMC dt-bindings: arm: aspeed: document AMD DaytonaX ARM: dts: aspeed: Yosemite V2: Enable OCP debug card ARM: dts: aspeed: mtjade: Remove gpio-keys entries ARM: dts: aspeed: Add device tree for Ampere's Mt. Mitchell BMC dt-bindings: arm: aspeed: document Ampere Mt.Mitchell BMC compatibles ARM: dts: aspeed: bletchley: Remove hdc1080 node ARM: dts: aspeed: bletchley: Add USB debug card IPMB node ARM: dts: aspeed: ast2600-evb: Update I2C devices Link: https://lore.kernel.org/r/CACPK8Xepnci+f+7Pi1jtXod8Jmt+OnJYfDRENjiP-xDBQwFCVg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28Merge tag 'v6.1-rockchip-dts64-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt RK3399-Nanopi-R4S-enterprise as variant board, Gru-Scarlet SKU variants, DSI support for rk356x, display-gamma-control for rk3399, display output for quartz64-b and rk3566-roc-pc, hdmi supplies for rk3399-roc-pc, some pinctrl improvements for the px30-evb and a number of changes to bring rk3399 rock4 and rock-pi4 structure closer to names used in schematics. * tag 'v6.1-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: use pin constant for reset-gpios on px30-evb arm64: dts: rockchip: add pinctrl for mipi-pdn pin on px30-evb arm64: dts: rockchip: set max drive-strength for cif_clkout_m0 on px30-evb arm64: dts: rockchip: add avdd-0v9-supply and avdd-1v8-supply on rk3399 rock 4c and pi4 arm64: dts: rockchip: sort nodes/properties on rk3399-rock-4 arm64: dts: rockchip: fix regulator name on rk3399-rock-4 arm64: dts: rockchip: sort nodes/properties on rk3399-rock-4c-plus arm64: dts: rockchip: fix regulator structure on rk3399-rock-4c-plus arm64: dts: rockchip: connect vcca_1v8 to APIO5_VDD on rk3399-rock-4c-plus arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x arm64: dts: rockchip: Enable HDMI and GPU on quartz64-b arm64: dts: rockchip: Add RK3399 NanoPi R4S Enterprise Edition dt-bindings: Add doc for FriendlyARM NanoPi R4S Enterprise Edition arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to px30 arm64: dts: rockchip: Add HDMI supplies on rk3399-roc-pc arm64: dts: rockchip: Support gru-scarlet sku{2,4} variants dt-bindings: arm: rockchip: Add gru-scarlet sku{2,4} variants arm64: dts: rockchip: enable gamma control on RK3399 arm64: dts: rockchip: Enable video output on rk3566-roc-pc Link: https://lore.kernel.org/r/38114097.10thIPus4b@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28m68k: Rework BI_VIRT_RNG_SEED as BI_RNG_SEEDJason A. Donenfeld
This is useful on !virt platforms for kexec, so change things from BI_VIRT_RNG_SEED to be BI_RNG_SEED, and simply remove BI_VIRT_RNG_SEED because it only ever lasted one release, and nothing is broken by not having it. At the same time, keep a comment noting that it's been removed, so that ID isn't reused. In addition, we previously documented 2-byte alignment, but 4-byte alignment is actually necessary, so update that comment. Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Fixes: a1ee38ab1a75 ("m68k: virt: Use RNG seed from bootinfo block") Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Link: https://lore.kernel.org/r/20220927130835.1629806-2-Jason@zx2c4.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-09-28m68k: Process bootinfo records before saving themJason A. Donenfeld
The RNG seed boot record is memzeroed after processing, in order to preserve forward secrecy. By saving the bootinfo for procfs prior to that, forward secrecy is violated, since it becomes possible to recover past states. So, save the bootinfo block only after first processing them. Fixes: a1ee38ab1a75 ("m68k: virt: Use RNG seed from bootinfo block") Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Link: https://lore.kernel.org/r/20220927130835.1629806-1-Jason@zx2c4.com Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-09-28KVM: x86/svm/pmu: Rewrite get_gp_pmc_amd() for more counters scalabilityLike Xu
If the number of AMD gp counters continues to grow, the code will be very clumsy and the switch-case design of inline get_gp_pmc_amd() will also bloat the kernel text size. The target code is taught to manage two groups of MSRs, each representing a different version of the AMD PMU counter MSRs. The MSR addresses of each group are contiguous, with no holes, and there is no intersection between two sets of addresses, but they are discrete in functionality by design like this: [Group A : All counter MSRs are tightly bound to all event select MSRs ] MSR_K7_EVNTSEL0 0xc0010000 MSR_K7_EVNTSELi 0xc0010000 + i ... MSR_K7_EVNTSEL3 0xc0010003 MSR_K7_PERFCTR0 0xc0010004 MSR_K7_PERFCTRi 0xc0010004 + i ... MSR_K7_PERFCTR3 0xc0010007 [Group B : The counter MSRs are interleaved with the event select MSRs ] MSR_F15H_PERF_CTL0 0xc0010200 MSR_F15H_PERF_CTR0 (0xc0010200 + 1) ... MSR_F15H_PERF_CTLi (0xc0010200 + 2 * i) MSR_F15H_PERF_CTRi (0xc0010200 + 2 * i + 1) ... MSR_F15H_PERF_CTL5 (0xc0010200 + 2 * 5) MSR_F15H_PERF_CTR5 (0xc0010200 + 2 * 5 + 1) Rewrite get_gp_pmc_amd() in this way: first determine which group of registers is accessed, then determine if it matches its requested type, applying different scaling ratios respectively, and finally get pmc_idx to pass into amd_pmc_idx_to_pmc(). Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-8-likexu@tencent.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: x86/svm/pmu: Direct access pmu->gp_counter[] to implement amd_*_to_pmc()Like Xu
Access PMU counters on AMD by directly indexing the array of general purpose counters instead of translating the PMC index to an MSR index. AMD only supports gp counters, there's no need to translate a PMC index to an MSR index and back to a PMC index. Opportunistically apply array_index_nospec() to reduce the attack surface for speculative execution and remove the dead code. Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-7-likexu@tencent.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: x86/pmu: Avoid using PEBS perf_events for normal countersLike Xu
The check logic in the pmc_resume_counter() to determine whether a perf_event is reusable is partial and flawed, especially when it comes to a pseudocode sequence (contrived, but valid) like: - enabling a counter and its PEBS bit - enable global_ctrl - run workload - disable only the PEBS bit, leaving the global_ctrl bit enabled In this corner case, a perf_event created for PEBS can be reused by a normal counter before it has been released and recreated, and when this normal counter overflows, it triggers a PEBS interrupt (precise_ip != 0). To address this issue, reprogram all affected counters when PEBS_ENABLE change and reuse a counter if and only if PEBS exactly matches precise. Fixes: 79f3e3b58386 ("KVM: x86/pmu: Reprogram PEBS event to emulate guest PEBS counter") Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-4-likexu@tencent.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: x86/pmu: Refactor PERF_GLOBAL_CTRL update helper for reuse by PEBSLike Xu
Extract the "global ctrl" specific bits out of global_ctrl_changed() so that the helper only deals with reprogramming general purpose counters, and rename the helper accordingly. PEBS needs the same logic, i.e needs to reprogram counters associated when PEBS_ENABLE bits are toggled, and will use the helper in a future fix. No functional change intended. Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-4-likexu@tencent.com [sean: split to separate patch, write changelog] Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: x86/pmu: Don't generate PEBS records for emulated instructionsLike Xu
KVM will accumulate an enabled counter for at least INSTRUCTIONS or BRANCH_INSTRUCTION hw event from any KVM emulated instructions, generating emulated overflow interrupt on counter overflow, which in theory should also happen when the PEBS counter overflows but it currently lacks this part of the underlying support (e.g. through software injection of records in the irq context or a lazy approach). In this case, KVM skips the injection of this BUFFER_OVF PMI (effectively dropping one PEBS record) and let the overflow counter move on. The loss of a single sample does not introduce a loss of accuracy, but is easily noticeable for certain specific instructions. This issue is expected to be addressed along with the issue of PEBS cross-mapped counters with a slow-path proposal. Fixes: 79f3e3b58386 ("KVM: x86/pmu: Reprogram PEBS event to emulate guest PEBS counter") Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-3-likexu@tencent.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-28KVM: x86/pmu: Avoid setting BIT_ULL(-1) to pmu->host_cross_mapped_maskLike Xu
In the extreme case of host counters multiplexing and contention, the perf_event requested by the guest's pebs counter is not allocated to any actual physical counter, in which case hw.idx is bookkept as -1, resulting in an out-of-bounds access to host_cross_mapped_mask. Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations") Signed-off-by: Like Xu <likexu@tencent.com> Link: https://lore.kernel.org/r/20220831085328.45489-2-likexu@tencent.com [sean: expand comment to explain how a negative idx can be encountered] Signed-off-by: Sean Christopherson <seanjc@google.com>
2022-09-29kbuild: build init/built-in.a just onceMasahiro Yamada
Kbuild builds init/built-in.a twice; first during the ordinary directory descending, second from scripts/link-vmlinux.sh. We do this because UTS_VERSION contains the build version and the timestamp. We cannot update it during the normal directory traversal since we do not yet know if we need to update vmlinux. UTS_VERSION is temporarily calculated, but omitted from the update check. Otherwise, vmlinux would be rebuilt every time. When Kbuild results in running link-vmlinux.sh, it increments the version number in the .version file and takes the timestamp at that time to really fix UTS_VERSION. However, updating the same file twice is a footgun. To avoid nasty timestamp issues, all build artifacts that depend on init/built-in.a are atomically generated in link-vmlinux.sh, where some of them do not need rebuilding. To fix this issue, this commit changes as follows: [1] Split UTS_VERSION out to include/generated/utsversion.h from include/generated/compile.h include/generated/utsversion.h is generated just before the vmlinux link. It is generated under include/generated/ because some decompressors (s390, x86) use UTS_VERSION. [2] Split init_uts_ns and linux_banner out to init/version-timestamp.c from init/version.c init_uts_ns and linux_banner contain UTS_VERSION. During the ordinary directory descending, they are compiled with __weak and used to determine if vmlinux needs relinking. Just before the vmlinux link, they are compiled without __weak to embed the real version and timestamp. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2022-09-29nios2: move core-y in arch/nios2/Makefile to arch/nios2/KbuildMasahiro Yamada
Use obj-y to clean up Makefile. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2022-09-28x86/cacheinfo: Add a cpu_llc_shared_mask() UP variantBorislav Petkov
On a CONFIG_SMP=n kernel, the LLC shared mask is 0, which prevents __cache_amd_cpumap_setup() from doing the L3 masks setup, and more specifically from setting up the shared_cpu_map and shared_cpu_list files in sysfs, leading to lscpu from util-linux getting confused and segfaulting. Add a cpu_llc_shared_mask() UP variant which returns a mask with a single bit set, i.e., for CPU0. Fixes: 2b83809a5e6d ("x86/cpu/amd: Derive L3 shared_cpu_map from cpu_llc_shared_mask") Reported-by: Saurabh Sengar <ssengar@linux.microsoft.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/1660148115-302-1-git-send-email-ssengar@linux.microsoft.com
2022-09-28mfd: stmpe: Switch to using gpiod APIDmitry Torokhov
This patch switches the driver away from legacy gpio/of_gpio API to gpiod API, and removes use of of_get_named_gpio_flags() which I want to make private to gpiolib. We also need to patch relevant DTS files, as the original code relied on the fact that of_get_named_gpio_flags() would fetch any data encoded in GPIO flags, even if it does not reflect valid flags for a GPIO. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/YxeS1BK2OBH1P/kO@google.com
2022-09-28mfd/omap1: htc-i2cpld: Convert to a pure GPIO driverLinus Walleij
Instead of passing GPIO numbers pertaining to ourselves through platform data, just request GPIO descriptors from our own GPIO chips and use them, and cut down on the unnecessary complexity. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Janusz Krzysztofik <jmkrzyszt@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Cory Maccarrone <darkstar6262@gmail.com> Cc: linux-omap@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20220905115810.5987-1-linus.walleij@linaro.org
2022-09-28hyperv: simplify and rename generate_guest_idLi kunyu
The generate_guest_id function is more suitable for use after the following modifications. 1. The return value of the function is modified to u64. 2. Remove the d_info1 and d_info2 parameters from the function, keep the u64 type kernel_version parameter. 3. Rename the function to make it clearly a Hyper-V related function, and modify it to hv_generate_guest_id. Signed-off-by: Li kunyu <kunyu@nfschina.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com> Link: https://lore.kernel.org/r/20220928064046.3545-1-kunyu@nfschina.com Signed-off-by: Wei Liu <wei.liu@kernel.org>
2022-09-28powerpc: Ignore DSI error caused by the copy/paste instructionHaren Myneni
The data storage interrupt (DSI) error will be generated when the paste operation is issued on the suspended Nest Accelerator (NX) window due to NX state changes. The hypervisor expects the partition to ignore this error during page fault handling. To differentiate DSI caused by an actual HW configuration or by the NX window, a new “ibm,pi-features” type value is defined. Byte 0, bit 3 of pi-attribute-specifier-type is now defined to indicate this DSI error. If this error is not ignored, the user space can get SIGBUS when the NX request is issued. This patch adds changes to read ibm,pi-features property and ignore DSI error during page fault handling if MMU_FTR_NX_DSI is defined. Signed-off-by: Haren Myneni <haren@linux.ibm.com> [mpe: Mention PAPR version in comment] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/b9cd844b85eb8f70459109ce1b14e44c4cc85fa7.camel@linux.ibm.com
2022-09-28powerpc: Reverse stack frame marker on little endianMichael Ellerman
On little endian the stack frame marker appears reversed when dumping memory sequentially, as is typical in xmon or gdb, eg: c000000004733e40 0000000000000000 0000000000000000 |................| c000000004733e50 0000000000000000 0000000000000000 |................| c000000004733e60 0000000000000000 0000000000000000 |................| c000000004733e70 5347455200000000 0000000000000000 |SGER............| c000000004733e80 a700000000000000 708897f7ff7f0000 |........p.......| c000000004733e90 0073428fff7f0000 208997f7ff7f0000 |.sB..... .......| c000000004733ea0 0100000000000000 ffffffffffffffff |................| c000000004733eb0 0000000000000000 0000000000000000 |................| To make it easier to recognise, reverse the value on little endian, so it always appears as "REGS", eg: c000000004733e70 5245475300000000 0000000000000000 |REGS............| Acked-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220927150419.1503001-2-mpe@ellerman.id.au
2022-09-28powerpc: Make stack frame marker upper caseMichael Ellerman
Now that the stack frame regs marker is only 32-bits it is not as obvious in memory dumps and easier to miss, eg: c000000004733e40 0000000000000000 0000000000000000 |................| c000000004733e50 0000000000000000 0000000000000000 |................| c000000004733e60 0000000000000000 0000000000000000 |................| c000000004733e70 7367657200000000 0000000000000000 |sger............| c000000004733e80 a700000000000000 708897f7ff7f0000 |........p.......| c000000004733e90 0073428fff7f0000 208997f7ff7f0000 |.sB..... .......| c000000004733ea0 0100000000000000 ffffffffffffffff |................| c000000004733eb0 0000000000000000 0000000000000000 |................| So make it upper case to make it stand out a bit more: c000000004733e70 5347455200000000 0000000000000000 |SGER............| Acked-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220927150419.1503001-1-mpe@ellerman.id.au
2022-09-28powerpc/kprobes: Fix null pointer reference in arch_prepare_kprobe()Li Huafei
I found a null pointer reference in arch_prepare_kprobe(): # echo 'p cmdline_proc_show' > kprobe_events # echo 'p cmdline_proc_show+16' >> kprobe_events Kernel attempted to read user page (0) - exploit attempt? (uid: 0) BUG: Kernel NULL pointer dereference on read at 0x00000000 Faulting instruction address: 0xc000000000050bfc Oops: Kernel access of bad area, sig: 11 [#1] LE PAGE_SIZE=64K MMU=Radix SMP NR_CPUS=2048 NUMA PowerNV Modules linked in: CPU: 0 PID: 122 Comm: sh Not tainted 6.0.0-rc3-00007-gdcf8e5633e2e #10 NIP: c000000000050bfc LR: c000000000050bec CTR: 0000000000005bdc REGS: c0000000348475b0 TRAP: 0300 Not tainted (6.0.0-rc3-00007-gdcf8e5633e2e) MSR: 9000000000009033 <SF,HV,EE,ME,IR,DR,RI,LE> CR: 88002444 XER: 20040006 CFAR: c00000000022d100 DAR: 0000000000000000 DSISR: 40000000 IRQMASK: 0 ... NIP arch_prepare_kprobe+0x10c/0x2d0 LR arch_prepare_kprobe+0xfc/0x2d0 Call Trace: 0xc0000000012f77a0 (unreliable) register_kprobe+0x3c0/0x7a0 __register_trace_kprobe+0x140/0x1a0 __trace_kprobe_create+0x794/0x1040 trace_probe_create+0xc4/0xe0 create_or_delete_trace_kprobe+0x2c/0x80 trace_parse_run_command+0xf0/0x210 probes_write+0x20/0x40 vfs_write+0xfc/0x450 ksys_write+0x84/0x140 system_call_exception+0x17c/0x3a0 system_call_vectored_common+0xe8/0x278 --- interrupt: 3000 at 0x7fffa5682de0 NIP: 00007fffa5682de0 LR: 0000000000000000 CTR: 0000000000000000 REGS: c000000034847e80 TRAP: 3000 Not tainted (6.0.0-rc3-00007-gdcf8e5633e2e) MSR: 900000000280f033 <SF,HV,VEC,VSX,EE,PR,FP,ME,IR,DR,RI,LE> CR: 44002408 XER: 00000000 The address being probed has some special: cmdline_proc_show: Probe based on ftrace cmdline_proc_show+16: Probe for the next instruction at the ftrace location The ftrace-based kprobe does not generate kprobe::ainsn::insn, it gets set to NULL. In arch_prepare_kprobe() it will check for: ... prev = get_kprobe(p->addr - 1); preempt_enable_no_resched(); if (prev && ppc_inst_prefixed(ppc_inst_read(prev->ainsn.insn))) { ... If prev is based on ftrace, 'ppc_inst_read(prev->ainsn.insn)' will occur with a null pointer reference. At this point prev->addr will not be a prefixed instruction, so the check can be skipped. Check if prev is ftrace-based kprobe before reading 'prev->ainsn.insn' to fix this problem. Fixes: b4657f7650ba ("powerpc/kprobes: Don't allow breakpoints on suffixes") Signed-off-by: Li Huafei <lihuafei1@huawei.com> [mpe: Trim oops] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220923093253.177298-1-lihuafei1@huawei.com
2022-09-28ocxl: Remove the unneeded result variableye xingchen
Return the value opal_npu_spa_clear_cache() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Acked-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220906072006.337099-1-ye.xingchen@zte.com.cn
2022-09-28powerpc/pseries/vas: Remove the unneeded result variableye xingchen
Return the value vas_register_coproc_api() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220825072657.229168-1-ye.xingchen@zte.com.cn
2022-09-28powerpc/smp: poll cpu_callin_map more aggressively in __cpu_up()Nathan Lynch
At boot time, it is not necessary to delay between polls of cpu_callin_map when waiting for a kicked CPU to come up. Remove the delay intervals, but preserve the overall deadline (five seconds). At run time, the first poll result is usually negative and we incur a sleeping wait. If we spin on the callin word for a short time first, we can reduce __cpu_up() from dozens of milliseconds to under 1ms in the common case on a P9 LPAR: $ ppc64_cpu --smt=off $ bpftrace -e 'kprobe:__cpu_up { @start[tid] = nsecs; } kretprobe:__cpu_up /@start[tid]/ { @us = hist((nsecs - @start[tid]) / 1000); delete(@start[tid]); }' -c 'ppc64_cpu --smt=on' Before: @us: [16K, 32K) 85 |@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@| [32K, 64K) 13 |@@@@@@@ | After: @us: [128, 256) 95 |@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@| [256, 512) 3 |@ | Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220926220250.157022-1-nathanl@linux.ibm.com
2022-09-28powerpc/rtas: block error injection when locked downNathan Lynch
The error injection facility on pseries VMs allows corruption of arbitrary guest memory, potentially enabling a sufficiently privileged user to disable lockdown or perform other modifications of the running kernel via the rtas syscall. Block the PAPR error injection facility from being opened or called when locked down. Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Acked-by: Paul Moore <paul@paul-moore.com> (LSM) Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220926131643.146502-3-nathanl@linux.ibm.com
2022-09-28powerpc/pseries: block untrusted device tree changes when locked downNathan Lynch
The /proc/powerpc/ofdt interface allows the root user to freely alter the in-kernel device tree, enabling arbitrary physical address writes via drivers that could bind to malicious device nodes, thus making it possible to disable lockdown. Historically this interface has been used on the pseries platform to facilitate the runtime addition and removal of processor, memory, and device resources (aka Dynamic Logical Partitioning or DLPAR). Years ago, the processor and memory use cases were migrated to designs that happen to be lockdown-friendly: device tree updates are communicated directly to the kernel from firmware without passing through untrusted user space. I/O device DLPAR via the "drmgr" command in powerpc-utils remains the sole legitimate user of /proc/powerpc/ofdt, but it is already broken in lockdown since it uses /dev/mem to allocate argument buffers for the rtas syscall. So only illegitimate uses of the interface should see a behavior change when running on a locked down kernel. Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Acked-by: Paul Moore <paul@paul-moore.com> (LSM) Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220926131643.146502-2-nathanl@linux.ibm.com
2022-09-28powerpc/udbg: Remove extern function prototypesPali Rohár
'extern' keyword is pointless and deprecated for function prototypes. Signed-off-by: Pali Rohár <pali@kernel.org> Suggested-by: Gabriel Paubert <paubert@iram.es> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220822231751.16973-1-pali@kernel.org
2022-09-28powerpc/boot: Explicitly disable usage of SPE instructionsPali Rohár
uImage boot wrapper should not use SPE instructions, like kernel itself. Boot wrapper has already disabled Altivec and VSX instructions but not SPE. Options -mno-spe and -mspe=no already set when compilation of kernel, but not when compiling uImage wrapper yet. Fix it. Cc: stable@vger.kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220827134454.17365-1-pali@kernel.org
2022-09-28powerpc: Include e500v1_power_isa.dtsi for remaining e500v1 platformsPali Rohár
There are still some board device tree files without Power ISA properties which have Freescale e500v1 cores, namely those which are based on Freescale mpc8540, mpc8541, mpc8555 and mpc8560 processors. So include newly introduced e500v1_power_isa.dtsi file in devices tree files with those processors. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220902212103.22534-2-pali@kernel.org
2022-09-28powerpc: Fix SPE Power ISA properties for e500v1 platformsPali Rohár
Commit 2eb28006431c ("powerpc/e500v2: Add Power ISA properties to comply with ePAPR 1.1") introduced new include file e500v2_power_isa.dtsi and should have used it for all e500v2 platforms. But apparently it was used also for e500v1 platforms mpc8540, mpc8541, mpc8555 and mpc8560. e500v1 cores compared to e500v2 do not support double precision floating point SPE instructions. Hence power-isa-sp.fd should not be set on e500v1 platforms, which is in e500v2_power_isa.dtsi include file. Fix this issue by introducing a new e500v1_power_isa.dtsi include file and use it in all e500v1 device tree files. Fixes: 2eb28006431c ("powerpc/e500v2: Add Power ISA properties to comply with ePAPR 1.1") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220902212103.22534-1-pali@kernel.org
2022-09-28powerpc/perf: Fix branch_filter support for multiple filtersAthira Rajeev
For PERF_SAMPLE_BRANCH_STACK sample type, different branch_sample_type ie branch filters are supported. The branch filters are requested via event attribute "branch_sample_type". Multiple branch filters can be passed in event attribute. eg: $ perf record -b -o- -B --branch-filter any,ind_call true None of the Power PMUs support having multiple branch filters at the same time. Branch filters for branch stack sampling is set via MMCRA IFM bits [32:33]. But currently when requesting for multiple filter types, the "perf record" command does not report any error. eg: $ perf record -b -o- -B --branch-filter any,save_type true $ perf record -b -o- -B --branch-filter any,ind_call true The "bhrb_filter_map" function in PMU driver code does the validity check for supported branch filters. But this check is done for single filter. Hence "perf record" will proceed here without reporting any error. Fix power_pmu_event_init() to return EOPNOTSUPP when multiple branch filters are requested in the event attr. After the fix: $ perf record --branch-filter any,ind_call -- ls Error: cycles: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat' Reported-by: Disha Goel <disgoel@linux.vnet.ibm.com> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Tested-by: Disha Goel<disgoel@linux.vnet.ibm.com> Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com> Reviewed-by: Kajol Jain <kjain@linux.ibm.com> [mpe: Tweak comment and change log wording] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220921145255.20972-1-atrajeev@linux.vnet.ibm.com
2022-09-28powerpc/64s/interrupt: halt early boot interrupts if paca is not set upNicholas Piggin
Ensure r13 is zero from very early in boot until it gets set to the boot paca pointer. This allows early program and mce handlers to halt if there is no valid paca, rather than potentially run off into the weeds. This preserves register and memory contents for low level debugging tools. Nothing could be printed to console at this point in any case because even udbg is only set up after the boot paca is set, so this shouldn't be missed. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220926055620.2676869-6-npiggin@gmail.com
2022-09-28powerpc/64: don't set boot CPU's r13 to paca until the structure is set upNicholas Piggin
The idea is to get to the point where if r13 is non-zero, then it should contain a reasonable paca. This can be used in early boot program check and machine check handlers to avoid running off into the weeds if they hit before r13 has a paca. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220926055620.2676869-5-npiggin@gmail.com
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