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2016-05-09MIPS: Don't unwind to user mode with EVAJames Hogan
When unwinding through IRQs and exceptions, the unwinding only continues if the PC is a kernel text address, however since EVA it is possible for user and kernel address ranges to overlap, potentially allowing unwinding to continue to user mode if the user PC happens to be in the kernel text address range. Adjust the check to also ensure that the register state from before the exception is actually running in kernel mode, i.e. !user_mode(regs). I don't believe any harm can come of this problem, since the PC is only output, the stack pointer is checked to ensure it resides within the task's stack page before it is dereferenced in search of the return address, and the return address register is similarly only output (if the PC is in a leaf function or the beginning of a non-leaf function). However unwind_stack() is only meant for unwinding kernel code, so to be correct the unwind should stop there. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/11700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Fill in current_cpu_data.coreFlorian Fainelli
Read the core ID in bmips_smp_finish() for BMIPS5000 CPUs to get appropriate processor parenting in set_cpu_sibling_map(). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: jaedon.shin@gmail.com Cc: dragan.stancevic@gmail.com Cc: jogo@openwrt.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12380/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Remove maxcpus from BCM97435SVMB DTSFlorian Fainelli
Now that SMP properly works on 7435, do not restrict the number of core, unleash them all. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: jaedon.shin@gmail.com Cc: dragan.stancevic@gmail.com Cc: jogo@openwrt.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12379/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Add missing 7038 L1 register cells to BCM7435Florian Fainelli
7435 has 4 7038 L1 base register address for each of its Core + TP (for a total of 4 threads of execution), add the two missing cells for Core 1. We are providing HW interrupts 2/3 even for Core 1/TP0/TP1 because that's what they are, and we can later decide to remap these in software to provide proper interrupt affinity/parenting. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: jaedon.shin@gmail.com Cc: dragan.stancevic@gmail.com Cc: jogo@openwrt.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12378/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Make whitespacely correct.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Add Whirlwind (BMIPS5200) initialization codeFlorian Fainelli
Import bmips_5xxx_init.S from the stblinux-3.3 tree, and to make sure that this would work nicely with a BMIPS multiplatform kernel (with BMIPS330, BMIPS43XX and BMIPS5000 enabled), update soft_reset to check for the BMIPS5200 processor id (PRID_IMP_BMIPS5200) and execute bmips_5xxx_init for these processors to bring them online. Tested on 7425, 7429 and 7435 with CPU hotplug. 7435 SMP still needs some additional changes in the L1 interrupt area to work properly with interrupt affinity. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: jaedon.shin@gmail.com Cc: dragan.stancevic@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/12377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: BMIPS: Fix PRID_IMP_BMIPS5000 masking for BMIPS5200Florian Fainelli
BMIPS5000 have a PrID value of 0x5A00 and BMIPS5200 have a PrID value of 0x5B00, which, masked with 0x5A00, returns 0x5A00. Update all conditionals on the PrID to cover both variants since we are going to need this to enable BMIPS5200 SMP. The existing check, masking with 0xFF00 would not cover BMIPS5200 at all. Fixes: 68e6a78373a6d ("MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)") Fixes: 6465460c92a85 ("MIPS: BMIPS: change compile time checks to runtime checks") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Cc: jaedon.shin@gmail.com Cc: jfraser@broadcom.com Cc: pgynther@google.com Cc: dragan.stancevic@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12279/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Don't BUG_ON when no IPI domain is foundPaul Burton
Commit fbde2d7d8290 ("MIPS: Add generic SMP IPI support") introduced code that BUG_ON's in the case of a kernel that supports IPI domains but does not have one at runtime. This case is possible on Malta where for IPIs we may use either the GIC (which has an IPI IRQ domain implementation) or core-local software interrupts between VPEs (which do not currently have an IPI IRQ domain implementation). We can not know which will be used until runtime when we know whether a GIC is actually present, and if we run on a system with multiple VPEs and no GIC then the BUG_ON is hit. Commit 19fb5818ed60 ("IPS: Fix broken malta qemu") worked around this for the single-core single-VPE case typically seen using QEMU, but does not catch the multi-VPE case. This patch removes the insufficient CPU presence check that was added and works around the bug differently, effectively reverting that commit. A simple way to reproduce this bug is by using QEMU, which partially implements the MT ASE but does not implement the GIC as of version 2.5. Using "-cpu 34Kf -smp 2" will present a system with 2 VPEs in one core & no GIC, hitting the BUG_ON. Given that we're post-merge-window on the way to v4.6, avoid this by just returning from mips_smp_ipi_init when no IPI IRQ domain is found. Ideally at some point all IPI implementations would be converted to the same IPI IRQ domain interface & we'd be able to restore the check. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Fixes: fbde2d7d8290 ("MIPS: Add generic SMP IPI support") Fixes: 19fb5818ed60 ("IPS: Fix broken malta qemu") Reverts: 19fb5818ed60 ("IPS: Fix broken malta qemu") Cc: Qais Yousef <qsyousef@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Alex Smith <alex.smith@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Fix siginfo.h to use strict posix typesJames Hogan
Commit 85efde6f4e0d ("make exported headers use strict posix types") changed the asm-generic siginfo.h to use the __kernel_* types, and commit 3a471cbc081b ("remove __KERNEL_STRICT_NAMES") make the internal types accessible only to the kernel, but the MIPS implementation hasn't been updated to match. Switch to proper types now so that the exported asm/siginfo.h won't produce quite so many compiler errors when included alone by a user program. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Christopher Ferris <cferris@google.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 2.6.30- Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12477/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09MIPS: Fix crash registers on non-crashing CPUsCorey Minyard
As part of handling a crash on an SMP system, an IPI is send to all other CPUs to save their current registers and stop. It was using task_pt_regs(current) to get the registers, but that will only be accurate if the CPU was interrupted running in userland. Instead allow the architecture to pass in the registers (all pass NULL now, but allow for the future) and then use get_irq_regs() which should be accurate as we are in an interrupt. Fall back to task_pt_regs(current) if nothing else is available. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13050/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09mips: Fix CPC_BASE_ADDR mask to match datasheetNikolay Martynov
According to 'MIPS32® interAptivTM Multiprocessing System Programmer’s Guide' CPC_BASE_ADDR takes bits [31:15]. This change is tested ith mt7621 which wasn't working without it. Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11766/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09arm/configs: Add Aspeed defconfigJoel Stanley
Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-05-09arm/configs/multi_v5: Add Aspeed ast2400Joel Stanley
This adds the Aspeed ast2400 BMC SoC to the build. The SoC has six UARTs so we need to enable the appropriate options for SERIAL_8250 Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-05-09arm/dst: Add Aspeed ast2500 device treeJoel Stanley
This adds a common device tree for all fifth generation Aspeed systems, and a board specific device tree for the ast2500 evaluation board. Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-05-09arm/dts: Add Aspeed ast2400 device treeJoel Stanley
A common device tree for all forth gen/ast2400 systems and a board specific dts for the Palmetto OpenPower developemnt machine which was used for testing. Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-05-09arm: Add Aspeed machineJoel Stanley
Aspeed devices are a common Baseboard Management Controller (BMC) system on chip containing an ARM9 or ARM11 core, off-chip DDR RAM and support for a large number of peripherals. This patch adds basic support for the ast2400 and ast2500 machines, capable of booting to a prompt in QEMU (-M palmetto-bmc), on an Palmetto OpenPower development machine, and on the ast2500 EVB. Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-05-09Merge 4.6-rc7 into tty-nextGreg Kroah-Hartman
We want the pty fixes in here as well so that patches can build on it. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-05-09ARC: Add eznps platform to Kconfig and MakefileNoam Camus
This commit should be left last since only now eznps platform is in state which one can actually use. Signed-off-by: Noam Camus <noamc@ezchip.com>
2016-05-09ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZENoam Camus
The default 256 bytes sometimes is just not enough. We usually provide earlycon=... and console=... and ip=... All this and more may need more room. Signed-off-by: Noam Camus <noamc@ezchip.com> Acked-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: [plat-eznps] Use dedicated cpu_relax()Tal Zilcer
Since the CTOP is SMT hardware multi-threaded, we need to hint the HW that now will be a very good time to do a hardware thread context switching. This is done by issuing the schd.rw instruction (binary coded here so as to not require specific revision of GCC to build the kernel). sched.rw means that Thread becomes eligible for execution by the threads scheduler after all pending read/write transactions were completed. Implementing cpu_relax_lowlatency() with barrier() Since with current semantics of cpu_relax() it may take a while till yielded CPU will get back. Signed-off-by: Noam Camus <noamc@ezchip.com> Cc: Peter Zijlstra <peterz@infradead.org> Acked-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: [plat-eznps] Use dedicated identity auxiliary register.Noam Camus
With generic "identity" num of CPUs is limited to 256 (8 bit). We use our alternative AUX register GLOBAL_ID (12 bit). Now we can support up to 4096 CPUs. Signed-off-by: Noam Camus <noamc@ezchip.com>
2016-05-09ARC: [plat-eznps] Use dedicated SMP barriersNoam Camus
NPS device got 256 cores and each got 16 HW threads (SMT). We use EZchip dedicated ISA to trigger HW scheduler of the core that current HW thread belongs to. This scheduling makes sure that data beyond barrier is available to all HW threads in core and by that to all in device (4K). Signed-off-by: Noam Camus <noamc@ezchip.com> Cc: Peter Zijlstra <peterz@infradead.org>
2016-05-09ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchgNoam Camus
We need our own implementaions since we lack LLSC support. Our extended ISA provided with optimized solution for all 32bit operations we see in these three headers. Signed-off-by: Noam Camus <noamc@ezchip.com>
2016-05-09ARC: [plat-eznps] Use dedicated user stack topNoam Camus
NPS use special mapping right below TASK_SIZE. Hence we need to lower STACK_TOP so that user stack won't overlap NPS special mapping. Signed-off-by: Noam Camus <noamc@ezchip.com> Acked-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: [plat-eznps] Add eznps platformNoam Camus
This platform include boards: Hardware Emulator (HE) Simulator based upon nSIM. Signed-off-by: Noam Camus <noamc@ezchip.com>
2016-05-09ARC: [plat-eznps] Add eznps board defconfig and dtsNoam Camus
Adding default configuration file and DTS file Signed-off-by: Noam Camus <noamc@ezchip.com>
2016-05-09ARC: Mark secondary cpu online only after all HW setup is doneNoam Camus
In SMP setup, master loops for each_present_cpu calling cpu_up(). For ARC it returns as soon as new cpu's status becomes online, However secondary may still do HW initializing, machine or platform hook level. So turn secondary online only after all HW setup is done. Signed-off-by: Noam Camus <noamc@ezchip.com> Acked-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: rwlock: disable interrupts in !LLSC variantNoam Camus
If we hold rwlock and interrupt occures we may end up spinning on it for ever during softirq. Note that this lock is an internal lock and since the lock is free to be used from any context, the lock needs to be IRQ-safe. Below you may see an example for interrupt we get while nl_table_lock is holding its rw->lock_mutex and we spinned on it for ever. The concept for the fix was taken from SPARC. [2015-05-12 19:16:12] Stack Trace: [2015-05-12 19:16:12] arc_unwind_core+0xb8/0x11c [2015-05-12 19:16:12] dump_stack+0x68/0xac [2015-05-12 19:16:12] _raw_read_lock+0xa8/0xac [2015-05-12 19:16:12] netlink_broadcast_filtered+0x56/0x35c [2015-05-12 19:16:12] nlmsg_notify+0x42/0xa4 [2015-05-12 19:16:13] neigh_update+0x1fe/0x44c [2015-05-12 19:16:13] neigh_event_ns+0x40/0xa4 [2015-05-12 19:16:13] arp_process+0x46e/0x5a8 [2015-05-12 19:16:13] __netif_receive_skb_core+0x358/0x500 [2015-05-12 19:16:13] process_backlog+0x92/0x154 [2015-05-12 19:16:13] net_rx_action+0xb8/0x188 [2015-05-12 19:16:13] __do_softirq+0xda/0x1d8 [2015-05-12 19:16:14] irq_exit+0x8a/0x8c [2015-05-12 19:16:14] arch_do_IRQ+0x6c/0xa8 [2015-05-12 19:16:14] handle_interrupt_level1+0xe4/0xf0 Signed-off-by: Noam Camus <noamc@ezchip.com> Acked-by: Peter Zijlstra <peterz@infradead.org>
2016-05-09ARC: Make vmalloc size configurableNoam Camus
On ARC, lower 2G of address space is translated and used for - user vaddr space (region 0 to 5) - unused kernel-user gutter (region 6) - kernel vaddr space (region 7) where each region simply represents 256MB of address space. The kernel vaddr space of 256MB is used to implement vmalloc, modules So far this was enough, but not on EZChip system with 4K CPUs (given that per cpu mechanism uses vmalloc for allocating chunks) So allow VMALLOC_SIZE to be configurable by expanding down into the unused kernel-user gutter region which at default 256M was excessive anyways. Also use _BITUL() to fix a build error since PGDIR_SIZE cannot use "1UL" as called from assembly code in mm/tlbex.S Signed-off-by: Noam Camus <noamc@ezchip.com> [vgupta: rewrote changelog, debugged bootup crash due to int vs. hex] Acked-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: clean out UAPI byteorder.h clean off Kconfig symbolNoam Camus
UAPI header should not use Kconfig items Use __BIG_ENDIAN__ defined as a compiler intrinsic Signed-off-by: Noam Camus <noamc@ezchip.com> [vgupta: fix changelog] Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: RIP arc_{get|set}_core_freq() clk APIAlexey Brodkin
There are no more users of this - so RIP! Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> [vgupta: update changelog] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: Don't try to use value of top level clock-frequency in DTAlexey Brodkin
We no longer use it and instead a real clk device such as fixed-clk instance is fed to timers etc. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> [vgupta: broken out of a bigger patch, rewrote changelog] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: use fixed frequencies in arc_set_early_base_baud()Alexey Brodkin
UARTs usually have fixed clock so we're switching to use of constant values instead of something derived from core clock frequency. Among other things this will allow us to get rid of arc_{get|set}_core_freq() and switch to generic clock framework later on. Acked-by: Christian Ruppert <christian.ruppert@alitech.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: [intc-*] switch to linear domainVineet Gupta
Now that we have Timers probed from DT, don't need legacy domain This however requires mapping to be called explicitly for the IRQ which still can't (and probably never) be probed from DT such as IPI and SOFTIRQ Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: [intc-*] Do a domain lookup in primary handler for hwirq -> linux virqVineet Gupta
The primary interrupt handler arch_do_IRQ() was passing hwirq as linux virq to core code. This was fragile and worked so far as we only had legacy/linear domains. This came out of a rant by Marc Zyngier. http://lists.infradead.org/pipermail/linux-snps-arc/2015-December/000298.html Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Noam Camus <noamc@ezchip.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: irq: export some IRQs againVineet Gupta
This will be needed for switching to linear irq domain as irq_create_mapping() called by intr code needs the IRQ numbers in addition to existing usage in mcip.c for requesting the irq Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: clocksource: DT based probeVineet Gupta
- Remove explicit clocksource setup and let it be done by OF framework by defining CLOCKSOURCE_OF_DECLARE() for various timers - This allows multiple clocksources to be potentially registered simultaneouly: previously we could only do one - as all of them had same arc_counter_setup() routine for registration - Setup routines also ensure that the underlying timer actually exists. - Remove some of the panic() calls if underlying timer is NOT detected as fallback clocksource might still be available 1. If GRFC doesn't exist, jiffies clocksource gets registered anyways 2. if RTC doesn't exist, TIMER1 can take over (as it is always present) Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: clockevent: DT based probeVineet Gupta
- timer frequency is derived from DT (no longer rely on top level DT "clock-frequency" probed early and exported by asm/clk.h) - TIMER0_IRQ need not be exported across arch code, confined to intc as it is property of same - Any failures in clockevent setup are considered pedantic and system panic()'s as there is no generic fallback (unlike clocksource where a jiffies based soft clocksource always exists) Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: [dts] Introduce Timer bindingsVineet Gupta
ARC Timers have historically been probed directly. As precursor to start probing Timers thru DT introduce these bindings Note that to keep series bisectable, these bindings are not yet used in code. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: devicetree@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: [dts] Add clk feeding into timers to DTsVineet Gupta
This allows us to introduce timers in DT in next commit The core clk frequency hack in AXS103 platform is also extended, where the core clk feeding into timers is updated in-place in FDT. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: [dts] Rename cpu_intc -> core_intcVineet Gupta
This is again for future changes to use common DTSI for timers which refer to @core_intc Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARCv2: [dts]: Introduce HS38 specific include DTS ...Vineet Gupta
... and add them to plat-sim DTS. This allows for future change to introduce timers in DT in single place Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: clockevent: Prepare for DT based probeNoam Camus
- call clocksource_probe() - This in turns needs of_clk_init() to be called earlier Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Noam Camus <noamc@ezchip.com> [vgupta: broken off from a bigger patch] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: clockevent: switch to cpu notifier for clockevent setupNoam Camus
ARC Timers so far have been handled as "legacy" w/o explicit description in DT. This poses challenge for newer platforms wanting to use them. This series will eventually help move timers over to DT. This patch does a small change of using a CPU notifier to set clockevent on non-boot CPUs. So explicit setup is done only on boot CPU (which will later be done by DT) Signed-off-by: Noam Camus <noamc@ezchip.com> [vgupta: broken off from a bigger patch] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: [plat-axs] Refactor core freq get/setVineet Gupta
Reduces diff in future patches ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: opencode arc_request_percpu_irqVineet Gupta
- The idea is to remove the API usage since it has a subltle design flaw - relies on being called on cpu0 first. This is true for some early per cpu irqs such as TIMER/IPI, but not for late probed per cpu peripherals such a perf. And it's usage in perf has already bitten us once: see c6317bc7c5ab ("ARCv2: perf: Ensure perf intr gets enabled on all cores") where we ended up open coding it anyways - The seeming duplication will go away once we start using cpu notifier for timer setup Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09ARC: [intc-compact] setup TIMER as percpu_devVineet Gupta
This removes the quirk from arc_request_percpu_irq() and paves way for future simplifications Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-05-09Merge tag 'v4.6-rc7' into drm-nextDave Airlie
Merge this back as we've built up a fair few conflicts, and I have some newer trees to pull in.
2016-05-08ARM: sun7i: dt: Add pll3 and pll7 clocksPriit Laes
Enable pll3 and pll7 clocks that are needed by display clocks. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-05-08ARM: dts: sunxi: Add a olinuxino-lime2-emmcOlliver Schinagl
There are 3 kinds of OLinuXino Lime2 boards. One without any on board storage, one with NAND storage and one with eMMC storage. This patch adds the eMMC variant of boards. eMMC storage is different from a regular SD card in that it is soldered on the board and cannot be changed. Additionally, it shares pins with the NAND module and with the second SPI port. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> [Maxime: Removed the change log from the commit log] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
generated by cgit (git 2.34.1) at 2025-09-14 23:24:31 +0000