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2024-01-03RISC-V: hwprobe: Clarify cpus size parameterAndrew Jones
The "count" parameter associated with the 'cpus' parameter of the hwprobe syscall is the size in bytes of 'cpus'. Naming it 'cpu_count' may mislead users (it did me) to think it's the number of CPUs that are or can be represented by 'cpus' instead. This is particularly easy (IMO) to get wrong since 'cpus' is documented to be defined by CPU_SET(3) and CPU_SET(3) also documents a CPU_COUNT() (the number of CPUs in set) macro. CPU_SET(3) refers to the size of cpu sets with 'setsize'. Adopt 'cpusetsize' for the hwprobe parameter and specifically state it is in bytes in Documentation/riscv/hwprobe.rst to clarify. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20231122164700.127954-7-ajones@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-03RISC-V: Remove the removed single-letter extensionsPalmer Dabbelt
There were a few single-letter extensions that we had references to floating around in the kernel, but that never ended up as actual ISA specs and have mostly been replaced by multi-letter extensions. This removes the references to those extensions. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231110175903.2631-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-03arch/x86: Fix typosBjorn Helgaas
Fix typos, most reported by "codespell arch/x86". Only touches comments, no code changes. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20240103004011.1758650-1-helgaas@kernel.org
2024-01-03Merge branches 'apple/dart', 'arm/rockchip', 'arm/smmu', 'virtio', ↵Joerg Roedel
'x86/vt-d', 'x86/amd' and 'core' into next
2024-01-02Merge tag 'kvm-riscv-6.8-1' of https://github.com/kvm-riscv/linux into HEADPaolo Bonzini
KVM/riscv changes for 6.8 part #1 - KVM_GET_REG_LIST improvement for vector registers - Generate ISA extension reg_list using macros in get-reg-list selftest - Steal time account support along with selftest
2024-01-02Merge tag 'kvm-s390-next-6.8-1' of ↵Paolo Bonzini
https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD - uvdevice fixed additional data return length - stfle (feature indication) vsie fixes and minor cleanup
2024-01-02Merge tag 'loongarch-kvm-6.8' of ↵Paolo Bonzini
git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson into HEAD LoongArch KVM changes for v6.8 1. Optimization for memslot hugepage checking. 2. Cleanup and fix some HW/SW timer issues. 3. Add LSX/LASX (128bit/256bit SIMD) support.
2024-01-02ARM: sun9i: smp: fix return code check of of_property_match_stringStefan Wahren
of_property_match_string returns an int; either an index from 0 or greater if successful or negative on failure. Even it's very unlikely that the DT CPU node contains multiple enable-methods these checks should be fixed. This patch was inspired by the work of Nick Desaulniers. Link: https://lore.kernel.org/lkml/20230516-sunxi-v1-1-ac4b9651a8c1@google.com/T/ Cc: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20231228193903.9078-2-wahrenst@gmx.net Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-02ARM: sun9i: smp: Fix array-index-out-of-bounds read in sunxi_mc_smp_initStefan Wahren
Running a multi-arch kernel (multi_v7_defconfig) on a Raspberry Pi 3B+ with enabled CONFIG_UBSAN triggers the following warning: UBSAN: array-index-out-of-bounds in arch/arm/mach-sunxi/mc_smp.c:810:29 index 2 is out of range for type 'sunxi_mc_smp_data [2]' CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.7.0-rc6-00248-g5254c0cbc92d Hardware name: BCM2835 unwind_backtrace from show_stack+0x10/0x14 show_stack from dump_stack_lvl+0x40/0x4c dump_stack_lvl from ubsan_epilogue+0x8/0x34 ubsan_epilogue from __ubsan_handle_out_of_bounds+0x78/0x80 __ubsan_handle_out_of_bounds from sunxi_mc_smp_init+0xe4/0x4cc sunxi_mc_smp_init from do_one_initcall+0xa0/0x2fc do_one_initcall from kernel_init_freeable+0xf4/0x2f4 kernel_init_freeable from kernel_init+0x18/0x158 kernel_init from ret_from_fork+0x14/0x28 Since the enabled method couldn't match with any entry from sunxi_mc_smp_data, the value of the index shouldn't be used right after the loop. So move it after the check of ret in order to have a valid index. Fixes: 1631090e34f5 ("ARM: sun9i: smp: Add is_a83t field") Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20231228193903.9078-1-wahrenst@gmx.net Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-02net/sched: Remove CONFIG_NET_ACT_IPT from default configsJamal Hadi Salim
Now that we are retiring the IPT action. Reviewed-by: Victor Noguiera <victor@mojatatu.com> Reviewed-by: Pedro Tammela <pctammela@mojatatu.com> Signed-off-by: Jamal Hadi Salim <jhs@mojatatu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-01-02Merge tag 'v6.8-rockchip-dts32-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt RK3036 fix for emmc init issue and stdout-path for the console on rk3036 kylin. * tag 'v6.8-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Remove rockchip,default-sample-phase from rk3036.dtsi ARM: dts: rockchip: Add stdout-path for rk3036 kylin Link: https://lore.kernel.org/r/15502825.JCcGWNJJiE@diego Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-02Merge tag 'v6.8-rockchip-dts64-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt One new boards, the CoolPi CM5 SoM and 4B SBC. Basic node for the rk3588 display controller and a bunch of small improvements for different boards, * tag 'v6.8-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits) arm64: dts: rockchip: Fix led pinctrl of lubancat 1 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b arm64: dts: rockchip: support poweroff on the rock-5b arm64: dts: rockchip: Support poweroff on Orange Pi 5 arm64: dts: rockchip: nanopc-t6 sdmmc beautification arm64: dts: rockchip: Fix rk3588 USB power-domain clocks arm64: dts: rockchip: configure eth pad driver strength for orangepi r1 plus lts arm64: dts: rockchip: Support poweroff on NanoPC-T6 arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names cleanup arm64: dts: rockchip: Add support for rk3588 based board Cool Pi CM5 EVB dt-bindings: arm: rockchip: Add Cool Pi CM5 arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B dt-bindings: arm: rockchip: Add Cool Pi 4B dt-bindings: vendor-prefixes: Add Cool Pi arm64: dts: rockchip: add gpio-line-names to rk3328-rock-pi-e arm64: dts: rockchip: make use gpio-keys for buttons on puma-haikou arm64: dts: rockchip: expose BIOS Disable feedback pin on rk3399-puma arm64: dts: rockchip: fix misleading comment in rk3399-puma-haikou.dts arm64: dts: rockchip: Add vop on rk3588 ... Link: https://lore.kernel.org/r/3711719.VqM8IeB0Os@diego Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-02Merge tag 'qcom-arm64-for-6.8-2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt A few more Qualcomm Arm64 DeviceTree updates for v6.8 This corrects the rate of the UTMI clock on IPQ6018 USB0. The SDHCI controller on SC7280 gains missing markings for being cache-coherent. For SC8180X a typo in assignment of PCIe refgen clocks is corrected, PCI controllers are marked cache-coherent, and the USB SS PHY interrupts are corrected to allow wakeup. Similarly USB HS PHY and SS PHY interrupts are corrected to allow wakeup on SDM670. On SM8550 the X3 cluster idle state is properly described, and the latency numbers are adjusted for all the idle states. The PM8550 regulator supplies on X1E are corrected to match the driver and binding, and the timer node is updated to avoid an unnecessary validation error. * tag 'qcom-arm64-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: dts: qcom: sc8180x: Fix up PCIe nodes arm64: dts: qcom: sc8180x: Mark PCIe hosts cache-coherent arm64: dts: qcom: x1e80100-qcp: Fix supplies for some LDOs in PM8550 arm64: dts: qcom: sm8550: Update idle state time requirements arm64: dts: qcom: sm8550: Separate out X3 idle state arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK arm64: dts: qcom: x1e80100: align mem timer size cells with bindings arm64: dts: qcom: sc7280: Mark SDHCI hosts as cache-coherent arm64: dts: qcom: sc8180x: fix USB SS wakeup arm64: dts: qcom: sdm670: fix USB SS wakeup arm64: dts: qcom: sdm670: fix USB DP/DM HS PHY interrupts Link: https://lore.kernel.org/r/20231231034108.3262678-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-02Merge tag 'qcom-arm32-for-6.8-2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt A few more Qualcomm Arm32 DeviceTree updates fr v6.8 The recently introduced changes to the SDX55 USB controller interrupt flags prevents the USB controller from probing. These patches corrects the PDC's interrupt-cells, so that appropriate interrupt controller (which supports both-edge interrupts) can be used instead, which resolves the issue. The SDX55 PCIe PHY base address is also adjusted, from a mistake when the node recently was transitioned to the modernized DeviceTree binding. * tag 'qcom-arm32-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: ARM: dts: qcom: sdx55: Fix the base address of PCIe PHY ARM: dts: qcom: sdx55: fix USB SS wakeup ARM: dts: qcom: sdx55: fix USB DP/DM HS PHY interrupts ARM: dts: qcom: sdx55: fix pdc '#interrupt-cells' Link: https://lore.kernel.org/r/20231231033153.3262575-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-02Merge tag 'arm-soc/for-6.8/devicetree' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM-based SoCs Device Tree changes for 6.8, please pull the following: - Rafal adds a Device Tree node for the BCM63138 high-speed UART used for Bluetooth devices * tag 'arm-soc/for-6.8/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: broadcom: Add BCM63138's high speed UART Link: https://lore.kernel.org/r/20231228085822.3656546-1-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-02Merge tag 'sprd-dt-6.8-rc1' of https://github.com/lyrazhang/linux into soc/dtArnd Bergmann
ARM: sprd: DTS and bindings for v6.8-rc1 Unisoc ARM64 DTS and bindings changes are: - Fixed a few dtb_check warnings - Add bindings for a new SoC - UMS9620 - Fixed an issue on UMS512 * tag 'sprd-dt-6.8-rc1' of https://github.com/lyrazhang/linux: arm64: dts: sprd: Change UMS512 idle-state nodename to match bindings arm64: dts: sprd: Add clock reference for pll2 on UMS512 arm64: dts: sprd: Removed unused clock references from etm nodes arm64: dts: sprd: Add support for Unisoc's UMS9620 dt-bindings: arm: Add compatible strings for Unisoc's UMS9620 arm64: dts: sprd: fix the cpu node for UMS512 Link: https://lore.kernel.org/r/20231228084958.1439115-1-chunyan.zhang@unisoc.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-02Merge tag 'qcom-arm64-defconfig-for-6.8-2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig A few more Qualcomm Arm64 defconfig updates for v6.8 This enables the base drivers necessary to boot devices on the X1E platform. The GPU clock controller for SM8450/SM8550 is enabled and the SC8280XP camera clock controller is enabled, to enable respective functionality on these platforms. * tag 'qcom-arm64-defconfig-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: defconfig: Enable Qualcomm SC8280XP camera clock controller arm64: defconfig: enable GPU clock controller for SM8[45]50 arm64: defconfig: Enable X1E80100 SoC base configs Link: https://lore.kernel.org/r/20231231034648.3262882-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-02ARM: Delete ARM11MPCore perf leftoversLinus Walleij
My commit deleting the PB11MPCore apparently left a few dangling structs in the perf event code. Fix it up. Fixes: 2560cffd2134 ("ARM: Delete ARM11MPCore (ARM11 ARMv6K SMP) support") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://lore.kernel.org/r/20231224-drop-11mpcore-fix-v1-1-d8b16d1c1fae@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-01-01powerpc: Export kvm_guest static key, for bcachefs six locksKent Overstreet
bcachefs's six locks need kvm_guest, via ower_on_cpu() -> vcpu_is_preempted() -> is_kvm_guest() Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev> Cc: linuxppc-dev@lists.ozlabs.org Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
2023-12-30MIPS: Remove unused shadow GPR support from vector irq setupThomas Bogendoerfer
Using shadow GPRs for vectored interrupts has never been used, time to remove it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-12-30MIPS: Allow vectored interrupt handler to reside everywhere for 64bitThomas Bogendoerfer
Setting up vector interrupts worked only with handlers, which resided in CKSEG0 space. This limits the kernel placement for 64bit platforms. By patching in the offset into vi_handlers[] instead of the full handler address, the vectored exception handler can load the address by itself and jump to it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2023-12-30x86/alternative: Correct feature bit debug outputBorislav Petkov (AMD)
In https://lore.kernel.org/r/20231206110636.GBZXBVvCWj2IDjVk4c@fat_crate.local I wanted to adjust the alternative patching debug output to the new changes introduced by da0fe6e68e10 ("x86/alternative: Add indirect call patching") but removed the '*' which denotes the ->x86_capability word. The correct output should be, for example: [ 0.230071] SMP alternatives: feat: 11*32+15, old: (entry_SYSCALL_64_after_hwframe+0x5a/0x77 (ffffffff81c000c2) len: 16), repl: (ffffffff89ae896a, len: 5) flags: 0x0 while the incorrect one says "... 1132+15" currently. Add back the '*'. Fixes: da0fe6e68e10 ("x86/alternative: Add indirect call patching") Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20231206110636.GBZXBVvCWj2IDjVk4c@fat_crate.local
2023-12-30RISC-V: KVM: Implement SBI STA extensionAndrew Jones
Add a select SCHED_INFO to the KVM config in order to get run_delay info. Then implement SBI STA's set-steal-time-shmem function and kvm_riscv_vcpu_record_steal_time() to provide the steal-time info to guests. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-30RISC-V: KVM: Add support for SBI STA registersAndrew Jones
KVM userspace needs to be able to save and restore the steal-time shared memory address. Provide the address through the get/set-one-reg interface with two ulong-sized SBI STA extension registers (lo and hi). 64-bit KVM userspace must not set the hi register to anything other than zero and is allowed to completely neglect saving/restoring it. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-30RISC-V: KVM: Add support for SBI extension registersAndrew Jones
Some SBI extensions have state that needs to be saved / restored when migrating the VM. Provide a get/set-one-reg register type for SBI extension registers. Each SBI extension that uses this type will have its own subtype. There are currently no subtypes defined. The next patch introduces the first one. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-30RISC-V: KVM: Add SBI STA info to vcpu_archAndrew Jones
KVM's implementation of SBI STA needs to track the address of each VCPU's steal-time shared memory region as well as the amount of stolen time. Add a structure to vcpu_arch to contain this state and make sure that the address is always set to INVALID_GPA on vcpu reset. And, of course, ensure KVM won't try to update steal- time when the shared memory address is invalid. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-30RISC-V: KVM: Add steal-update vcpu requestAndrew Jones
Add a new vcpu request to inform a vcpu that it should record its steal-time information. The request is made each time it has been detected that the vcpu task was not assigned a cpu for some time, which is easy to do by making the request from vcpu-load. The record function is just a stub for now and will be filled in with the rest of the steal-time support functions in following patches. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-30RISC-V: KVM: Add SBI STA extension skeletonAndrew Jones
Add the files and functions needed to support the SBI STA (steal-time accounting) extension. In the next patches we'll complete the functions to fully enable SBI STA support. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-30RISC-V: paravirt: Implement steal-time supportAndrew Jones
When the SBI STA extension exists we can use it to implement paravirt steal-time support. Fill in the empty pv-time functions with an SBI STA implementation and add the Kconfig knobs allowing it to be enabled. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-30RISC-V: Add SBI STA extension definitionsAndrew Jones
The SBI STA extension enables steal-time accounting. Add the definitions it specifies. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-30RISC-V: paravirt: Add skeleton for pv-time supportAndrew Jones
Add the files and functions needed to support paravirt time on RISC-V. Also include the common code needed for the first application of pv-time, which is steal-time. In the next patches we'll complete the functions to fully enable steal-time support. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-29arm64: dts: rockchip: Fix led pinctrl of lubancat 1Andy Yan
According to the schematics, the gpio control sys_led is GPIO0_C5. Fixes: 8d94da58de53 ("arm64: dts: rockchip: Add EmbedFire LubanCat 1") Reported-by: Zhang Ning <zhangn1985@outlook.com> Closes: https://lore.kernel.org/linux-rockchip/OS0P286MB06412D049D8BF7B063D41350CD95A@OS0P286MB0641.JPNP286.PROD.OUTLOOK.COM/T/#u Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20231225005055.3102743-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6John Clark
Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1. Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20231225223226.17690-1-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5bJohn Clark
Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1. Signed-off-by: John Clark <inindev@gmail.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20231225222859.17153-2-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29arm64: dts: rockchip: support poweroff on the rock-5bJohn Clark
Allow the rock-5b to poweroff its pmic. When issuing a "shutdown -h now" on the rock-5b it reboots instead. Defining 'system-power-controller' allows the rk806 to power down. Commit c699fbfdfd54 ("arm64: dts: rockchip: Support poweroff on NanoPC-T6") similarly resolves this issue for the nanopc-t6. Signed-off-by: John Clark <inindev@gmail.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20231225222859.17153-1-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29arm64: dts: rockchip: Support poweroff on Orange Pi 5Jimmy Hon
The RK806 on the Orange Pi 5 can be used to power on/off the whole board. Mark it as the system power controller. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20231227203211.1047-1-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29arm64: dts: rockchip: nanopc-t6 sdmmc beautificationJohn Clark
drop max-frequency = <200000000> as it is already defined in rk3588s.dtsi order no-sdio & no-mmc properties while we are here Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20231228173011.2863-1-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-29x86/kexec: fix incorrect end address passed to kernel_ident_mapping_init()Yuntao Wang
kernel_ident_mapping_init() takes an exclusive memory range [pstart, pend) where pend is not included in the range, while res represents an inclusive memory range [start, end] where end is considered part of the range. Passing [start, end] rather than [start, end+1) to kernel_ident_mapping_init() may result in the identity mapping for the end address not being set up. For example, when res->start is equal to res->end, kernel_ident_mapping_init() will not establish any identity mapping. Similarly, when the value of res->end is a multiple of 2M and the page table maps 2M pages, kernel_ident_mapping_init() will also not set up identity mapping for res->end. Therefore, passing res->end directly to kernel_ident_mapping_init() is incorrect, the correct end address should be `res->end + 1`. Link: https://lkml.kernel.org/r/20231221101702.20956-1-ytcoode@gmail.com Signed-off-by: Yuntao Wang <ytcoode@gmail.com> Cc: Baoquan He <bhe@redhat.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Borislav Petkov (AMD) <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Simon Horman <horms@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-12-29x86/kexec: fix incorrect argument passed to kexec_dprintk()Yuntao Wang
kexec_dprintk() expects the last argument to be kbuf.memsz, but the actual argument being passed is kbuf.bufsz. Although these two values are currently equal, it is better to pass the correct one, in case these two values become different in the future. Link: https://lkml.kernel.org/r/20231220154105.215610-1-ytcoode@gmail.com Signed-off-by: Yuntao Wang <ytcoode@gmail.com> Cc: Baoquan He <bhe@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-12-29x86/kexec: use pr_err() instead of kexec_dprintk() when an error occursYuntao Wang
When detecting an error, the current code uses kexec_dprintk() to output log message. This is not quite appropriate as kexec_dprintk() is mainly used for outputting debugging messages, rather than error messages. Replace kexec_dprintk() with pr_err(). This also makes the output method for this error log align with the output method for other error logs in this function. Additionally, the last return statement in set_page_address() is unnecessary, remove it. Link: https://lkml.kernel.org/r/20231220030124.149160-1-ytcoode@gmail.com Signed-off-by: Yuntao Wang <ytcoode@gmail.com> Cc: Baoquan He <bhe@redhat.com> Cc: Borislav Petkov (AMD) <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-12-29kasan/arm64: improve comments for KASAN_SHADOW_START/ENDAndrey Konovalov
Patch series "kasan: assorted clean-ups". Code clean-ups, nothing worthy of being backported to stable. This patch (of 11): Unify and improve the comments for KASAN_SHADOW_START/END definitions from include/asm/kasan.h and include/asm/memory.h. Also put both definitions together in include/asm/memory.h. Also clarify the related BUILD_BUG_ON checks in mm/kasan_init.c. Link: https://lkml.kernel.org/r/cover.1703188911.git.andreyknvl@google.com Link: https://lkml.kernel.org/r/140108ca0b164648c395a41fbeecb0601b1ae9e1.1703188911.git.andreyknvl@google.com Signed-off-by: Andrey Konovalov <andreyknvl@google.com> Cc: Alexander Potapenko <glider@google.com> Cc: Andrey Ryabinin <ryabinin.a.a@gmail.com> Cc: Dmitry Vyukov <dvyukov@google.com> Cc: Marco Elver <elver@google.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-12-29xtensa, kasan: define KASAN_SHADOW_ENDAndrey Konovalov
Common KASAN code might rely on the definitions of the shadow mapping start, end, and size. Define KASAN_SHADOW_END in addition to KASAN_SHADOW_START and KASAN_SHADOW_SIZE. Link: https://lkml.kernel.org/r/20231225151924.5422-1-andrey.konovalov@linux.dev Signed-off-by: Andrey Konovalov <andreyknvl@google.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312240755.MqsWuTno-lkp@intel.com/ Cc: Alexander Potapenko <glider@google.com> Cc: Andrey Ryabinin <ryabinin.a.a@gmail.com> Cc: Chris Zankel <chris@zankel.net> Cc: Dmitry Vyukov <dvyukov@google.com> Cc: Marco Elver <elver@google.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-12-29arch/mm/fault: fix major fault accounting when retrying under per-VMA lockSuren Baghdasaryan
A test [1] in Android test suite started failing after [2] was merged. It turns out that after handling a major fault under per-VMA lock, the process major fault counter does not register that fault as major. Before [2] read faults would be done under mmap_lock, in which case FAULT_FLAG_TRIED flag is set before retrying. That in turn causes mm_account_fault() to account the fault as major once retry completes. With per-VMA locks we often retry because a fault can't be handled without locking the whole mm using mmap_lock. Therefore such retries do not set FAULT_FLAG_TRIED flag. This logic does not work after [2] because we can now handle read major faults under per-VMA lock and upon retry the fact there was a major fault gets lost. Fix this by setting FAULT_FLAG_TRIED after retrying under per-VMA lock if VM_FAULT_MAJOR was returned. Ideally we would use an additional VM_FAULT bit to indicate the reason for the retry (could not handle under per-VMA lock vs other reason) but this simpler solution seems to work, so keeping it simple. [1] https://cs.android.com/android/platform/superproject/+/master:test/vts-testcase/kernel/api/drop_caches_prop/drop_caches_test.cpp [2] https://lore.kernel.org/all/20231006195318.4087158-6-willy@infradead.org/ Link: https://lkml.kernel.org/r/20231226214610.109282-1-surenb@google.com Fixes: 12214eba1992 ("mm: handle read faults under the VMA lock") Signed-off-by: Suren Baghdasaryan <surenb@google.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Gerald Schaefer <gerald.schaefer@linux.ibm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2023-12-29ubd: use the default discard granularityChristoph Hellwig
The discard granularity now defaults to a single sector, so don't set that value explicitly. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Richard Weinberger <richard@nod.at> Link: https://lore.kernel.org/r/20231228075545.362768-5-hch@lst.de Signed-off-by: Jens Axboe <axboe@kernel.dk>
2023-12-29RISC-V: KVM: Fix indentation in kvm_riscv_vcpu_set_reg_csr()Anup Patel
The indentation of "break" in kvm_riscv_vcpu_set_reg_csr() is inconsistent hence let us fix it. Fixes: c04913f2b54e ("RISCV: KVM: Add sstateen0 to ONE_REG") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312190719.kBuYl6oJ-lkp@intel.com/ Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-29RISC-V: KVM: add vector registers and CSRs in KVM_GET_REG_LISTDaniel Henrique Barboza
Add all vector registers and CSRs (vstart, vl, vtype, vcsr, vlenb) in get-reg-list. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-29RISC-V: KVM: add 'vlenb' Vector CSRDaniel Henrique Barboza
Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise it is not possible to retrieve any vector reg since we're returning EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-29RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context()Daniel Henrique Barboza
'vlenb', added to riscv_v_ext_state by commit c35f3aa34509 ("RISC-V: vector: export VLENB csr in __sc_riscv_v_state"), isn't being initialized in guest_context. If we export 'vlenb' as a KVM CSR, something we want to do in the next patch, it'll always return 0. Set 'vlenb' to riscv_v_size/32. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-29RISC-V: KVM: Make SBI uapi consistent with ISA uapiAndrew Jones
When an SBI extension cannot be enabled, that's a distinct state vs. enabled and disabled. Modify enum kvm_riscv_sbi_ext_status to accommodate it, which allows KVM userspace to tell the difference in state too, as the SBI extension register will disappear when it cannot be enabled, i.e. accesses to it return ENOENT. get-reg-list is updated as well to only add SBI extension registers to the list which may be enabled. Returning ENOENT for SBI extension registers which cannot be enabled makes them consistent with ISA extension registers. Any SBI extensions which were enabled by default are still enabled by default, if they can be enabled at all. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
2023-12-29RISC-V: KVM: Don't add SBI multi regs in get-reg-listAndrew Jones
The multi regs are derived from the single registers. Only list the single registers in get-reg-list. This also makes the SBI extension register listing consistent with the ISA extension register listing. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Haibo Xu <haibo1.xu@intel.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit (git 2.34.1) at 2025-09-20 11:46:15 +0000