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2021-01-25KVM: x86/pmu: Fix HW_REF_CPU_CYCLES event pseudo-encoding in intel_arch_events[]Like Xu
The HW_REF_CPU_CYCLES event on the fixed counter 2 is pseudo-encoded as 0x0300 in the intel_perfmon_event_map[]. Correct its usage. Fixes: 62079d8a4312 ("KVM: PMU: add proper support for fixed counter 2") Signed-off-by: Like Xu <like.xu@linux.intel.com> Message-Id: <20201230081916.63417-1-like.xu@linux.intel.com> Reviewed-by: Sean Christopherson <seanjc@google.com> Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-25KVM: x86/pmu: Fix UBSAN shift-out-of-bounds warning in intel_pmu_refresh()Like Xu
Since we know vPMU will not work properly when (1) the guest bit_width(s) of the [gp|fixed] counters are greater than the host ones, or (2) guest requested architectural events exceeds the range supported by the host, so we can setup a smaller left shift value and refresh the guest cpuid entry, thus fixing the following UBSAN shift-out-of-bounds warning: shift exponent 197 is too large for 64-bit type 'long long unsigned int' Call Trace: __dump_stack lib/dump_stack.c:79 [inline] dump_stack+0x107/0x163 lib/dump_stack.c:120 ubsan_epilogue+0xb/0x5a lib/ubsan.c:148 __ubsan_handle_shift_out_of_bounds.cold+0xb1/0x181 lib/ubsan.c:395 intel_pmu_refresh.cold+0x75/0x99 arch/x86/kvm/vmx/pmu_intel.c:348 kvm_vcpu_after_set_cpuid+0x65a/0xf80 arch/x86/kvm/cpuid.c:177 kvm_vcpu_ioctl_set_cpuid2+0x160/0x440 arch/x86/kvm/cpuid.c:308 kvm_arch_vcpu_ioctl+0x11b6/0x2d70 arch/x86/kvm/x86.c:4709 kvm_vcpu_ioctl+0x7b9/0xdb0 arch/x86/kvm/../../../virt/kvm/kvm_main.c:3386 vfs_ioctl fs/ioctl.c:48 [inline] __do_sys_ioctl fs/ioctl.c:753 [inline] __se_sys_ioctl fs/ioctl.c:739 [inline] __x64_sys_ioctl+0x193/0x200 fs/ioctl.c:739 do_syscall_64+0x2d/0x70 arch/x86/entry/common.c:46 entry_SYSCALL_64_after_hwframe+0x44/0xa9 Reported-by: syzbot+ae488dc136a4cc6ba32b@syzkaller.appspotmail.com Signed-off-by: Like Xu <like.xu@linux.intel.com> Message-Id: <20210118025800.34620-1-like.xu@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-25KVM: x86: Add more protection against undefined behavior in rsvd_bits()Sean Christopherson
Add compile-time asserts in rsvd_bits() to guard against KVM passing in garbage hardcoded values, and cap the upper bound at '63' for dynamic values to prevent generating a mask that would overflow a u64. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Message-Id: <20210113204515.3473079-1-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-25Merge tag 'kvmarm-fixes-5.11-2' of ↵Paolo Bonzini
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 fixes for 5.11, take #2 - Don't allow tagged pointers to point to memslots - Filter out ARMv8.1+ PMU events on v8.0 hardware - Hide PMU registers from userspace when no PMU is configured - More PMU cleanups - Don't try to handle broken PSCI firmware - More sys_reg() to reg_to_encoding() conversions
2021-01-26ARM: dts: rockchip: assign a fixed index to mmc devices on rv1108 boardsJohan Jonker
Recently introduced async probe on mmc devices can shuffle block IDs. Pin them to fixed values to ease booting in environments where UUIDs are not practical. Use newly introduced aliases for mmcblk devices from [1]. The sort order is based on reg address. [1] https://patchwork.kernel.org/patch/11747669/ Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210118155242.7172-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26ARM: dts: rockchip: assign a fixed index to mmc devices on rk322x boardsJohan Jonker
Recently introduced async probe on mmc devices can shuffle block IDs. Pin them to fixed values to ease booting in environments where UUIDs are not practical. Use newly introduced aliases for mmcblk devices from [1]. The sort order is based on reg address. [1] https://patchwork.kernel.org/patch/11747669/ Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210118155242.7172-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26ARM: dts: rockchip: Remove bogus "amba" bus nodesRobin Murphy
The "amba" bus nodes wrapping all the DMA-330 nodes serve no useful purpose, and certainly bear no relation at all to the actual underlying interconnect topology. They appear to be cargo-cult copying from a design misstep in the very early days of FDT adoption on ARM, which was righted with the "arm,primecell" compatible, and the last trace of the idea finally purged by commit 2ef7d5f342c1 ("ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus""). As such, they can simply be removed and the DMA-330 nodes fitted into the normal sort order. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/e682edd25133bde2ed8198138febc90071530a51.1611186142.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26arm64: dts: rockchip: Disable display for NanoPi R2SRobin Murphy
NanoPi R2S is headless, so rightly does not enable any of the display interface hardware, which currently provokes an obnoxious error in the boot log from the fake DRM device failing to find anything to bind to. It probably isn't *too* hard to obviate the fake device shenanigans entirely with a bit of driver reshuffling, but for now let's just disable it here to shut up the spurious error. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/c4553dfad1ad6792c4f22454c135ff55de77e2d6.1611186099.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-25arm64: dts: rockchip: Add NanoPi M4B boardChen-Yu Tsai
The NanoPi M4B is a minor revision of the original M4. The differences against the original Nanopi M4 that are common with the other M4V2 revision include: - microphone header removed - power button added - recovery button added Additional changes specific to the M4B: - USB 3.0 hub removed; board now has 2x USB 3.0 type-A ports and 2x USB 2.0 ports - ADB toggle switch added; this changes the top USB 3.0 host port to a peripheral port - Type-C port no longer supports data or PD - WiFi/Bluetooth combo chip switched to AP6256, which supports BT 5.0 but only 1T1R (down from 2T2R) for WiFi Add a new dts file for the new board revision that shows the difference against the original. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20210121162321.4538-5-wens@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-25arm64: dts: rockchip: Move ep-gpios property to nanopc-t4 from nanopi4Chen-Yu Tsai
Only the NanoPC T4 hs the PCIe reset pin routed to the SoC. For the NanoPi M4 family, no such signal is routed to the expansion header on the base board. As the schematics for the expansion board were not released, it is unclear how this is handled, but the likely answer is that the signal is always pulled high. Move the ep-gpios property from the common nanopi4.dtsi file to the board level nanopc-t4.dts file. This makes the nanopi-m4 lack ep-gpios, matching the board design. A companion patch "PCI: rockchip: make ep_gpio optional" for the Linux driver is required, as the driver currently requires the property to be present. Fixes: e7a095908227 ("arm64: dts: rockchip: Add devicetree for NanoPC-T4") Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20210121162321.4538-4-wens@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-25ARM: dts: bcm21664: Replace spaces with a tabStanislav Jakubek
Fix checkpatch warning: WARNING: please, no spaces at the start of a line Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-01-25KVM: arm64: Implement the TRNG hypervisor callArd Biesheuvel
Provide a hypervisor implementation of the ARM architected TRNG firmware interface described in ARM spec DEN0098. All function IDs are implemented, including both 32-bit and 64-bit versions of the TRNG_RND service, which is the centerpiece of the API. The API is backed by the kernel's entropy pool only, to avoid guests draining more precious direct entropy sources. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> [Andre: minor fixes, drop arch_get_random() usage] Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210106103453.152275-6-andre.przywara@arm.com
2021-01-25Merge tag 'tags/bcm2835-soc-next-2021-01-25' into soc/nextFlorian Fainelli
Select BRCMSTB_L2_IRQ as it's now used on Raspberry Pi 4 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-01-25ARM: bcm: Select BRCMSTB_L2_IRQ for bcm2835Maxime Ripard
The BCM2711 has a number of instances of interrupt controllers handled by the driver behind the BRCMSTB_L2_IRQ Kconfig option (irq-brcmstb-l2). Let's select that driver as part of the ARCH_BCM2835 Kconfig option. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20210111142309.193441-1-maxime@cerno.tech
2021-01-25ARM: multi_v7_defconfig: Enable nvmem's rmem driverNicolas Saenz Julienne
It'll be used by the RPi4 family of boards to access its bootloader configuration. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20210112142342.7290-1-nsaenzjulienne@suse.de
2021-01-25arm64: defconfig: Enable nvmem's rmem driverNicolas Saenz Julienne
It'll be used by the RPi4 family of boards to access its bootloader configuration. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20210112142342.7290-1-nsaenzjulienne@suse.de
2021-01-25ARM: dts: bcm2711: Add the BSC interrupt controllerMaxime Ripard
The BSC controllers used for the HDMI DDC have an interrupt controller shared between both instances. Let's add it to avoid polling. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20210111142309.193441-1-maxime@cerno.tech
2021-01-25ARM: dts: bcm2711: Add reserved memory template to hold firmware configurationNicolas Saenz Julienne
RPi4's co-processor will copy the board's bootloader[1] configuration into memory for the OS to consume. Specifically, for the bootloader configuration and upgrade user-space routines to query it through nvmem's sysfs interface. Introduce a reserved-memory area template for the co-processor to edit before booting the system so as for Linux not to overwrite that memory and to expose it as an nvmem device. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Tim Gover <tim.gover@raspberrypi.com> Link: https://lore.kernel.org/r/e8ca9365-a1f2-1f9d-377c-13bf97883cce@linaro.org [1] https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711_bootloader_config.md
2021-01-25ARM: dts: bcm2711: Use compatible string for BCM2711 DSI1Dave Stevenson
Updates the compatible string for DSI1 on BCM2711 to differentiate it from BCM2835. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20201203132543.861591-9-maxime@cerno.tech
2021-01-25arm64: dts: qcom: msm8994-kitakami: Add missing email in the copyrightKonrad Dybcio
I forgot to do this the first time around. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-11-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: msm8994/8994-kitakami: Fix up the memory mapKonrad Dybcio
The previous map was wrong. Fix it up. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-10-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: msm8994: Fix BLSP2_UART2 nodeKonrad Dybcio
Fix up the node to make the peripheral functional. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-9-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: msm8994-kitakami: Add VDD_GFX regulatorKonrad Dybcio
This is required for the GPU to function. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-8-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: msm8994-kitakami: Add uSD card supportKonrad Dybcio
Assign regulators and enable regulator-set-load on VMMC so as to provide sufficient power. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-7-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: msm8994-kitakami: Add Synaptics RMI touchscreenKonrad Dybcio
All Kitakami phones use Synaptics RMI4 touchscreens attached to the same i2c bus. Configure and enable it. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-6-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: msm/apq8994-kitakami: Add regulator configKonrad Dybcio
Add regulator config for all Kitakami devices, commonizing where applicable. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-5-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: msm8992/4: Rename vreg_vph_pwr to vph_pwrKonrad Dybcio
Rename the fixed regulator to follow the common naming scheme Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: msm8992-libra: Update regulator configKonrad Dybcio
* Add PMI8994 RPM regulators * Add missing PM8994 LVSes * Add comments concerning "missing" regulators Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: msm8992-bullhead: Update regulator configKonrad Dybcio
* Include pm(i)8994 dtsi * Add PMI8994 RPM regulators * Add comments concerning "missing" regulators Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: Add support for remaining Sony Kitakami boardsKonrad Dybcio
This patch adds support for the following Xperias: * Z3+ [aka Z4 in some regions] (Ivy) * Z4 Tablet (Karin) * Z4 Tablet Wi-Fi (Karin_windy) [APQ8094] * Z5 Compact (Suzuran) * Z5 Premium (Satsuki) These devices are very similar in terms of hardware, with main differences being display panels. While at it, update comments describing hardware used: SMB charger seems to not be used after all, PMI8994 charger is in use instead. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118162432.107275-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25arm64: dts: qcom: msm8992/4: Add RPM Power DomainsKonrad Dybcio
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118161943.105733-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25platform/x86: intel_scu_wdt: Move driver from arch/x86Andy Shevchenko
The ACPI-enabled Intel MID platforms neither have WDAT table nor proper IDs to instantiate watchdog device. In order to keep them working move the board code from arch/x86 to drivers/platform/x86. Note, the complete SFI support is going to be removed, that's why PDx86 has been chosen as a new home for it. This is the only device which needs additional code so far. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-25ARM: dts: meson8b: add the thermal-zones with cooling configurationMartin Blumenstingl
The vendor kernel uses the following thermal-zone settings: <= 70°C: - CPU frequency limited to 1.488GHz - GPU limited to 511MHz and 2 cores (pixel processors) <= 80°C: - CPU frequency limited to 1.2GHz - GPU limited to 435MHz and 2 cores (pixel processors) <= 90°C: - CPU frequency limited to 0.804GHz - GPU limited to 328MHz and 1 core (pixel processor) Add simplified thermal configuration which is taken from the GXBB/GXL/GXM SoC family (which uses the same manufacturing process and has the same maximum junction temperature of 125°C). With this the thermal framework will try to keep the SoC temperature at or below 80°C which is identical to the vendor kernel (with the exception of one CPU frequency step from 1.488GHz to 1.536GHz). The number of GPU cores are not taken into account as this is not supported. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201221181306.904272-5-martin.blumenstingl@googlemail.com
2021-01-25ARM: dts: meson8: add the thermal-zones with cooling configurationMartin Blumenstingl
The vendor kernel uses the following thermal-zone settings: <= 70°C: - CPU frequency limited to 1.608GHz - GPU limited to 511MHz and 5 cores (pixel processors) <= 80°C: - CPU frequency limited to 1.2GHz - GPU limited to 435MHz and 4 cores (pixel processors) <= 90°C: - CPU frequency limited to 0.804GHz - GPU limited to 328MHz and 3 cores (pixel processors) Add simplified thermal configuration which is taken from the GXBB/GXL/GXM SoC family (which uses the same manufacturing process and has the same maximum junction temperature of 125°C). With this the thermal framework will try to keep the SoC temperature at or below 80°C which is identical to the vendor kernel (with the exception of one GPU pixel processor). The number of GPU cores are not taken into account as this is not supported. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201221181306.904272-4-martin.blumenstingl@googlemail.com
2021-01-25ARM: dts: meson: add the ADC thermal sensor to meson.dtsiMartin Blumenstingl
The SoC temperature can be retrieved from ADC channel 8 on all 32-bit SoCs (Meson6, Meson8, Meson8b and Meson8m2). Add a "generic-adc-thermal" instance to meson.dtsi so the thermal sensor is available for all SoCs. If the temperature sensor calibration data is missing for a board then the "generic-adc-thermal" will not probe and not register a thermal sensor. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201221181306.904272-3-martin.blumenstingl@googlemail.com
2021-01-25ARM: dts: meson: move iio-hwmon for the SoC temperature to meson.dtsiMartin Blumenstingl
The SoC temperature can be retrieved from ADC channel 8 on all 32-bit SoCs (Meson6, Meson8, Meson8b and Meson8m2). Move the iio-hwmon instance to meson.dtsi instead of duplicating it in all board.dts. If the temperature sensor calibration data is missing for a board then iio-hwmon will simply not probe. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201221181306.904272-2-martin.blumenstingl@googlemail.com
2021-01-25ARM: multi_v7_defconfig: Enable support for the ADC thermal sensorMartin Blumenstingl
32-bit Amlogic Meson platforms are using a special ADC channel to read the SoC temperature. Enable the "generic ADC thermal" driver so this data can be used to cool the SoC for example by reduing the maximum CPU and GPU frequencies temporarily. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201221181306.904272-6-martin.blumenstingl@googlemail.com
2021-01-25ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO nodeRobert Marko
Since we now have driver for the SDHCI VQMMC LDO needed for I/0 voltage levels lets introduce the necessary node for it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Link: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25KVM: arm64: Mark the page dirty only if the fault is handled successfullyYanan Wang
We now set the pfn dirty and mark the page dirty before calling fault handlers in user_mem_abort(), so we might end up having spurious dirty pages if update of permissions or mapping has failed. Let's move these two operations after the fault handlers, and they will be done only if the fault has been handled successfully. When an -EAGAIN errno is returned from the map handler, we hope to the vcpu to enter guest directly instead of exiting back to userspace, so adjust the return value at the end of function. Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210114121350.123684-4-wangyanan55@huawei.com
2021-01-25KVM: arm64: Filter out the case of only changing permissions from stage-2 ↵Yanan Wang
map path (1) During running time of a a VM with numbers of vCPUs, if some vCPUs access the same GPA almost at the same time and the stage-2 mapping of the GPA has not been built yet, as a result they will all cause translation faults. The first vCPU builds the mapping, and the followed ones end up updating the valid leaf PTE. Note that these vCPUs might want different access permissions (RO, RW, RX, RWX, etc.). (2) It's inevitable that we sometimes will update an existing valid leaf PTE in the map path, and we perform break-before-make in this case. Then more unnecessary translation faults could be caused if the *break stage* of BBM is just catched by other vCPUS. With (1) and (2), something unsatisfactory could happen: vCPU A causes a translation fault and builds the mapping with RW permissions, vCPU B then update the valid leaf PTE with break-before-make and permissions are updated back to RO. Besides, *break stage* of BBM may trigger more translation faults. Finally, some useless small loops could occur. We can make some optimization to solve above problems: When we need to update a valid leaf PTE in the map path, let's filter out the case where this update only change access permissions, and don't update the valid leaf PTE here in this case. Instead, let the vCPU enter back the guest and it will exit next time to go through the relax_perms path without break-before-make if it still wants more permissions. Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210114121350.123684-3-wangyanan55@huawei.com
2021-01-25KVM: arm64: Adjust partial code of hyp stage-1 map and guest stage-2 mapYanan Wang
Procedures of hyp stage-1 map and guest stage-2 map are quite different, but they are tied closely by function kvm_set_valid_leaf_pte(). So adjust the relative code for ease of code maintenance in the future. Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210114121350.123684-2-wangyanan55@huawei.com
2021-01-25KVM: arm64: Simplify __kvm_hyp_init HVC detectionAndrew Scull
The arguments for __do_hyp_init are now passed with a pointer to a struct which means there are scratch registers available for use. Thanks to this, we no longer need to use clever, but hard to read, tricks that avoid the need for scratch registers when checking for the __kvm_hyp_init HVC. Tested-by: David Brazdil <dbrazdil@google.com> Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210125145415.122439-2-ascull@google.com
2021-01-25KVM: arm64: Don't clobber x4 in __do_hyp_initAndrew Scull
arm_smccc_1_1_hvc() only adds write contraints for x0-3 in the inline assembly for the HVC instruction so make sure those are the only registers that change when __do_hyp_init is called. Tested-by: David Brazdil <dbrazdil@google.com> Signed-off-by: Andrew Scull <ascull@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210125145415.122439-3-ascull@google.com
2021-01-25ARM: dts: stm32: Rename mmc controller nodes to mmc@Marek Vasut
Per mmc-controller.yaml, the node pattern is "^mmc(@.*)?$" , so adjust the node. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Ludovic Barre <ludovic.barre@st.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com Cc: devicetree@vger.kernel.org Acked-by: Yann Gautier <yann.gautier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-01-25ARM: dts: stm32: Enable voltage translator auto-detection on DHCOMMarek Vasut
The DHCOM SoM uSD slot has an optional voltage level translator, add DT bindings which permit the MMCI driver to detect the translator automatically. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Ludovic Barre <ludovic.barre@st.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-01-25ARM: dts: stm32: Add additional init state for SDMMC1 pinsMarek Vasut
Add "init" mux option for SDMMC1, where the CMD, CK, CKIN lines are not configured, so they can be claimed as GPIOs early on in driver probe(). This is used for probing optional voltage level translator. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Ludovic Barre <ludovic.barre@st.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-01-25m68k: defconfig: Update defconfigs for v5.11-rc1Geert Uytterhoeven
- Enable modular build of netfilter nf_tables netdev REJECT support, - Enable modular build of the resource and cmdline API unit tests. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: https://lore.kernel.org/r/20201228104232.1421134-1-geert@linux-m68k.org
2021-01-25MIPS: Add is_jr_ra_ins() to end the loop earlyJinyang He
For those leaf functions, they are likely to have no stack operations. Add is_jr_ra_ins() to determine whether jr ra has been touched before the frame_size is found. Without this patch, the get frame_size operation may be out of range and get the frame_size from the next nested function. There is no POOL32A format in uapi/asm/inst.h, so some bits here use the format of r_format instead. e.g. --------------------------------------------------------------------- | format | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 | -----------------+---------+-------+-------+------------+------------ | pool32a_format | pool32a | rt | rs | jalrc | pool32axf | -----------------+---------+-------+-------+------------+------------ | r_format | opcode | rs | rt | rd:5, re:5 | func | --------------------------------------------------------------------- Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-01-25MIPS: Fix get_frame_info() handing of function sizeJinyang He
[1]: Commit b6c7a324df37b ("MIPS: Fix get_frame_info() handling of microMIPS function size") [2]: Commit 2b424cfc69728 ("MIPS: Remove function size check in get_frame_info()") First patch added a constant to check the number of iterations against. Second patch fixed the situation that info->func_size is zero. However, func_size member became useless after the second commit. Without ip_end, the get frame_size operation may be out of range although KALLSYMS enabled. Thus, check func_size first. Then make ip_end be the sum of ip and a constant (512) if func_size is equal to 0. Otherwise make ip_end be the sum of ip and func_size. Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-01-25MIPS: microMIPS: Fix the judgment of mm_jr16_op and mm_jalr_opJinyang He
mm16_r5_format.rt is 5 bits, so directly judge the value if equal or not. mm_jalr_op requires 7th to 16th bits. These 10 which bits generated by shifting u_format.uimmediate by 6 may be affected by sign extension. Thus, take out the 10 bits for comparison. Without this patch, errors may occur, such as these bits are all ones. Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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