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2010-05-10sh: rework memory limits to work with LMB.Paul Mundt
This reworks the memory limit handling to tie in through the available LMB infrastructure. This requires a bit of reordering as we need to have all of the LMB reservations taken care of prior to establishing the limits. While we're at it, the crash kernel reservation semantics are reworked so that we allocate from the bottom up and reduce the risk of having to disable the memory limit due to a clash with the crash kernel reservation. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-05-10Merge branch 'core' of ↵Ingo Molnar
git://git.kernel.org/pub/scm/linux/kernel/git/rric/oprofile into oprofile
2010-05-10Merge commit 'v2.6.34-rc7' into oprofileIngo Molnar
Merge reason: Update to Linus's latest -rc. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-10fix "seperate" typos in commentsAnand Gadiyar
s/seperate/separate Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-05-10sh: enable LMB region setup via machvec.Paul Mundt
This plugs in a memory init callback in the machvec to permit boards to wire up various bits of memory directly in to LMB. A generic machvec implementation is provided that simply wraps around the normal Kconfig-derived memory start/size. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-05-09x86, hypervisor: add missing <linux/module.h>H. Peter Anvin
EXPORT_SYMBOL() needs <linux/module.h> to be included; fixes modular builds of the VMware balloon driver, and any future modular drivers which depends on the hypervisor. Reported-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Cc: Greg KH <greg@kroah.com> Cc: Hank Janssen <hjanssen@microsoft.com> Cc: Alok Kataria <akataria@vmware.com> Cc: Ky Srinivasan <ksrinivasan@novell.com> Cc: Dmitry Torokhov <dtor@vmware.com> LKML-Reference: <4BE49778.6060800@zytor.com>
2010-05-10ARM: SAMSUNG: Update S3C2416 entry with S3C2450Ben Dooks
These devices are so similar that they share the same SoC ID code, so note this. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: S3C2413: Update GPIO pull-up supportBen Dooks
Ensure the right get/set pull code is selected and assigned to the GPIO core. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: S3C2416: Use s3c2440 style i2c controllerBen Dooks
The s3c2416 i2c controllers are compatible with the s3c2440 style i2c block, so change the device name appropriately. Signed-off-by: Ben Dooks <ben-linux@fluff.org>y
2010-05-10ARM: S3C2416: Add support for OHCI on SMDK2416Ben Dooks
Add device definition and ensure that the host port is powered up at start time. Full power control can be added at a later date. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: S3C2416: Add support for second HSMMC channelBen Dooks
Add support for the second HSMMC channel on the S3C2416. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: S3C2416: Add basic clock supportBen Dooks
Add basic clock support for the PLLs, HSMMC channels and PWM clocks. This is enough to get a basic system up and running. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: S3C2443: Move parts of the clock code to common clock fileBen Dooks
To share code with some of the newer parts such as the S3C2416, move parts of arch/arm/mach-s3c2443/clock.c to a common file called arch/arm/plat-s3c24xx/s3c2443-clock.c. Update the build configuration to deal with this new file. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: S3C24XX: Identify S3C2416 if S3C2412/S3C2413 built inBen Dooks
Extend the ARMv5 ID code to deal with S3C2416 being built with S3C2412/S3C2413 enabled, as these have their ID registers in a different place. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: S3C2416: Add initial support of SMDK2416Yauhen Kharuzhy
Add support of SMDK2416 development board. Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: S3C2416: Add arch supportYauhen Kharuzhy
Add arch/arm/mach-s3c2416 for support of the Samsung S3C2416 SoC. This patch adds support of the S3C2416 SoC, clocks, timers, and initial IRQ support (without support of secondary set of registers). Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com> [ben-linux@fluff.org: removed files to be reworked, fixed conflicts] [ben-linux@fluff.org: use s3c2443 reset instead of specific reset code] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: SAMSUNG: Add s3c_disable_clocks() and tidy init+disable usageBen Dooks
Add s3c_disable_clocks() and change the clock registration code to use the s3c_register_clocks() followed by s3c_disable_clocks() instead of the loops it was using. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: SAMSUNG: Move S3C6400 PLL code to <plat/pll.h> for re-useBen Dooks
The S3C6400 EPLL code matches the S3C2416 and compatible SoCs, so move it from mach-s3c64xx into <plat/pll.h> for easy reuse. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-10ARM: S3C2416: Add S3C2416-specific registers definitionsYauhen Kharuzhy
Add macros for S3C2416 SoC support. Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com> [ben-linux@fluff.org: removed files that need changing] [ben-linux@fluff.org: Fix S3C2416_GPH0_TXD0 definition] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-05-09x86, hypervisor: Export the x86_hyper* symbolsH. Peter Anvin
Export x86_hyper and the related specific structures, allowing for hypervisor identification by modules. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Cc: Greg KH <greg@kroah.com> Cc: Hank Janssen <hjanssen@microsoft.com> Cc: Alok Kataria <akataria@vmware.com> Cc: Ky Srinivasan <ksrinivasan@novell.com> Cc: Dmitry Torokhov <dtor@vmware.com> LKML-Reference: <4BE49778.6060800@zytor.com>
2010-05-08Merge commit 'v2.6.34-rc6' into x86/cpuH. Peter Anvin
2010-05-08Merge branch 'cpu_stop' of ↵Ingo Molnar
git://git.kernel.org/pub/scm/linux/kernel/git/tj/misc into sched/core
2010-05-08x86, perf: P4 PMU -- check for proper event index in RAW eventsCyrill Gorcunov
RAW events are special and we should be ready for user passing in insane event index values. Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Lin Ming <ming.m.lin@intel.com> LKML-Reference: <20100508112717.315897547@openvz.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-08x86, perf: P4 PMU -- Get rid of redundant check for array indexCyrill Gorcunov
The caller already has done such a check. And it was wrong anyway, it had to be '>=' rather than '>' Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Lin Ming <ming.m.lin@intel.com> LKML-Reference: <20100508112717.130386882@openvz.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-08x86, perf: P4 PMU -- protect sensible procedures from preemptionCyrill Gorcunov
Steven reported: | | I'm getting: | | Pid: 3477, comm: perf Not tainted 2.6.34-rc6 #2727 | Call Trace: | [<ffffffff811c7565>] debug_smp_processor_id+0xd5/0xf0 | [<ffffffff81019874>] p4_hw_config+0x2b/0x15c | [<ffffffff8107acbc>] ? trace_hardirqs_on_caller+0x12b/0x14f | [<ffffffff81019143>] hw_perf_event_init+0x468/0x7be | [<ffffffff810782fd>] ? debug_mutex_init+0x31/0x3c | [<ffffffff810c68b2>] T.850+0x273/0x42e | [<ffffffff810c6cab>] sys_perf_event_open+0x23e/0x3f1 | [<ffffffff81009e6a>] ? sysret_check+0x2e/0x69 | [<ffffffff81009e32>] system_call_fastpath+0x16/0x1b | | When running perf record in latest tip/perf/core | Due to the fact that p4 counters are shared between HT threads we synthetically divide the whole set of counters into two non-intersected subsets. And while we're "borrowing" counters from these subsets we should not be preempted (well, strictly speaking in p4_hw_config we just pre-set reference to the subset which allow to save some cycles in schedule routine if it happens on the same cpu). So use get_cpu/put_cpu pair. Also p4_pmu_schedule_events should use smp_processor_id rather than raw_ version. This allow us to catch up preemption issue (if there will ever be). Reported-by: Steven Rostedt <rostedt@goodmis.org> Tested-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Lin Ming <ming.m.lin@intel.com> LKML-Reference: <20100508112716.963478928@openvz.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-08x86, perf: P4 PMU -- configure predefined eventsCyrill Gorcunov
If an event is not RAW we should not exit p4_hw_config early but call x86_setup_perfctr as well. Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Lin Ming <ming.m.lin@intel.com> Cc: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-08ARM: 6110/1: Fix Thumb-2 kernel builds when UACCESS_WITH_MEMCPY is enabledCatalin Marinas
The patch adds the ENDPROC declarations for the __copy_to_user_std and __clear_user_std functions. Without these, the compiler generates BXL to ARM when compiling the kernel in Thumb-2 mode. Reported-by: Kyungmin Park <kmpark@infradead.org> Tested-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-05-08ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMPCatalin Marinas
The standard I-cache Invalidate All (ICIALLU) and Branch Predication Invalidate All (BPIALL) operations are not automatically broadcast to the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-05-08ARM: 6111/1: Implement read/write for ownership in the ARMv6 DMA cache opsCatalin Marinas
The Snoop Control Unit on the ARM11MPCore hardware does not detect the cache operations and the dma_cache_maint*() functions may leave stale cache entries on other CPUs. The solution implemented in this patch performs a Read or Write For Ownership in the ARMv6 DMA cache maintenance functions. These LDR/STR instructions change the cache line state to shared or exclusive so that the cache maintenance operation has the desired effect. Tested-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-05-08ARM: 6106/1: Implement copy_to_user_page() for noMMUCatalin Marinas
Commit 7959722 introduced calls to copy_(to|from)_user_page() from access_process_vm() in mm/nommu.c. The copy_to_user_page() was not implemented on noMMU ARM. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-05-08ARM: 6105/1: Fix the __arm_ioremap_caller() definition in nommu.cCatalin Marinas
Commit 31aa8fd6 introduced the __arm_ioremap_caller() function but the nommu.c version did not have the _caller suffix. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-05-07x86: Clean up the hypervisor layerH. Peter Anvin
Clean up the hypervisor layer and the hypervisor drivers, using an ops structure instead of an enumeration with if statements. The identity of the hypervisor, if needed, can be tested by testing the pointer value in x86_hyper. The MS-HyperV private state is moved into a normal global variable (it's per-system state, not per-CPU state). Being a normal bss variable, it will be left at all zero on non-HyperV platforms, and so can generally be tested for HyperV-specific features without additional qualification. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Acked-by: Greg KH <greg@kroah.com> Cc: Hank Janssen <hjanssen@microsoft.com> Cc: Alok Kataria <akataria@vmware.com> Cc: Ky Srinivasan <ksrinivasan@novell.com> LKML-Reference: <4BE49778.6060800@zytor.com>
2010-05-07x86, HyperV: fix up the license to mshyperv.cGreg Kroah-Hartman
This should have been GPLv2 only, we cut and pasted from the wrong file originally, sorry. Also removed some unneeded boilerplate license code, we all know where to find the GPLv2, and that there's no warranty as that is implicit from the license. Cc: Ky Srinivasan <ksrinivasan@novell.com> Cc: Hank Janssen <hjanssen@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> LKML-Reference: <20100507235541.GA15448@kroah.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2010-05-07x86: Avoid check hlt for newer cpusJacob Pan
Check hlt instruction was targeted for some older CPUs. It is an expensive operation in that it takes 4 ticks to break out the check. We can avoid such check completely for newer x86 cpus (family >= 5). [ hpa: corrected family > 5 to family >= 5 ] Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> LKML-Reference: <1273269585-14346-1-git-send-email-jacob.jun.pan@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2010-05-07Merge branch 'v4l_for_2.6.34' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6 * 'v4l_for_2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6: V4L/DVB: pxa_camera: move fifo reset direct before dma start V4L/DVB: video: testing unsigned for less than 0 V4L/DVB: mx1-camera: compile fix V4L/DVB: budget: Oops: "BUG: unable to handle kernel NULL pointer dereference" V4L/DVB: ngene: Workaround for stuck DiSEqC pin V4L/DVB: saa7146: fix regression of the av7110/budget-av driver V4L/DVB: v4l: fix config dependencies: mxb and saa7191 are V4L2 drivers, not V4L1 V4L/DVB: feature-removal: announce videotext.h removal V4L/DVB: V4L - vpfe capture - fix for kernel crash V4L/DVB: gspca: make usb id 0461:0815 get handled by the right driver V4L/DVB: gspca - stv06xx: Remove the 046d:08da from the stv06xx driver V4L/DVB: gspca - sn9c20x: Correct onstack wait_queue_head declaration V4L/DVB: saa7146: fix up bytesperline if it is an impossible value V4L/DVB: V4L: vpfe_capture - free ccdc_lock when memory allocation fails V4L/DVB: V4L - Makfile:Removed duplicate entry of davinci V4L/DVB: omap24xxcam: potential buffer overflow
2010-05-07Merge branch 'for-russell' of ↵Russell King
git://codeaurora.org/quic/kernel/dwalker/linux-msm into devel-stable
2010-05-07Merge branch 'gemini_fix' of git://git.berlios.de/gemini-board into devel-stableRussell King
2010-05-07Revert "arm: msm: add oprofile pmu support"Daniel Walker
This reverts commit ee3c454b8da04815c1884ed85fe89d2d131c0e51. As request by Russell King. Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-05-07ARM: S3C2412: DMA: Remove I2S FIFO addressJassi Brar
The S3C DMA API doesn't make use of hw_addr.to/from and also the FIFO addresses are provided from the I2S drivers. So these fields are redundant. This patch removes the hw_addr.to/from fields for I2S and the inclusion of header, paving way for the header to be moved closer to the I2S controller drivers. Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Acked-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-05-07Revert "microblaze: Kill NET_SKB_PAD and NET_IP_ALIGN overrides."David S. Miller
This reverts commit 39e0786d3cf39c6d2f47b4818ae2da8b8ebc9ce2. On request from microblaze developers, they are going to handle this differently. Signed-off-by: David S. Miller <davem@davemloft.net>
2010-05-07perf, x86: implement group scheduling transactional APIsLin Ming
Convert to the transactional PMU API and remove the duplication of group_sched_in(). Reviewed-by: Stephane Eranian <eranian@google.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: David Miller <davem@davemloft.net> Cc: Paul Mackerras <paulus@samba.org> LKML-Reference: <1272002172.5707.61.camel@minggr.sh.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-07perf, x86: Improve the PEBS ABIPeter Zijlstra
Rename perf_event_attr::precise to perf_event_attr::precise_ip and widen it to 2 bits. This new field describes the required precision of the PERF_SAMPLE_IP field: 0 - SAMPLE_IP can have arbitrary skid 1 - SAMPLE_IP must have constant skid 2 - SAMPLE_IP requested to have 0 skid 3 - SAMPLE_IP must have 0 skid And modify the Intel PEBS code accordingly. The PEBS implementation now supports up to precise_ip == 2, where we perform the IP fixup. Also s/PERF_RECORD_MISC_EXACT/&_IP/ to clarify its meaning, this bit should be set for each PERF_SAMPLE_IP field known to match the actual instruction triggering the event. This new scheme allows for a PEBS mode that uses the buffer for more than a single event. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Stephane Eranian <eranian@google.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-07perf, x86: Consolidate some code repetitionPeter Zijlstra
Remove some duplicated logic. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-07perf, x86: Remove PEBS SAMPLE_RAW supportPeter Zijlstra
Its broken, we really should get PERF_SAMPLE_REGS sorted. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-07perf, x86: Use weight instead of cmask in for_each_event_constraint()Robert Richter
There may exist constraints with a cmask set to zero. In this case for_each_event_constraint() will not work properly. Now weight is used instead of the cmask for loop exit detection. Weight is always a value other than zero since the default contains the HWEIGHT from the counter mask and in other cases a value of zero does not fit too. This is in preparation of ibs event constraints that wont have a cmask. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1271190201-25705-7-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-07perf, x86: Pass enable bit mask to __x86_pmu_enable_event()Robert Richter
To reuse this function for events with different enable bit masks, this mask is part of the function's argument list now. The function will be used later to control ibs events too. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1271190201-25705-6-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-07perf, x86: Call x86_setup_perfctr() from .hw_config()Robert Richter
The perfctr setup calls are in the corresponding .hw_config() functions now. This makes it possible to introduce config functions for other pmu events that are not perfctr specific. Also, all of a sudden the code looks much nicer. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1271190201-25705-4-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-07perf, x86: Move x86_setup_perfctr()Robert Richter
Move x86_setup_perfctr(), no other changes made. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1271190201-25705-3-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-07perf, x86: Move perfctr init code to x86_setup_perfctr()Robert Richter
Split __hw_perf_event_init() to configure pmu events other than perfctrs. Perfctr code is moved to a separate function x86_setup_perfctr(). This and the following patches refactor the code. Split in multiple patches for better review. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1271190201-25705-2-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-05-07Merge branch 'perf/urgent' into perf/coreIngo Molnar
Merge reason: Resolve patch dependency Signed-off-by: Ingo Molnar <mingo@elte.hu>
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