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2017-08-29Merge tag 'sunxi-fixes-for-4.13-3' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into fixes Allwinner fixes for 4.13, take 3 This is a revert of the EMAC bindings. The discussion has not settled down yet on a proper representation of the PHY, and therefore we cannot commit to a binding yet * tag 'sunxi-fixes-for-4.13-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm: dts: sunxi: Revert EMAC changes arm64: dts: allwinner: Revert EMAC changes dt-bindings: net: Revert sun8i dwmac binding Signed-off-by: Olof Johansson <olof@lixom.net>
2017-08-29Merge tag 'amlogic-dt64-2' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64 Amlogic 64-bit DT updates for v4.14, round 2 - clock updates w/dependencies on clock tree - GPIO names updates * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxl-libretech-cc: Add GPIO lines names ARM64: dts: meson-gx: Add AO CEC nodes ARM64: dts: meson-gx: update AO clkc to new bindings dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb: Add sd_emmc clk0 clkids clk: meson-gxbb: expose almost every clock in the bindings clk: meson8b: expose every clock in the bindings clk: meson: gxbb: fix protection against undefined clks clk: meson: meson8b: fix protection against undefined clks dt-bindings: clock: meson8b: describe the embedded reset controller Signed-off-by: Olof Johansson <olof@lixom.net>
2017-08-29arm64: defconfig: enable rockchip graphicsHeiko Stuebner
Enable the graphics-related options needed by Rockchip boards. This includes the pwm-backlight which will be needed by the internal displays used on Gru Chrome-devices. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Mark yao <mark.yao@rock-chips.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2017-08-29Merge tag 'mvebu-dt64-4.14-3' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson
next/dt64 mvebu dt64 for 4.14 (part 3) Add description for a new family SoC from Marvell: Armada-8KP. * tag 'mvebu-dt64-4.14-3' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: add Device Tree files for Armada-8KP Signed-off-by: Olof Johansson <olof@lixom.net>
2017-08-29Merge tag 'v4.13-next-dts32' of https://github.com/mbgg/linux-mediatek into ↵Olof Johansson
next/dt - mt7623: add mt7623n and mt7623a plattform - add mt7623 based reference boards - mt7623: add usb3, ethernet, cpufreq, - Add banana-pi board - add mt6323 pmic - mt2701: add larb-id property to smi larb * tag 'v4.13-next-dts32' of https://github.com/mbgg/linux-mediatek: arm: dts: mt7623: cleanup binding file arm: dts: mt7623: Add SD-card and EMMC to bananapi-r2 arm: dts: mediatek: add larbid property for larb arm: dts: mt7623: fix mmc interrupt assignment arm: dts: mt2701: Add usb3 device nodes arm: dts: mt2701: Add ethernet device node arm: dts: mt7623: add clock-frequency to CPU nodes arm: dts: mt7623: add support for Bananapi R2 (BPI-R2) board arm: dts: mt7623: enable the nand device on the mt7623n nand rfb arm: dts: mt7623: enable the usb device on the mt7623n rfb arm: dts: mt7623: cleanup the mt7623n rfb uart nodes arm: dts: mt7623: rename mt7623-evb.dts to arch/arm/boot/dts/mt7623n-rfb.dtsi arm: dts: mt7623: add mt6323.dtsi file dt-bindings: arm: mediatek: add bindings for mediatek MT7623a SoC Platform dt-bindings: arm: mediatek: update for MT7623n SoC and relevant boards arm: dts: mt7623: fixup binding violation missing reset in ethernet node dt-bindings: net: mediatek: update documentation for reset signals Signed-off-by: Olof Johansson <olof@lixom.net>
2017-08-30KVM: PPC: Book3S HV: Protect updates to spapr_tce_tables listPaul Mackerras
Al Viro pointed out that while one thread of a process is executing in kvm_vm_ioctl_create_spapr_tce(), another thread could guess the file descriptor returned by anon_inode_getfd() and close() it before the first thread has added it to the kvm->arch.spapr_tce_tables list. That highlights a more general problem: there is no mutual exclusion between writers to the spapr_tce_tables list, leading to the possibility of the list becoming corrupted, which could cause a host kernel crash. To fix the mutual exclusion problem, we add a mutex_lock/unlock pair around the list_del_rce in kvm_spapr_tce_release(). Also, this moves the call to anon_inode_getfd() inside the region protected by the kvm->lock mutex, after we have done the check for a duplicate LIOBN. This means that if another thread does guess the file descriptor and closes it, its call to kvm_spapr_tce_release() will not do any harm because it will have to wait until the first thread has released kvm->lock. With this, there are no failure points in kvm_vm_ioctl_create_spapr_tce() after the call to anon_inode_getfd(). The other things that the second thread could do with the guessed file descriptor are to mmap it or to pass it as a parameter to a KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE ioctl on a KVM device fd. An mmap call won't cause any harm because kvm_spapr_tce_mmap() and kvm_spapr_tce_fault() don't access the spapr_tce_tables list or the kvmppc_spapr_tce_table.list field, and the fields that they do use have been properly initialized by the time of the anon_inode_getfd() call. The KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE ioctl calls kvm_spapr_tce_attach_iommu_group(), which scans the spapr_tce_tables list looking for the kvmppc_spapr_tce_table struct corresponding to the fd given as the parameter. Either it will find the new entry or it won't; if it doesn't, it just returns an error, and if it does, it will function normally. So, in each case there is no harmful effect. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-08-30MIPS: Don't use dma_cache_sync to implement fd_cacheflushChristoph Hellwig
The floppy drivers doesn't otherwise use the DMA API, so indirecting through it just for cache flushing in MIPS-specific code just call dma_cache_wback_inv directly. Signed-off-by: Christoph Hellwig <hch@lst.de> Cc: iommu@lists.linux-foundation.org Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Michal Simek <monstr@monstr.eu> Cc: David Howells <dhowells@redhat.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Chris Zankel <chris@zankel.net> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: x86@kernel.org Cc: linux-mips@linux-mips.org Cc: linux-ia64@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-xtensa@linux-xtensa.org Cc: linux-sh@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17183/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: generic: Bump default NR_CPUS to 16Paul Burton
In generic_defconfig set CONFIG_NR_CPUS to 16 rather than 2, which is a rather too low limit for many modern day MIPS systems. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16949/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: generic: Don't explicitly disable CONFIG_USB_SUPPORTPaul Burton
Leave CONFIG_USB_SUPPORT at its default, allowing board config fragments to make use of USB drivers without needing to override it & trigger warnings from merge_config.sh. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16948/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: Make CONFIG_MIPS_MT_SMP default yPaul Burton
On systems that support MT ASE multithreading (ie. VPEs) we are very likely to want to include that support as default. Rather than setting it in various defconfigs, simply make CONFIG_MIPS_MT_SMP default y such that systems which select CONFIG_SYS_SUPPORTS_MULTITHREADING get it by default. As well as allowing us to remove the selection of CONFIG_MIPS_MT_SMP from various defconfigs, this also allows the generated generic defconfigs which derive from generic_defconfig to automatically gain support for MT ASE SMP when building for a suitable (pre-MIPSr6) ISA. For malta_kvm_guest_defconfig CONFIG_MIPS_MT_SMP is explicitly disabled since enabling SMP implicitly disables CONFIG_KVM_GUEST, which depends on CONFIG_BROKEN_ON_SMP. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16947/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: Prevent direct use of generic_defconfigPaul Burton
Using generic_defconfig directly is unlikely to be what a user actually wants to do - it doesn't specify any particular ISA revision & it doesn't enable any board or driver support, resulting in a largely useless kernel. Prevent users from using it directly, printing a helpful message to point them in the right direction if they attempt to. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16946/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: NI 169445: Only include in 32r2el kernelsPaul Burton
The NI 169445 board uses a little endian MIPS32r2 CPU, and therefore including board support in kernels that are unable to run on such a CPU is pointless. Specify requirements in the board config fragment that cause the NI 169445 board support to only be included in generic kernels that target little endian MIPS32r2 CPUs. For example, NI 169445 support will be included when configuring using 32r2el_defconfig but not when using 64r6_defconfig. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Nathan Sullivan <nathan.sullivan@ni.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16945/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: SEAD-3: Only include in 32 bit kernels by defaultPaul Burton
The MIPS SEAD-3 development board has only ever been used with 32 bit CPUs, so including support for it in 64 bit kernels is wasteful since those kernels will never run on a SEAD-3. Specify a requirement in the SEAD-3 board config fragment that ensures the board support is only included in 32 bit kernels, by checking that CONFIG_32BIT=y. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16944/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: generic: Allow filtering enabled boards by requirementsPaul Burton
Up until now when configuring a generic kernel all board config fragments have been merged by default unless boards are explicitly selected by the user specifying BOARDS=. In many cases this is sub-optimal, since some boards don't make sense to include in some kernels. For example the MIPS SEAD-3 development board has only ever been used with 32 bit CPUs, so including support for the SEAD-3 in a 64 bit kernel is wasteful. This patch introduces support for specifying requirements in board config fragments, using comments formatted like so: # require CONFIG_BLA=y For example the SEAD-3 board could specify that it should only be merged for 32 bit kernels using a requirement line like the following: # require CONFIG_32BIT=y A new generic-board-config.sh script is introduced to handle selecting the board config fragments to merge & calling merge_config.sh to merge them. In order to allow requirements to check Kconfig symbols that are implicitly selected, rather than explicitly specified by generic_defconfig or one of the ISA config fragments, an intermediate .config file is saved & used as a reference when checking requirements. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16943/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Detect CPUs in secondary clustersPaul Burton
As a first step towards supporting multi-cluster systems, detect cores & VPs in secondary clusters & record their cluster information in the cpu_data array. The "VP topology" line printed during boot is extended to display multiple clusters. On a single cluster it shows output like the following: VP topology: {4,4} This would indicate a system with 2 cores which each contain 4 VPs. We extend this to cover multiple clusters in a natural way: VP topology: {4,4},{2,2} This would indicate a system with 2 clusters. The first cluster contains 2 cores which each contain 4 VPs. The second cluster contains 2 cores which each contain 2 VPs. Actually booting these cores & VPs is left to further patches once other pieces are in place. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17017/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Cluster support for topology functionsPaul Burton
Modify the functions we use to read information about the topology of the system (the number of cores, VPs & IOCUs that it contains) in order to take into account multiple clusters, and provide a new function to determine the number of clusters in the system. Users of these functions are modified only such that they continue to build successfully - having them actually handle multiple clusters is left to further patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17016/ Patchwork: https://patchwork.linux-mips.org/patch/17218/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Have asm/mips-cps.h include CM & CPC headersPaul Burton
With Coherence Manager (CM) 3.5 information about the topology of the system, which has previously only been available through & accessed from the CM, is now also provided by the Cluster Power Controller (CPC). This includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG. In preparation for adjusting functions such as mips_cm_numcores(), which have previously only needed to access the CM, to also access the CPC this patch modifies the way we use the various CPS headers. Rather than having users include asm/mips-cm.h or asm/mips-cpc.h individually we instead have users include asm/mips-cps.h which in turn includes asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access to both CM & CPC registers by including one header, and most importantly it makes asm/mips-cps.h an ideal location for helper functions which need to access the various components of the CPS. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17015/ Patchwork: https://patchwork.linux-mips.org/patch/17217/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: SMP: Allow boot_secondary SMP op to return errorsPaul Burton
Allow the boot_secondary SMP op to return an error to __cpu_up(), which will in turn return it to its caller. This will allow SMP implementations to return errors quickly in cases they they know have failed, rather than relying upon __cpu_up() eventually timing out waiting for the cpu_running completion. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17014/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CM: Add cluster & block args to mips_cm_lock_other()Paul Burton
With CM >= 3.5 we have the notion of multiple clusters & can access their CM, CPC & GIC registers via the apporpriate redirect/other register blocks. In order to allow for this introduce cluster & block arguments to mips_cm_lock_other() which configures the redirect/other region to point at the appropriate cluster, core, VP & register block. Since we now have 4 arguments to mips_cm_lock_other() & a common use is likely to be to target the cluster, core & VP corresponding to a particular Linux CPU number we also add a new mips_cm_lock_other_cpu() helper function which handles that without the caller needing to manually pull out the cluster, core & VP numbers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17013/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: Add CPU cluster number accessorsPaul Burton
Introduce cpu_cluster() & cpu_set_cluster() accessor functions in the same vein as cpu_core(), cpu_vpe_id() & their set variants. These will be used in further patches to allow users to get or set a CPUs cluster number. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17012/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: Unify checks for sibling CPUsPaul Burton
Up until now we have open-coded checks for whether CPUs are siblings, with slight variations on whether we consider the package ID or not. This will only get more complex when we introduce cluster support, so in preparation for that this patch introduces a cpus_are_siblings() function which can be used to check whether or not 2 CPUs are siblings in a consistent manner. By checking globalnumber with the VP ID masked out this also has the neat side effect of being ready for multi-cluster systems already. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Rafael J. Wysocki <rjw@rjwysocki.net> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17011/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: Store core & VP IDs in GlobalNumber-style variablePaul Burton
This patch modifies the way we store core & VP IDs such that we store them in a single 32 bit integer whose format matches that of the MIPSr6 GlobalNumber register. Whereas we have previously stored core & VP IDs in separate fields, storing them in a single GlobalNumber-like field: 1) Reduces the size of struct cpuinfo_mips by 4 bytes, and will allow it to not grow when cluster support is added. 2) Gives us a natural place to store cluster number, which matches up with what the architecture provides. 3) Will be useful in the future as a parameter to the MIPSr6 GINVI instruction to specify a target CPU whose icache that instruction should operate on. The cpu_set*() accessor functions are moved out of the asm/cpu-info.h header in order to allow them to use the WARN_ON macro, which is unusable in asm/cpu-info.h due to include ordering. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17010/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: Abstract CPU core & VP(E) ID access through accessor functionsPaul Burton
We currently have fields in struct cpuinfo_mips for the core & VP(E) ID of a particular CPU, and various pieces of code directly access those fields. This patch abstracts such access by introducing accessor functions cpu_core(), cpu_set_core(), cpu_vpe_id() & cpu_set_vpe_id() and having code that needs to access these values call those functions rather than directly accessing the struct cpuinfo_mips fields. This prepares us for changes to the way in which those values are stored in later patches. The cpu_vpe_id() function is introduced even though we already had a cpu_vpe_id() macro for a couple of reasons: 1) It's more consistent with the core, and future cluster, accessors. 2) It ensures a sensible return type without explicit casts. 3) It's generally preferable to use functions rather than macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Use GlobalNumber macros rather than magic numbersPaul Burton
We now have definitions for the GlobalNumber register in asm/mipsregs.h, so use them in place of magic numbers in cps-vec.S. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17008/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: Add accessor & bit definitions for GlobalNumberPaul Burton
MIPSr6 introduces a GlobalNumber register, which is required when VPs are implemented (ie. when multi-threading is supported) but otherwise optional. The register contains sufficient information to uniquely identify a VP within a system using its cluster number, core number & VP ID. In preparation for using this register & its fields, introduce an accessor macro for it & define its various bits with the typical style preprocessor macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Add CM/CPC 3.5 register definitionsPaul Burton
Introduce definitions & accessors for a selection of Coherence Manager (CM) & Cluster Power Controller (CPC) registers that are new with CM v3.5 & the MIPS I6500. These are primarily registers that will be used in supporting multiple CPU clusters. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Use change_*, set_* & clear_* where appropriatePaul Burton
Make use of the new change_*, set_* & clear_* accessor functions for CPS (CM, CPC & GIC) registers where doing so makes the code easier to read or shortens it without adversely affecting readability. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17005/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPS: Introduce register modify (set/clear/change) accessorsPaul Burton
For read-write registers introduce accessor functions that simplify the task of modifying a subset of bits within the register. set_* functions set bits to 1, clear_* functions clear bits to 0 & change_* functions set bits specified in a mask to an arbitrary value. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17004/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shiftsPaul Burton
Tidy up asm/mips-cpc.h in a similar way to what "MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts" did for asm/mips-cm.h. We use BIT() & GENMASK() to simplify the definition of register fields, drop the _SHF definitions since that information can be found in the _MSK ones, and then drop the _MSK suffix. Fields definitions are moved to be next to the appropriate register definition, making it easier to link the two & keep everything ordered by register address. Comments are added including the name of each register & a brief description of its purpose which helps to understand what registers are for, link them back to hardware documentation or grep for them. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17003/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30MIPS: CPC: Use common CPS accessor generation macrosPaul Burton
Switch the MIPS Cluster Power Controller (CPC) accessor functions to be generated by the new common Coherent Processing System (CPS) macros shared with the Coherence Manager (CM). Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17002/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-29alpha: uapi: Add support for __SANE_USERSPACE_TYPES__Ben Hutchings
This fixes compiler errors in perf such as: tests/attr.c: In function 'store_event': tests/attr.c:66:27: error: format '%llu' expects argument of type 'long long unsigned int', but argument 6 has type '__u64 {aka long unsigned int}' [-Werror=format=] snprintf(path, PATH_MAX, "%s/event-%d-%llu-%d", dir, ^ Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Tested-by: Michael Cree <mcree@orcon.net.nz> Cc: stable@vger.kernel.org Signed-off-by: Matt Turner <mattst88@gmail.com>
2017-08-29alpha: Define ioremap_wcGuenter Roeck
Commit 3cc2dac5be3f ("drivers/video/fbdev/atyfb: Replace MTRR UC hole with strong UC") introduces calls to ioremap_wc and ioremap_uc. This causes build failures with alpha:allmodconfig. Map the missing functions to ioremap_nocache. Fixes: 3cc2dac5be3f ("drivers/video/fbdev/atyfb: Replace MTRR UC hole with strong UC") Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Luis R. Rodriguez <mcgrof@suse.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Matt Turner <mattst88@gmail.com>
2017-08-29alpha: Fix section mismatchesMatt Turner
Signed-off-by: Matt Turner <mattst88@gmail.com>
2017-08-29alpha: support R_ALPHA_REFLONG relocations for module loadingMichael Cree
Since commit 71810db27c1c853b33 (modversions: treat symbol CRCs as 32 bit quantities) R_ALPHA_REFLONG relocations can be required to load modules. This implements it. Tested-by: Bob Tracy <rct@gherkin.frus.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael Cree <mcree@orcon.net.nz> Signed-off-by: Matt Turner <mattst88@gmail.com>
2017-08-29alpha: Fix typo in ev6-copy_user.SRichard Henderson
Patch 8525023121de4848b5f0a7d867ffeadbc477774d introduced a typo. That said, the identity AND insns added by that patch are more clearly written as MOV. At the same time, re-schedule the ev6 version so that the first dispatch can execute in parallel. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Matt Turner <mattst88@gmail.com>
2017-08-29alpha: Package string routines togetherRichard Henderson
There are direct branches between {str*cpy,str*cat} and stx*cpy. Ensure the branches are within range by merging these objects. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Matt Turner <mattst88@gmail.com>
2017-08-29alpha: Update for new syscallsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Matt Turner <mattst88@gmail.com>
2017-08-29alpha: Fix build error without CONFIG_VGA_HOSE.Matt Turner
pci_vga_hose is #defined to 0 in include/asm/vga.h if CONFIG_VGA_HOSE is not set. Signed-off-by: Matt Turner <mattst88@gmail.com>
2017-08-29arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339Shawn Lin
Convert all RK3399 platforms to use per-lane PHY model in order to save more power by idling unused lane(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
2017-08-29KVM: s390: we are always in czam modeDavid Hildenbrand
Independent of the underlying hardware, kvm will now always handle SIGP SET ARCHITECTURE as if czam were enabled. Therefore, let's not only forward that bit but always set it. While at it, add a comment regarding STHYI. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170829143108.14703-1-david@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-08-29s390/mm: avoid empty zero pages for KVM guests to avoid postcopy hangsChristian Borntraeger
Right now there is a potential hang situation for postcopy migrations, if the guest is enabling storage keys on the target system during the postcopy process. For storage key virtualization, we have to forbid the empty zero page as the storage key is a property of the physical page frame. As we enable storage key handling lazily we then drop all mappings for empty zero pages for lazy refaulting later on. This does not work with the postcopy migration, which relies on the empty zero page never triggering a fault again in the future. The reason is that postcopy migration will simply read a page on the target system if that page is a known zero page to fault in an empty zero page. At the same time postcopy remembers that this page was already transferred - so any future userfault on that page will NOT be retransmitted again to avoid races. If now the guest enters the storage key mode while in postcopy, we will break this assumption of postcopy. The solution is to disable the empty zero page for KVM guests early on and not during storage key enablement. With this change, the postcopy migration process is guaranteed to start after no zero pages are left. As guest pages are very likely not empty zero pages anyway the memory overhead is also pretty small. While at it this also adds proper page table locking to the zero page removal. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Janosch Frank <frankja@linux.vnet.ibm.com> Cc: stable@vger.kernel.org Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2017-08-29s390/dasd: Add discard support for FBA devicesJan Höppner
The z/VM hypervisor provides virtual disks (VDISK) which are backed by main memory of the hypervisor. Those devices are seen as DASD FBA disks within the Linux guest. Whenever data is written to such a device, memory is allocated on-the-fly by z/VM accordingly. This memory, however, is not being freed if data on the device is deleted by the guest OS. In order to make memory usable after deletion again, add discard support to the FBA discipline. While at it, update comments regarding the DASD_FEATURE_* flags. Reviewed-by: Stefan Haberland <sth@linux.vnet.ibm.com> Signed-off-by: Jan Höppner <hoeppner@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2017-08-29s390/uaccess: avoid mvcos jump labelMartin Schwidefsky
If the kernel is compiled for z10 or later machines the uaccess code inlines the mvcos instruction. The facility bit 27 which indicates the availability of MVCOS has to be set. The have_mvcos jump label will always be true. Make the generation of the have_mvcos jump label conditional on !CONFIG_HAVE_MARCH_Z10_FEATURES. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2017-08-29s390/mm: use generic mm_hooksMartin Schwidefsky
With git commit 3446c13b268af86391d06611327006b059b8bab1 "s390/mm: four page table levels vs. fork" s390 dropped its architecture specific version of arch_dup_mmap. Now all functions defined by include/asm-generic/mm_hooks.h are identical to the s390 versions. Use the generic header. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2017-08-29s390/facilities: fix typoHeiko Carstens
There really is no "general extension" facility available. Use the correct name "general instructions extension" facility instead. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2017-08-29microblaze: Convert to using %pOF instead of full_nameRob Herring
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michal Simek <monstr@monstr.eu>
2017-08-29MIPS: Remove pt_regs adjustments in indirect syscall handlerJames Cowgill
If a restartable syscall is called using the indirect o32 syscall handler - eg: syscall(__NR_waitid, ...), then it is possible for the incorrect arguments to be passed to the syscall after it has been restarted. This is because the syscall handler tries to shift all the registers down one place in pt_regs so that when the syscall is restarted, the "real" syscall is called instead. Unfortunately it only shifts the arguments passed in registers, not the arguments on the user stack. This causes the 4th argument to be duplicated when the syscall is restarted. Fix by removing all the pt_regs shifting so that the indirect syscall handler is called again when the syscall is restarted. The comment "some syscalls like execve get their arguments from struct pt_regs" is long out of date so this should now be safe. Signed-off-by: James Cowgill <James.Cowgill@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Tested-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15856/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-29MIPS: seccomp: Fix indirect syscall argsJames Hogan
Since commit 669c4092225f ("MIPS: Give __secure_computing() access to syscall arguments."), upon syscall entry when seccomp is enabled, syscall_trace_enter() passes a carefully prepared struct seccomp_data containing syscall arguments to __secure_computing(). Unfortunately it directly uses mips_get_syscall_arg() and fails to take into account the indirect O32 system calls (i.e. syscall(2)) which put the system call number in a0 and have the arguments shifted up by one entry. We can't just revert that commit as samples/bpf/tracex5 would break again, so use syscall_get_arguments() which already takes indirect syscalls into account instead of directly using mips_get_syscall_arg(), similar to what populate_seccomp_data() does. This also removes the redundant error checking of the mips_get_syscall_arg() return value (get_user() already zeroes the result if an argument from the stack can't be loaded). Reported-by: James Cowgill <James.Cowgill@imgtec.com> Fixes: 669c4092225f ("MIPS: Give __secure_computing() access to syscall arguments.") Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Kees Cook <keescook@chromium.org> Cc: David Daney <david.daney@cavium.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Will Drewry <wad@chromium.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Alexei Starovoitov <ast@kernel.org> Cc: Daniel Borkmann <daniel@iogearbox.net> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16994/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-29MIPS: CM: Use BIT/GENMASK for register fields, order & drop shiftsPaul Burton
There's no reason for us not to use BIT() & GENMASK() in asm/mips-cm.h when declaring macros corresponding to register fields. This patch modifies our definitions to do so. The *_SHF definitions are removed entirely - they duplicate information found in the masks, are infrequently used & can be replaced with use of __ffs() where needed. The *_MSK definitions then lose their _MSK suffix which is now somewhat redundant, and users are modified to match. The field definitions are moved to follow the appropriate register's accessor functions, which helps to keep the field definitions in order & to find the appropriate fields for a given register. Whilst here a comment is added describing each register & including its name, which is helpful both for linking the register back to hardware documentation & for grepping purposes. This also cleans up a couple of issues that became obvious as a result of making the changes described above: - We previously had definitions for GCR_Cx_RESET_EXT_BASE & a phony copy of that named GCR_RESET_EXT_BASE - a register which does not exist. The bad definitions were added by commit 497e803ebf98 ("MIPS: smp-cps: Ensure secondary cores start with EVA disabled") and made use of from boot_core(), which is now modified to use the GCR_Cx_RESET_EXT_BASE definitions. - We had a typo in CM_GCR_ERROR_CAUSE_ERRINGO_MSK - we now correctly define this as inFo rather than inGo. Now that we don't duplicate field information between _SHF & _MSK definitions, and keep the fields next to the register accessors, it will be much easier to spot & prevent any similar oddities being introduced in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17001/ Patchwork: https://patchwork.linux-mips.org/patch/17216/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-29MIPS: CM: Specify register size when generating accessorsPaul Burton
Some CM registers are always 32 bits, or at least only use bits in the lower 32 bits of the register. For these registers it is wasteful for us to generate accessors which bother to check mips_cm_is64 & perform 64 bit accesses. This patch modifies the accessor generation to take into account the size of the register, and for 32 bit registers we generate accessors which only ever perform 32 bit accesses. For 64 bit registers we either perform a 64 bit access or two 32 bit accesses, depending upon the value of mips_cm_is64. Doing this saves us ~1.5KiB of code in a generic 64r6el kernel, and perhaps more importantly simplifies various code paths. This removes the read64_gcr_* accessors, so mips_cm_error_report() is modified to stop using them & instead use the regular read_gcr_* accessors which will return 64 bit values from the 64 bit registers. The new accessor macros are placed in asm/mips-cps.h such that they can be shared by CPC & GIC code in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17000/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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