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2023-10-05arm64: dts: renesas: Add initial device tree for RZ/G3S SMARC EVK boardClaudiu Beznea
Add the initial device tree for the Renesas RZ/G3S SMARC EVK board. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-28-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05arm64: dts: renesas: Add initial device tree for RZ SMARC Carrier-II BoardClaudiu Beznea
Add the initial device tree for the RZ SMARC Carrier-II. At the moment it contains only the serial interface. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-26-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05arm64: dts: renesas: Add initial support for RZ/G3S SMARC SoMClaudiu Beznea
Add initial support for the RZ/G3S SMARC SoM. The following devices available on the SoM are added to this initial device tree: - RZ/G3S SoC: Renesas R9A08G045S33GBG - Clock Generator (only 24MHz output): Renesas 5L35023B - 1GiB LPDDR4 SDRAM: Micron MT53D512M16D1DS-046 - 64GB eMMC Flash (though SD ch0): Micron MTFC64GBCAQTC SD channel 0 of RZ/G3S is connected to an uSD card interface and an eMMC. The selection b/w them is done through a hardware switch. The DT will select b/w uSD and eMMC through the SW_SD0_DEV_SEL build flag. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-25-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05arm64: dts: renesas: Add initial DTSI for RZ/G3S SoCClaudiu Beznea
Add the initial DTSI for the RZ/G3S SoC. The files in this commit have the following meaning: - r9a08g045.dtsi: RZ/G3S family SoC common parts - r9a08g045s33.dtsi: RZ/G3S R0A08G045S33 SoC specific parts Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-23-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly ↵Lad Prabhakar
disabled Now that noncoherent dma support for the RZ/Five SoC has been added, enable the IP blocks which were disabled on the RZ/Five SMARC. This adds support for the below peripherals: * Ethernet * DMAC * SDHI * USB * RSPI * SSI Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929000704.53217-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05riscv: dts: renesas: r9a07g043f: Add dma-noncoherent propertyLad Prabhakar
RZ/Five is a noncoherent SoC so to indicate this add dma-noncoherent property to RZ/Five SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929000704.53217-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05riscv: dts: renesas: r9a07g043f: Add L2 cache nodeLad Prabhakar
Add L2 cache node for RZ/Five SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929000704.53217-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05ARM: dts: renesas: bockw: Add FLASH nodeGeert Uytterhoeven
Add a device node for the Spansion S29GL512P NOR FLASH on the Bock-W development board. This FLASH resides in the external address space of the Local Bus State Controller. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/45e6343ae07ef1add8bba5e8281ef9e6a977c573.1694768311.git.geert+renesas@glider.be
2023-10-05arm64: dts: renesas: rz-smarc: Use versa3 clk for audio mclkBiju Das
Currently audio mclk uses a fixed clk of 11.2896MHz (multiple of 44.1kHz). Replace this fixed clk with the programmable versa3 clk that can provide the clocking to support both 44.1kHz (with a clock of 11.2896MHz) and 48kHz (with a clock of 12.2880MHz), based on audio sampling rate for playback and record. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230825090518.87394-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05ARM: multi_v7_defconfig: add tm2-touchkey driverMarek Szyprowski
The Cypress 'touchkey' hardware is available on Exynos4412-based Midas family boards, so enable the driver for it to increase testing coverage. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20231005111718.1096634-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-10-05s390/pci: Fix reset of IOMMU software countersNiklas Schnelle
Together with enabling the Function Measurement Block zpci_fmb_enable_device() also resets the software counters. This allows to use "echo 0 > /sys/kernel/debug/pci/<dev>/statistics" followed by echo "1 > /../statistics" to reset all counters. In commit c76c067e488c ("s390/pci: Use dma-iommu layer") this use of the now obsolete counters in struct zpci_device was missed as was their removal. Fix this by resetting the new counters and removing the old ones. Fixes: c76c067e488c ("s390/pci: Use dma-iommu layer") Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Link: https://lore.kernel.org/r/20231004-dma_iommu_fix-v1-1-129777cd8232@linux.ibm.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2023-10-05crypto: x86/aesni - Perform address alignment early for XTS modeChang S. Bae
Currently, the alignment of each field in struct aesni_xts_ctx occurs right before every access. However, it's possible to perform this alignment ahead of time. Introduce a helper function that converts struct crypto_skcipher *tfm to struct aesni_xts_ctx *ctx and returns an aligned address. Utilize this helper function at the beginning of each XTS function and then eliminate redundant alignment code. Suggested-by: Eric Biggers <ebiggers@kernel.org> Link: https://lore.kernel.org/all/ZFWQ4sZEVu%2FLHq+Q@gmail.com/ Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Cc: linux-crypto@vger.kernel.org Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2023-10-05crypto: x86/aesni - Correct the data type in struct aesni_xts_ctxChang S. Bae
Currently, every field in struct aesni_xts_ctx is defined as a byte array of the same size as struct crypto_aes_ctx. This data type is obscure and the choice lacks justification. To rectify this, update the field type in struct aesni_xts_ctx to match its actual structure. Suggested-by: Eric Biggers <ebiggers@kernel.org> Link: https://lore.kernel.org/all/ZFWQ4sZEVu%2FLHq+Q@gmail.com/ Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Cc: linux-crypto@vger.kernel.org Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2023-10-05crypto: x86/aesni - Refactor the common address alignment codeChang S. Bae
The address alignment code has been duplicated for each mode. Instead of duplicating the same code, refactor the alignment code and simplify the alignment helpers. Suggested-by: Eric Biggers <ebiggers@kernel.org> Link: https://lore.kernel.org/all/20230526065414.GB875@sol.localdomain/ Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Cc: linux-crypto@vger.kernel.org Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2023-10-05KVM: arm64: Use mtree_empty() to determine if SMCCC filter configuredOliver Upton
The smccc_filter maple tree is only populated if userspace attempted to configure it. Use the state of the maple tree to determine if the filter has been configured, eliminating the VM flag. Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20231004234947.207507-4-oliver.upton@linux.dev Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2023-10-05KVM: arm64: Only insert reserved ranges when SMCCC filter is usedOliver Upton
The reserved ranges are only useful for preventing userspace from adding a rule that intersects with functions we must handle in KVM. If userspace never writes to the SMCCC filter than this is all just wasted work/memory. Insert reserved ranges on the first call to KVM_ARM_VM_SMCCC_FILTER. Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20231004234947.207507-3-oliver.upton@linux.dev Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2023-10-05KVM: arm64: Add a predicate for testing if SMCCC filter is configuredOliver Upton
Eventually we can drop the VM flag, move around the existing implementation for now. Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20231004234947.207507-2-oliver.upton@linux.dev Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2023-10-05x86/entry/32: Remove SEP test for SYSEXITBrian Gerst
SEP must be already be present in order for do_fast_syscall_32() to be called on native 32-bit, so checking it again is unnecessary. Signed-off-by: Brian Gerst <brgerst@gmail.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20230721161018.50214-6-brgerst@gmail.com
2023-10-05x86/entry/32: Convert do_fast_syscall_32() to bool return typeBrian Gerst
Doesn't have to be 'long' - this simplifies the code a bit. Signed-off-by: Brian Gerst <brgerst@gmail.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20230721161018.50214-5-brgerst@gmail.com
2023-10-05x86/entry/compat: Combine return value test from syscall handlerBrian Gerst
Move the sysret32_from_system_call label to remove a duplicate test of the return value from the syscall handler. Signed-off-by: Brian Gerst <brgerst@gmail.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20230721161018.50214-4-brgerst@gmail.com
2023-10-05x86/entry/64: Remove obsolete comment on tracing vs. SYSRETBrian Gerst
This comment comes from a time when the kernel attempted to use SYSRET on all returns to userspace, including interrupts and exceptions. Ever since commit fffbb5dc ("Move opportunistic sysret code to syscall code path"), SYSRET is only used for returning from system calls. The specific tracing issue listed in this comment is not possible anymore. Signed-off-by: Brian Gerst <brgerst@gmail.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lore.kernel.org/r/20230721161018.50214-2-brgerst@gmail.com
2023-10-05Merge tag 'v6.6-rc4' into x86/entry, to pick up fixesIngo Molnar
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2023-10-05arm64: dts: qcom: sm8550-qrd: add orientation gpioNeil Armstrong
Specify orientation GPIO to the PMIC GLINK node. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231002-topic-sm8550-upstream-type-c-orientation-v2-4-125410d3ff95@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-10-05arm64: dts: qcom: sm8550-mtp: add orientation gpioNeil Armstrong
Specify orientation GPIO in the PMIC GLINK node. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231002-topic-sm8550-upstream-type-c-orientation-v2-3-125410d3ff95@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-10-04KVM: x86/xen: ignore the VCPU_SSHOTTMR_future flagPaul Durrant
Upstream Xen now ignores _VCPU_SSHOTTMR_future[1], since the only guest kernel ever to use it was buggy. By ignoring the flag the guest will always get a callback if it sets a negative timeout which upstream Xen has determined not to cause problems for any guest setting the flag. [1] https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=19c6cbd909 Signed-off-by: Paul Durrant <pdurrant@amazon.com> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Link: https://lore.kernel.org/r/20231004174628.2073263-1-paul@xen.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2023-10-04KVM: x86: Add SBPB supportJosh Poimboeuf
Add support for the AMD Selective Branch Predictor Barrier (SBPB) by advertising the CPUID bit and handling PRED_CMD writes accordingly. Note, like SRSO_NO and IBPB_BRTYPE before it, advertise support for SBPB even if it's not enumerated by in the raw CPUID. Some CPUs that gained support via a uCode patch don't report SBPB via CPUID (the kernel forces the flag). Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org> Link: https://lore.kernel.org/r/a4ab1e7fe50096d50fde33e739ed2da40b41ea6a.1692919072.git.jpoimboe@kernel.org Co-developed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Sean Christopherson <seanjc@google.com>
2023-10-04KVM: x86: Add IBPB_BRTYPE supportJosh Poimboeuf
Add support for the IBPB_BRTYPE CPUID flag, which indicates that IBPB includes branch type prediction flushing. Note, like SRSO_NO, advertise support for IBPB_BRTYPE even if it's not enumerated by in the raw CPUID, i.e. bypass the cpuid_count() in __kvm_cpu_cap_mask(). Some CPUs that gained support via a uCode patch don't report IBPB_BRTYPE via CPUID (the kernel forces the flag). Opportunistically use kvm_cpu_cap_check_and_set() for SRSO_NO instead of manually querying host support (cpu_feature_enabled() and boot_cpu_has() yield the same end result in this case). Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org> Link: https://lore.kernel.org/r/79d5f5914fb42c2c62418ffbcd78f138645ded21.1692919072.git.jpoimboe@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
2023-10-04KVM: SVM: Treat all "skip" emulation for SEV guests as outright failuresSean Christopherson
Treat EMULTYPE_SKIP failures on SEV guests as unhandleable emulation instead of simply resuming the guest, and drop the hack-a-fix which effects that behavior for the INT3/INTO injection path. If KVM can't skip an instruction for which KVM has already done partial emulation, resuming the guest is undesirable as doing so may corrupt guest state. Link: https://lore.kernel.org/r/20230825013621.2845700-5-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2023-10-04KVM: x86: Refactor can_emulate_instruction() return to be more expressiveSean Christopherson
Refactor and rename can_emulate_instruction() to allow vendor code to return more than true/false, e.g. to explicitly differentiate between "retry", "fault", and "unhandleable". For now, just do the plumbing, a future patch will expand SVM's implementation to signal outright failure if KVM attempts EMULTYPE_SKIP on an SEV guest. No functional change intended (or rather, none that are visible to the guest or userspace). Link: https://lore.kernel.org/r/20230825013621.2845700-4-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2023-10-04ARM: dts: rockchip: Switch to operating-points-v2 for RK3128's CPUAlex Bee
This will allow frequency-scaling for the cpu-cores. Operating frequencies and voltages have been taken from Rockchip's downstream kernel. Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20230829214004.314932-10-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Enable SMP bring-up for RK3128Alex Bee
For bring-up of the non-boot cpu cores the enable-method for RK3036 can be re-used. This adds a (small) chunk of SRAM for execution of the SMP trampoline code and the respective enable-method property to the cpus. Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20230829214004.314932-8-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Add CPU resets for RK3128Alex Bee
In order to support bring-up of the non-boot cores, this patch adds the reset controls for the cpu cores. They are required/will be used by the Rockchip platsmp driver. Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20230829214004.314932-6-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Add SRAM node for RK3128Alex Bee
RK3128 SoCs have 8KB of SRAM. Add the respective device tree node for it. Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20230829214004.314932-4-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Enable pwm fan for edgeble-neu2Jagan Teki
Edgeble Neu2 IO board Fan connected to PWM11. Enable the pwm fan for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20230731103518.2906147-10-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Add pwm11 node to rv1126Jagan Teki
Add pwm11 node for Rockchip RV1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20230731103518.2906147-6-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Add pwm11m0 pins to rv1126Jagan Teki
Add pwm11m0 pins for Rockchip RV1126 PWM11. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20230731103518.2906147-5-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Add pwm2 node to rv1126Jagan Teki
Add PWM2 node for Rockchip RV1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20230731103518.2906147-4-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Add pwm2m0 pins to rv1126Jagan Teki
Add pwm2m0 pins for Rockchip RV1126 PWM2. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20230731103518.2906147-3-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Fix timer clocks for RK3128Alex Bee
Currently the Rockchip timer source clocks are set to xin24 for no obvious reason and the actual timer clocks (SCLK_TIMER*) will get disabled during boot process as they have no user. That will make the SoC stuck as no timer source exists. Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi") Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20230829203721.281455-12-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Add missing quirk for RK3128's dma engineAlex Bee
Like most other Rockchip ARM SoCs, the PL330 needs the arm,pl330-periph-burst quirk in order to work as expected. Add it. Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi") Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20230829203721.281455-10-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Add missing arm timer interrupt for RK3128Alex Bee
The Cortex-A7 timer has 4 interrupts. Add the missing one. Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi") Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20230829203721.281455-8-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04ARM: dts: rockchip: Fix i2c0 register address for RK3128Alex Bee
The register address for i2c0 is missing a 0x to mark it as hex. Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi") Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20230829203721.281455-6-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04arm64: dts: rockchip: Add NanoPC T6 PCIe e-key supportJohn Clark
before ~~~~ 0000:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01) 0002:20:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01) 0002:21:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller (rev 05) 0004:40:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01) 0004:41:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller (rev 05) after ~~~ 0000:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01) 0002:20:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01) 0002:21:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller (rev 05) 0003:30:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01) 0003:31:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8822CE 802.11ac PCIe Wireless Network Adapter 0004:40:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01) 0004:41:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller (rev 05) Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20230906012305.7113-1-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04arm64: dts: rockchip: set codec system-clock-fixed on px30-ringneck-haikouJakob Unterwurzacher
Having sgtl5000_clk defines as "fixed-clock" is not enough to prevent the dai subsystem from overwriting the frequency via sgtl5000_set_dai_sysclk. Setting system-clock-fixed does the job, and now a 1kHz sine wave comes out as actually 1kHz, no matter the sample rate of the source. Testcase: These should sound the same: speaker-test -r 48000 -t sine -f 1000 speaker-test -r 24000 -t sine -f 1000 Also remove the clock link here as having it in sgtl5000 and sgtl5000_codec causes duplicate clock unprepares with associated backtrace. Cc: stable@vger.kernel.org Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard") Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Link: https://lore.kernel.org/r/20230907151725.198347-2-jakob.unterwurzacher@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04arm64: dts: rockchip: use codec as clock master on px30-ringneck-haikouErmin Sunj
If the codec is not the clock master, the MCLK needs to be synchronous to both I2S_SCL ans I2S_LRCLK. We do not have that on Haikou, causing distorted audio. Before: Running an audio test script on Ringneck, 1kHz output sine wave is not stable and shows distortion. After: 10h audio test script loop failed only one time. That is 0.00014% failure rate. Cc: stable@vger.kernel.org Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard") Signed-off-by: Ermin Sunj <ermin.sunj@theobroma-systems.com> Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Link: https://lore.kernel.org/r/20230907151725.198347-1-jakob.unterwurzacher@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04arm64: dts: rockchip: Add sdio node to rock-5bTamás Szűcs
Enable SDIO on Radxa ROCK 5 Model B M.2 Key E. Add sdio node and alias as mmc2. Add regulator for the 3.3 V rail bringing it up during boot. Make sure EKEY_EN is muxed as GPIO. Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230924203740.65744-1-tszucs@protonmail.ch Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04arm64: dts: rockchip: add PCIe3 bus to rk3588-evb1Sebastian Reichel
Enable PCIe3 support, which is exposed via a PCIe3 connector. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230918141327.131108-3-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04arm64: dts: rockchip: add PCIe2 network controller to rk3588-evb1Sebastian Reichel
The RK3588 EVB1 has a second network card, which is connected via PCIe2. This adds support for that. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230918141327.131108-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5bSebastian Reichel
Enable PCIe2_0 controller and its voltage supply, which is routed to the M.2 E-Key on the upper side of the Radxa Rock 5B. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230918141451.131247-4-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-04arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5bSebastian Reichel
The Radxa Rock 5B has PCIe 3x4 routed to its M.2 M-key connector on the board's back. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230918141451.131247-3-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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