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2023-10-10x86/apic: Use u32 for phys_pkg_id()Thomas Gleixner
APIC IDs are used with random data types u16, u32, int, unsigned int, unsigned long. Make it all consistently use u32 because that reflects the hardware register width even if that callback going to be removed soonish. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Arjan van de Ven <arjan@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085113.113097126@linutronix.de
2023-10-10x86/apic: Use u32 for cpu_present_to_apicid()Thomas Gleixner
APIC IDs are used with random data types u16, u32, int, unsigned int, unsigned long. Make it all consistently use u32 because that reflects the hardware register width and fixup a few related usage sites for consistency sake. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Arjan van de Ven <arjan@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085113.054064391@linutronix.de
2023-10-10x86/apic: Use u32 for check_apicid_used()Thomas Gleixner
APIC IDs are used with random data types u16, u32, int, unsigned int, unsigned long. Make it all consistently use u32 because that reflects the hardware register width and move the default implementation to local.h as there are no users outside the apic directory. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Arjan van de Ven <arjan@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.981956102@linutronix.de
2023-10-10x86/apic: Use u32 for APIC IDs in global dataThomas Gleixner
APIC IDs are used with random data types u16, u32, int, unsigned int, unsigned long. Make it all consistently use u32 because that reflects the hardware register width and fixup the most obvious usage sites of that. The APIC callbacks will be addressed separately. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Arjan van de Ven <arjan@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.922905727@linutronix.de
2023-10-10x86/apic: Use BAD_APICID consistentlyThomas Gleixner
APIC ID checks compare with BAD_APICID all over the place, but some initializers and some code which fiddles with global data structure use -1[U] instead. That simply cannot work at all. Fix it up and use BAD_APICID consistently all over the place. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.862835121@linutronix.de
2023-10-10x86/cpu: Move cpu_l[l2]c_id into topology infoThomas Gleixner
The topology IDs which identify the LLC and L2 domains clearly belong to the per CPU topology information. Move them into cpuinfo_x86::cpuinfo_topo and get rid of the extra per CPU data and the related exports. This also paves the way to do proper topology evaluation during early boot because it removes the only per CPU dependency for that. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Arjan van de Ven <arjan@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.803864641@linutronix.de
2023-10-10x86/cpu: Move logical package and die IDs into topology infoThomas Gleixner
Yet another topology related data pair. Rename logical_proc_id to logical_pkg_id so it fits the common naming conventions. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.745139505@linutronix.de
2023-10-10x86/cpu: Remove pointless evaluation of x86_coreid_bitsThomas Gleixner
cpuinfo_x86::x86_coreid_bits is only used by the AMD numa topology code. No point in evaluating it on non AMD systems. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Arjan van de Ven <arjan@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.687588373@linutronix.de
2023-10-10x86/cpu: Move cu_id into topology infoThomas Gleixner
No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.628405546@linutronix.de
2023-10-10x86/cpu: Move cpu_core_id into topology infoThomas Gleixner
Rename it to core_id and stick it to the other ID fields. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.566519388@linutronix.de
2023-10-10x86/cpu: Move cpu_die_id into topology infoThomas Gleixner
Move the next member. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.388185134@linutronix.de
2023-10-10x86/cpu: Move phys_proc_id into topology infoThomas Gleixner
Rename it to pkg_id which is the terminology used in the kernel. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.329006989@linutronix.de
2023-10-10x86/cpu: Encapsulate topology information in cpuinfo_x86Thomas Gleixner
The topology related information is randomly scattered across cpuinfo_x86. Create a new structure cpuinfo_topo and move in a first step initial_apicid and apicid into it. Aside of being better readable this is in preparation for replacing the horribly fragile CPU topology evaluation code further down the road. Consolidate APIC ID fields to u32 as that represents the hardware type. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.269787744@linutronix.de
2023-10-10x86/apic: Fake primary thread mask for XEN/PVThomas Gleixner
The SMT control mechanism got added as speculation attack vector mitigation. The implemented logic relies on the primary thread mask to be set up properly. This turns out to be an issue with XEN/PV guests because their CPU hotplug mechanics do not enumerate APICs and therefore the mask is never correctly populated. This went unnoticed so far because by chance XEN/PV ends up with smp_num_siblings == 2. So cpu_smt_control stays at its default value CPU_SMT_ENABLED and the primary thread mask is never evaluated in the context of CPU hotplug. This stopped "working" with the upcoming overhaul of the topology evaluation which legitimately provides a fake topology for XEN/PV. That sets smp_num_siblings to 1, which causes the core CPU hot-plug core to refuse to bring up the APs. This happens because cpu_smt_control is set to CPU_SMT_NOT_SUPPORTED which causes cpu_bootable() to evaluate the unpopulated primary thread mask with the conclusion that all non-boot CPUs are not valid to be plugged. The core code has already been made more robust against this kind of fail, but the primary thread mask really wants to be populated to avoid other issues all over the place. Just fake the mask by pretending that all XEN/PV vCPUs are primary threads, which is consistent because all of XEN/PVs topology is fake or non-existent. Fixes: 6a4d2657e048 ("x86/smp: Provide topology_is_primary_thread()") Fixes: f54d4434c281 ("x86/apic: Provide cpu_primary_thread mask") Reported-by: Juergen Gross <jgross@suse.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.210011520@linutronix.de
2023-10-10x86/cpu/hygon: Fix the CPU topology evaluation for realPu Wen
Hygon processors with a model ID > 3 have CPUID leaf 0xB correctly populated and don't need the fixed package ID shift workaround. The fixup is also incorrect when running in a guest. Fixes: e0ceeae708ce ("x86/CPU/hygon: Fix phys_proc_id calculation logic for multi-die processors") Signed-off-by: Pu Wen <puwen@hygon.cn> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/tencent_594804A808BD93A4EBF50A994F228E3A7F07@qq.com Link: https://lore.kernel.org/r/20230814085112.089607918@linutronix.de
2023-10-10powerpc: Only define __parse_fpscr() when requiredChristophe Leroy
Clang 17 reports: arch/powerpc/kernel/traps.c:1167:19: error: unused function '__parse_fpscr' [-Werror,-Wunused-function] __parse_fpscr() is called from two sites. First call is guarded by #ifdef CONFIG_PPC_FPU_REGS Second call is guarded by CONFIG_MATH_EMULATION which selects CONFIG_PPC_FPU_REGS. So only define __parse_fpscr() when CONFIG_PPC_FPU_REGS is defined. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202309210327.WkqSd5Bq-lkp@intel.com/ Fixes: b6254ced4da6 ("powerpc/signal: Don't manage floating point regs when no FPU") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/5de2998c57f3983563b27b39228ea9a7229d4110.1695385984.git.christophe.leroy@csgroup.eu
2023-10-10powerpc/85xx: Fix math emulation exceptionChristophe Leroy
Booting mpc85xx_defconfig kernel on QEMU leads to: Bad trap at PC: fe9bab0, SR: 2d000, vector=800 awk[82]: unhandled trap (5) at 0 nip fe9bab0 lr fe9e01c code 5 in libc-2.27.so[fe5a000+17a000] awk[82]: code: 3aa00000 3a800010 4bffe03c 9421fff0 7ca62b78 38a00000 93c10008 83c10008 awk[82]: code: 38210010 4bffdec8 9421ffc0 7c0802a6 <fc00048e> d8010008 4815190d 93810030 Trace/breakpoint trap WARNING: no useful console This is because allthough CONFIG_MATH_EMULATION is selected, Exception 800 calls unknown_exception(). Call emulation_assist_interrupt() instead. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/066caa6d9480365da9b8ed83692d7101e10ac5f8.1695657339.git.christophe.leroy@csgroup.eu
2023-10-10arm64: dts: imx8mp-beacon: Add DMIC supportAdam Ford
The baseboard has a connector for a pulse density microphone. This is connected via the micfil interface and uses the DMIC audio codec with the simple-audio-card. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mn-beacon: Add DMIC supportAdam Ford
The baseboard has a connector for a pulse density microphone. This is connected via the micfil interface and uses the DMIC audio codec with the simple-audio-card. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mm-beacon: Add DMIC supportAdam Ford
The baseboard has a connector for a pulse density microphone. This is connected via the micfil interface and uses the DMIC audio codec with the simple-audio-card. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mm-beacon: Migrate sound card to simple-audio-cardAdam Ford
Instead of using a custom glue layer connecting the wm8962 CODEC to the SAI3 sound-dai, migrate the sound card to simple-audio-card. This also brings this board in line with the imx8mn-beacon and imx8mp-beacon. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mn-evk: Remove codec clocks/clock-namesFabio Estevam
Per wlf,wm8524.yaml, 'clocks' and 'clock-names' are not valid properties. Remove them to fix the following schema warning: audio-codec: Unevaluated properties are not allowed ('clock-names', 'clocks' were unexpected) from schema $id: http://devicetree.org/schemas/sound/wlf,wm8524.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mp-beacon: Configure 100MHz PCIe Ref ClkAdam Ford
There is a I2C controlled 100MHz Reference clock used by the PCIe controller. Configure this clock's DIF1 output to be used by the PCIe. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mn: Add sound-dai-cells to micfil nodeAdam Ford
Per the DT bindings, the micfil node should have a sound-dai-cells entry. Fixes: cca69ef6eba5 ("arm64: dts: imx8mn: Add support for micfil") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mm: Add sound-dai-cells to micfil nodeAdam Ford
Per the DT bindings, the micfil node should have a sound-dai-cells entry. Fixes: 3bd0788c43d9 ("arm64: dts: imx8mm: Add support for micfil") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: freescale: add initial device tree for TQMLS1088AGregor Herburger
This adds support for TQMLS1088A SOM on MBLS10xxA baseboard. Signed-off-by: Gregor Herburger <gregor.herburger@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: freescale: add initial device tree for TQMLS1043A/TQMLS1046AGregor Herburger
This adds support for the TQMLS1043A and TQMLS1046A SOM and the MBLS10xxA baseboard. TQMLS1043A and TQMLS1046A share a common layout and can be used on the MBLS10xxA. Signed-off-by: Gregor Herburger <gregor.herburger@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: ls1043a: remove second dspi nodeGregor Herburger
According to the documentation the ls1043a has only one spi controller. So remove the second one. Signed-off-by: Gregor Herburger <gregor.herburger@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: freescale: Add support for LX2162 SoM & Clearfog BoardJosua Mayer
Add support for the SolidRun LX2162A System on Module (SoM), and the Clearfog evaluation board. The SoM has few software-controllable features: - AR8035 Ethernet PHY - eMMC - SPI Flash - fan controller - various eeproms The Clearfog evaluation board provides: - microSD connector - USB-A - 2x 10Gbps SFP+ - 2x 25Gbps SFP+ with a retimer - 8x 2.5Gbps RJ45 - 2x mPCI (assembly option / disables 2xRJ45) The 8x RJ45 ports are connected with an 8-port PHY: Marvell 88E2580 supporting up to 5Gbps, while SoC and magnetics are limited to 2.5Gbps. However 2500 speed is untested due to documentation and drivier limitations. To avoid confusion the phy nodes have been explicitly limited to 1000 for now. The PCI nodes are disabled, but explicitly added to mark that this board can have pci. It is expected that the bootloader will patch the status property "okay" and disable 2x RJ45 ports, according to active serdes configuration. Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: lx2160a: describe the SerDes block #2Josua Mayer
Add description for the LX2160A second SerDes block. It is functionally identical to the first one already added in commit 3cbe93a1f540 ("arch: arm64: dts: lx2160a: describe the SerDes block #1"). The SerDes driver currently updates the registers of all 8 lanes by default during probe. Because currently this driver only supports configuration of network protocols, this can lead to problems with certain configurations. Set status property to "disabled" by default so that existing boards are not impacted. Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx93: update gpio nodePeng Fan
Per binding doc, i.MX93 GPIO supports two interrupts and one register base, compatible with i.MX8ULP. The current fsl,imx7ulp-gpio compatible could work for i.MX93 in gpio-vf610.c driver, it is based on the base address are splited into two with offset added in device tree node. Now following hardware design, using one register base in device tree node. This may break users who use compatible fsl,imx7ulp-gpio to enable i.MX93 GPIO. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8ulp: update gpio nodePeng Fan
The i.MX8ULP GPIO supports two interrupts and one register base, the current fsl,imx7ulp-gpio compatible could work for i.MX8ULP in gpio-vf610.c driver, it is based on the base address are splited into two with offset added in device tree node. Now following hardware design, using one register base in device tree node. This may break users who use compatible fsl,imx7ulp-gpio to enable i.MX8ULP GPIO. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mq-librem5: Fix tps65132 compatibleFabio Estevam
The valid compatible string for the tps65132 regulator is "ti,tps65132". Change it. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mp-debix-model-a: Remove USB hub reset-gpiosFabio Estevam
The SAI2_TXC pin is left unconnected per the imx8mp-debix-model-a schematics: https://debix.io/Uploads/Temp/file/20230331/DEBIX%20Model%20A%20Schematics.pdf Also, the RTS5411E USB hub chip does not have a reset pin. Remove this pin description to properly describe the hardware. This also fixes the following schema warning: hub@1: 'reset-gpios' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/usb/realtek,rts5411.yaml# Fixes: 0253e1cb6300 ("arm64: dts: imx8mp-debix: add USB host support") Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8-apalis-v1.1: Fix Ethernet PHY reset-namesFabio Estevam
Per ethernet-phy.yaml, the expected value for the 'reset-names' property is "phy". Change it accordingly to fix the following schema warning: imx8qm-apalis-ixora-v1.1.dtb: ethernet-phy@7: reset-names:0: 'phy' was expected from schema $id: http://devicetree.org/schemas/net/ethernet-phy.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mm-venice-gw790: Remove phy-mode from switch nodeFabio Estevam
Per microchip,ksz.yaml, phy-mode is not a valid property in the top-level switch node. phy-mode = "rgmii-id" is already passed in the CPU port switch (port@5). Remove it from the top-level switch node to fix the following schema warning: switch@5f: Unevaluated properties are not allowed ('phy-mode' was unexpected) from schema $id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mp-venice-gw73xx: add TPM deviceTim Harvey
Add the TPM device found on the GW73xx revision F PCB. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mm-venice-gw73xx: add TPM deviceTim Harvey
Add the TPM device found on the GW73xx revision F PCB. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mp-verdin: Remove invalid property from eqosFabio Estevam
Per nxp,dwmac-imx.yaml, it is not valid to pass 'phy-supply'. The reg_module_eth1phy regulator is marked with 'regulator-always-on', so it is safe to remove it from the eqos node. Remove it to fix the following schema warning: imx8mp-verdin-nonwifi-dahlia.dtb: ethernet@30bf0000: Unevaluated properties are not allowed ('phy-supply' was unexpected) from schema $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8qm-ss-img: Fix jpegenc compatible entryFabio Estevam
The first compatible entry for the jpegenc should be 'nxp,imx8qm-jpgenc'. Change it accordingly to fix the following schema warning: imx8qm-apalis-eval.dtb: jpegenc@58450000: compatible: 'oneOf' conditional failed, one must be fixed: 'nxp,imx8qm-jpgdec' is not one of ['nxp,imx8qxp-jpgdec', 'nxp,imx8qxp-jpgenc'] 'nxp,imx8qm-jpgenc' was expected 'nxp,imx8qxp-jpgdec' was expected Fixes: 5bb279171afc ("arm64: dts: imx8: Add jpeg encoder/decoder nodes") Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Mirela Rabulea <mirela.rabulea@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx93: Fix the dmas entries orderFabio Estevam
Per fsl-lpuart.yaml, the dmas and dma-names entries should be 'rx' followed by 'tx'. Change the order to fix the following schema warning: imx93-11x11-evk.dtb: serial@44380000: dma-names:0: 'rx' was expected from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml# imx93-11x11-evk.dtb: serial@44380000: dma-names:1: 'tx' was expected from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mm-venice-gw790: Pass GSC address/size-cellsFabio Estevam
Per gateworks-gsc.yaml, #address-cells and #size-cells are mandatory properties. Pass them to fix the following schema warning: imx8mm-venice-gw7903.dtb: gsc@20: '#address-cells' is a required property from schema $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml# imx8mm-venice-gw7903.dtb: gsc@20: '#size-cells' is a required property from schema $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8dxl: Pass fsl,imx8dxl-sc-wdtFabio Estevam
Pass 'fsl,imx8dxl-sc-wdt' to fix the following schema warning: system-controller: watchdog:compatible:0: 'fsl,imx8qxp-sc-wdt' was expected from schema $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# system-controller: watchdog:compatible: ['fsl,imx-sc-wdt'] is too short from schema $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8dxl: Pass fsl,imx8dxl-sc-thermalFabio Estevam
Pass 'fsl,imx8dxl-sc-thermal' to fix the following schema warning: system-controller: thermal-sensor:compatible:0: 'fsl,imx8qxp-sc-thermal' was expected from schema $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# system-controller: thermal-sensor:compatible: ['fsl,imx-sc-thermal'] is too short from schema $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8dxl: Remove wakeup-irqFabio Estevam
wakeup-irq is not documented, and not used anywhere. Remove it. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8dxl: Pass fsl,imx8dl-scu-pdFabio Estevam
Pass 'fsl,imx8dl-scu-pd' to fix the following schema warning: system-controller: power-controller:compatible:0: 'fsl,scu-pd' is not one of ['fsl,imx8qm-scu-pd', 'fsl,imx8qxp-scu-pd'] from schema $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8qm-mek: enable 8qm lpuart2 and lpuart3Frank Li
Enable uart2 and uart3 for imx8qm-mek board. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8qxp-mek: enable 8qxp lpuart2 and lpuart3Frank Li
Enable uart2 and uart3 for imx8qxp-mek board. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8: update lpuart[0..3] irq numberFrank Li
Original irq number combined UART irq and DMA irq. These doesn't match uart driver and dma engine's expection. Update to the irq numbers, which just uart can trigger. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8qm: Update edma channel for uart[0..3]Frank Li
imx8qm have difference dma channel number for uart[0..3]. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit (git 2.34.1) at 2025-10-01 11:15:43 +0000