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2017-01-26arm64: kernel: do not mark reserved memory regions as IORESOURCE_BUSYArd Biesheuvel
Memory regions marked as NOMAP should not be used for general allocation by the kernel, and should not even be covered by the linear mapping (hence the name). However, drivers or other subsystems (such as ACPI) that access the firmware directly may legally access them, which means it is also reasonable for such drivers to claim them by invoking request_resource(). Currently, this is prevented by the fact that arm64's request_standard_resources() marks reserved regions as IORESOURCE_BUSY. So drop the IORESOURCE_BUSY flag from these requests. Reported-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-26arm64: Use __pa_symbol for empty_zero_pageGeert Uytterhoeven
If CONFIG_DEBUG_VIRTUAL=y and CONFIG_ARM64_SW_TTBR0_PAN=y: virt_to_phys used for non-linear address: ffffff8008cc0000 (empty_zero_page+0x0/0x1000) WARNING: CPU: 0 PID: 0 at arch/arm64/mm/physaddr.c:14 __virt_to_phys+0x28/0x60 ... [<ffffff800809abb4>] __virt_to_phys+0x28/0x60 [<ffffff8008a02600>] setup_arch+0x46c/0x4d4 Fixes: 2077be6783b5936c ("arm64: Use __pa_symbol for kernel symbols") Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Laura Abbott <labbott@redhat.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-01-26arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h headerChen-Yu Tsai
All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm64/boot/dts/allwinner/*.dts? Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-25arm64: dts: Add dts files for Hisilicon Hi3660 SoCChen Feng
Add initial dtsi file to support Hisilicon Hi3660 SoC with support of Octal core CPUs in two clusters(4 * A53 & 4 * A73). Also add dts file to support HiKey960 development board which based on Hi3660 SoC. The output console is earlycon "earlycon=pl011,0xfdf05000". And the con_init uart5 with a fixed clock, which already configured at bootloader. When clock is available, the uart5 will be modified. Tested on HiKey960 Board. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-01-25ARM: dts: watchdog0 cannot reliably trigger resetDinh Nguyen
On the Arria10, because of hardware bug, watchdog0 cannot reliably trigger a reset to the CPU. The workaround would be to use watchdog1 instead. Also for watchdog1, there is a dependency on the bootloader to enable the boot_clk source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This corresponds to the (SWCTRLBTCLKEN & SWCTRLBTCLKSEL) bits enabled in the control register in the clock manager module of Arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-25KVM: arm/arm64: vgic: Add debugfs vgic-state fileChristoffer Dall
Add a file to debugfs to read the in-kernel state of the vgic. We don't do any locking of the entire VGIC state while traversing all the IRQs, so if the VM is running the user/developer may not see a quiesced state, but should take care to pause the VM using facilities in user space for that purpose. We also don't support LPIs yet, but they can be added easily if needed. Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2017-01-25x86/boot: Fix KASLR and memmap= collisionDave Jiang
CONFIG_RANDOMIZE_BASE=y relocates the kernel to a random base address. However it does not take into account the memmap= parameter passed in from the kernel command line. This results in the kernel sometimes being put in the middle of memmap. Teach KASLR to not insert the kernel in memmap defined regions. We support up to 4 memmap regions: any additional regions will cause KASLR to disable. The mem_avoid set has been augmented to add up to 4 unusable regions of memmaps provided by the user to exclude those regions from the set of valid address range to insert the uncompressed kernel image. The nn@ss ranges will be skipped by the mem_avoid set since it indicates that memory is useable. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Kees Cook <keescook@chromium.org> Acked-by: Baoquan He <bhe@redhat.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: dan.j.williams@intel.com Cc: david@fromorbit.com Cc: linux-nvdimm@lists.01.org Link: http://lkml.kernel.org/r/148417664156.131935.2248592164852799738.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-25ARM: tegra: nyan-blaze: Proper pinmux for TPM I2CJerome Coste
This corrects the pinmux for accessing the TPM over the I2C line. Thus, it allows correctly probing the module, that previously failed with I2C errors. Signed-off-by: Jerome Coste <jerome.coste@etu.utc.fr> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: nyan-big: Proper pinmux for TPM I2CPaul Kocialkowski
This corrects the pinmux for accessing the TPM over the I2C line. Thus, it allows correctly probing the module, that previously failed with I2C errors. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: nyan-blaze: Include compatible revisions for proper detectionPaul Kocialkowski
Depthcharge (the payload used with cros devices) will attempt to detect boards using their revision. This includes all the known revisions for the nyan-blaze board so that the dtb can be selected preferably. Defining compatibly revisions allows depthcharge to select the kernel via the revision it detects instead of using the default kernel. This allows having a FIT image with multiple kernels for multiple devices. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: nyan-big: Include compatible revisions for proper detectionPaul Kocialkowski
Depthcharge (the payload used with cros devices) will attempt to detect boards using their revision. This includes all the known revisions for the nyan-big board so that the dtb can be selected preferably. Defining compatibly revisions allows depthcharge to select the kernel via the revision it detects instead of using the default kernel. This allows having a FIT image with multiple kernels for multiple devices. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: nyan: Use external control for bq24735 chargerPaul Kocialkowski
Nyan boards come with an embedded controller that controls when to enable and disable the charge. Thus, it should not be left up to the kernel to handle that. Using the ti,external-control property allows specifying this use-case. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: nyan: Use proper IRQ type definitionsPaul Kocialkowski
This switches a few interrupt definitions that were using GPIO_ACTIVE_HIGH as IRQ type, which is invalid. This is mostly a cosmetic change, that doesn't affect any driver. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: dts: r7s72100: add power-domains to mmcifChris Brandt
Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-25ARM: shmobile: rcar-gen2: Add more register documentationGeert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-25ARM: dts: tegra: Fix missing card detection in Trimslice µSD card slotRask Ingemann Lambertsen
Card insertion and removal currently goes undetected. AFAIK there's no way to generate interrupts on card changes in this slot, so use polling. Signed-off-by: Rask Ingemann Lambertsen <rask@formelder.dk> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25x86/fpu: Fix the "Giving up, no FPU found" testAndy Lutomirski
We would never print "Giving up, no FPU found" because X86_FEATURE_FPU was in REQUIRED_MASK on non-FPU-emulating builds, so the boot_cpu_has() test didn't do anything. Signed-off-by: Andy Lutomirski <luto@kernel.org> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matthew Whitehead <tedheadster@gmail.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Yu-cheng Yu <yu-cheng.yu@intel.com> Link: http://lkml.kernel.org/r/1499077fa76f0f84b8ea28e37d3fa70beca4e310.1484705016.git.luto@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-25x86/fpu: Fix CPUID-less FPU detectionAndy Lutomirski
The old code didn't work at all because it adjusted the current caps instead of the forced caps. Anything it did would be undone later during CPU identification. Fix that and, while we're at it, improve the logging and don't bother running it if CPUID is available. Reported-by: Matthew Whitehead <tedheadster@gmail.com> Signed-off-by: Andy Lutomirski <luto@kernel.org> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Yu-cheng Yu <yu-cheng.yu@intel.com> Link: http://lkml.kernel.org/r/f1134e30cafa73c4e2e68119e9741793622cfd15.1484705016.git.luto@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-25x86/fpu: Fix "x86/fpu: Legacy x87 FPU detected" messageAndy Lutomirski
That message isn't at all clear -- what does "Legacy x87" even mean? Clarify it. If there's no FPU, say: x86/fpu: No FPU detected If there's an FPU that doesn't have XSAVE, say: x86/fpu: x87 FPU will use FSAVE|FXSAVE Signed-off-by: Andy Lutomirski <luto@kernel.org> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matthew Whitehead <tedheadster@gmail.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Yu-cheng Yu <yu-cheng.yu@intel.com> Link: http://lkml.kernel.org/r/bb839385e18e27bca23fe8666dfdad8170473045.1484705016.git.luto@kernel.org [ Small tweaks to the messages. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-25x86/cpu: Re-apply forced caps every time CPU caps are re-readAndy Lutomirski
Calling get_cpu_cap() will reset a bunch of CPU features. This will cause the system to lose track of force-set and force-cleared features in the words that are reset until the end of CPU initialization. This can cause X86_FEATURE_FPU, for example, to change back and forth during boot and potentially confuse CPU setup. To minimize the chance of confusion, re-apply forced caps every time get_cpu_cap() is called. Signed-off-by: Andy Lutomirski <luto@kernel.org> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matthew Whitehead <tedheadster@gmail.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Yu-cheng Yu <yu-cheng.yu@intel.com> Link: http://lkml.kernel.org/r/c817eb373d2c67c2c81413a70fc9b845fa34a37e.1484705016.git.luto@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-25x86/cpu: Factor out application of forced CPU capsAndy Lutomirski
There are multiple call sites that apply forced CPU caps. Factor them into a helper. Signed-off-by: Andy Lutomirski <luto@kernel.org> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matthew Whitehead <tedheadster@gmail.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Yu-cheng Yu <yu-cheng.yu@intel.com> Link: http://lkml.kernel.org/r/623ff7555488122143e4417de09b18be2085ad06.1484705016.git.luto@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-25x86/cpu: Add X86_FEATURE_CPUIDBorislav Petkov
Add a synthetic CPUID flag denoting whether the CPU sports the CPUID instruction or not. This will come useful later when accomodating CPUID-less CPUs. Signed-off-by: Borislav Petkov <bp@suse.de> [ Slightly prettified. ] Signed-off-by: Andy Lutomirski <luto@kernel.org> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matthew Whitehead <tedheadster@gmail.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Yu-cheng Yu <yu-cheng.yu@intel.com> Link: http://lkml.kernel.org/r/dcb355adae3ab812c79397056a61c212f1a0c7cc.1484705016.git.luto@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-25powerpc/8xx: Implement hw_breakpointChristophe Leroy
This patch implements HW breakpoint on the 8xx. The 8xx has capability to manage HW breakpoints, which is slightly different than BOOK3S: 1/ The breakpoint match doesn't trigger a DSI exception but a dedicated data breakpoint exception. 2/ The breakpoint happens after the instruction has completed, no need to single step or emulate the instruction, 3/ Matched address is not set in DAR but in BAR, 4/ DABR register doesn't exist, instead we have registers LCTRL1, LCTRL2 and CMPx registers, 5/ The match on one comparator is not on a double word but on a single word. The patch does: 1/ Prepare the dedicated registers in call to __set_dabr(). In order to emulate the double word handling of BOOK3S, comparator E is set to DABR address value and comparator F to address + 4. Then breakpoint 1 is set to match comparator E or F, 2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx, 3/ Implement the exception. In that exception, the matched address is taken from SPRN_BAR and manage as if it was from SPRN_DAR. 4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That tlbie triggers the breakpoint exception when performed on the breakpoint address. For this reason, the routine returns if the match is from one of those two tlbie. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
2017-01-25powerpc/32: Enable HW_BREAKPOINT on BOOK3SChristophe Leroy
BOOK3S also has DABR register and capability to handle data breakpoints, so this patch enable it on all BOOK3S, not only 64 bits. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
2017-01-25powerpc/corenet: add support for the kmcent2 boardValentin Longchamp
This board is built around Freescale's T1040 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - parallel NOR Flash as boot medium - 1 PCIe bus (PCIe1 x1) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 4 IFC bus devices: - NOR flash - NAND flash - QRIO reset/power mgmt CPLD - BFTIC chassis management CPLD - 2 I2C buses - 1 SPI bus - HDLC bus with the QE's UCC1 - last but not least, the mandatory serial port The board can be used with the corenet32_smp_defconfig. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-01-25powerpc/85xx: remove the kmp204x_defconfigValentin Longchamp
It is not maintained and thus obsolete. corenet32_smp_defconfig can be used as reference for the kmcoge4/kmp204x boards. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-01-25powerpc/corenet: explicitly disable the SDHC controller on kmcoge4Valentin Longchamp
It is not implemented on the kmcoge4 hardware and if not disabled it leads to error messages with the corenet32_smp_defconfig. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-01-25powerpc/85xx: Enable display support for t1042rdbJason Jin
Add a diu_ops implementation for t1042rdb. Signed-off-by: Jason Jin <jason.jin@nxp.com> [Meng Yi: Made file t1042rdb-specific] Signed-off-by: Meng Yi <meng.yi@nxp.com> [scottwood: clean up commit message] Signed-off-by: Scott Wood <oss@buserror.net>
2017-01-25arm64: tegra: Use symbolic clock identifiersThierry Reding
Now that the corresponding device tree binding include has been merged, convert the DTS files to use symbolic names instead of numeric ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25arm64: tegra: Use symbolic HSP identifiersThierry Reding
Now that the corresponding device tree binding include has been merged, convert the DTS files to use symbolic names instead of numeric ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: paz00: Mark panel regulator as enabled on bootMarc Dietrich
Current U-Boot enables the display already. Marking the regulator as enabled on boot fixes sporadic panel initialization failures. Signed-off-by: Marc Dietrich <marvin24@gmx.de> Tested-by: Misha Komarovskiy <zombah@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: paz00: Fix __initdata placementDmitry Torokhov
Placement of attributes, such as __initdata, is standardized through the checkpatch script. Fix up this instance to make checkpatch happy. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25x86/fpu/xstate: Move XSAVES state init to a functionYu-cheng Yu
Make XSTATE init similar to existing code; move it to a separate function. There is no functionality change. Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi V. Shankar <ravi.v.shankar@intel.com> Cc: Rik van Riel <riel@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1485282346-15437-1-git-send-email-yu-cheng.yu@intel.com [ Minor cleanliness edits. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-01-25ARM: tegra: apalis-tk1: Update compatibility commentMarcel Ziswiler
Now with the new V1.1A HW card detect being implemented update resp. compatibility information. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: apalis-tk1: Fix SD card detect on v1.1 HWMarcel Ziswiler
Add SD card detect SD1_CD# applicable for V1.1 modules using GPIO_PV2. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: apalis-tk1: Adjust pin muxing for v1.1 HWMarcel Ziswiler
Configure Apalis MMC1 D6 GPIO on SDMMC3_CLK_LB_IN as reserved function without any pull-up/down. Configure GPIO_PV2 as SD1_CD# according to latest V1.1 HW. Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka not tristated and input driver enabled as well as it features some magic properties even though the external loopback is disabled and the internal loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM! This pin is now a not-connect on V1.1 HW in order to avoid any interference. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: apalis-tk1: Optional DisplayPort hot-plug detectMarcel Ziswiler
Configure DP_HPD_PFF0 pin as optional DisplayPort hot-plug detect. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: apalis-tk1: Pull-up temperature alertMarcel Ziswiler
Pull-up GPIO_PI6 connected to TMP451's ALERT#/THERM2#. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25powerpc: Fix build failure with clang due to BUILD_BUG_ON()Michael Ellerman
Anton says: In commit 4db7327194db ("powerpc: Add option to use jump label for cpu_has_feature()") and commit c12e6f24d413 ("powerpc: Add option to use jump label for mmu_has_feature()") we added: BUILD_BUG_ON(!__builtin_constant_p(feature)) to cpu_has_feature() and mmu_has_feature() in order to catch usage issues (such as cpu_has_feature(cpu_has_feature(X), which has happened once in the past). Unfortunately LLVM isn't smart enough to resolve this, and it errors out. I work around it in my clang/LLVM builds of the kernel, but I have just discovered that it causes a lot of issues for the bcc (eBPF) trace tool (which uses LLVM). For now just #ifdef it away for clang builds. Fixes: 4db7327194db ("powerpc: Add option to use jump label for cpu_has_feature()") Fixes: c12e6f24d413 ("powerpc: Add option to use jump label for mmu_has_feature()") Cc: stable@vger.kernel.org # v4.8+ Reported-by: Anton Blanchard <anton@samba.org> Tested-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/bpf: Flush the entire JIT bufferNaveen N. Rao
With bpf_jit_binary_alloc(), we allocate at a page granularity and fill the rest of the space with illegal instructions to mitigate BPF spraying attacks, while having the actual JIT'ed BPF program at a random location within the allocated space. Under this scenario, it would be better to flush the entire allocated buffer rather than just the part containing the actual program. We already flush the buffer from start to the end of the BPF program. Extend this to include the illegal instructions after the BPF program. Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Acked-by: Alexei Starovoitov <ast@kernel.org> Acked-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/bpf: Remove redundant check for non-null imageDaniel Borkmann
We have a check earlier to ensure we don't proceed if image is NULL. As such, the redundant check can be removed. Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> [Added similar changes for classic BPF JIT] Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Acked-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/mm: Return directly after a failed __copy_from_user() in ↵Markus Elfring
sys_subpage_prot() This function already has multiple exit points, so there's no harm adding another. Although it looks odd to return directly in a function which takes a lock, we've actually just dropped the mmap_sem in this code, so there's really no reason to go via a label. And it means we can drop the unhelpfully named out2 label. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> [mpe: Rewrite change log] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/sstep: Return directly after a failed address_ok() in emulate_step()Markus Elfring
Setting err and going to ldst_done just returns 0, without using err, so just return 0 directly. We already do that for other call sites in this function. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> [mpe: Rewrite change log] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/kernel: Fix unbalanced refcount on RTAS device nodeGavin Shan
The RTAS device-tree node's refcount has been increased by one in the function call of_find_node_by_name(), but it's missed to be decreased by one in the error path. It leads to unbalanced refcount on RTAS device-tree node. This fixes above issue by decreasing RTAS device-tree node's refcount in error path. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/kernel: Use of_property_read_u32() in rtas_initialize()Gavin Shan
This uses of_property_read_u32() in rtas_initialize() so that we needn't explicitly care the CPU's endian. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/kernel: Remove nested if statements in rtas_initialize()Gavin Shan
This removes the unnecessary nested if statements in function rtas_initialize(), to simplify the code. No functional changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/powernv/pci: Use kmalloc_array() in two functionsMarkus Elfring
Use kmalloc_array(), which checks for overflow of the multiplication, rather than doing it by hand. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/mm: Fixup wrong LPCR_VRMASD valueAneesh Kumar K.V
In commit a4b349540a26af ("powerpc/mm: Cleanup LPCR defines") we updated LPCR_VRMASD wrongly as below. -#define LPCR_VRMASD (0x1ful << (63-16)) +#define LPCR_VRMASD_SH 47 +#define LPCR_VRMASD (ASM_CONST(1) << LPCR_VRMASD_SH) We initialize the VRMA bits in LPCR to 0x00 in kvm. Hence using a different mask value as above while updating lpcr should not have any impact. This patch updates it to the correct value. Fixes: a4b349540a26 ("powerpc/mm: Cleanup LPCR defines") Reported-by: Ram Pai <linuxram@us.ibm.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Jia He <hejianet@gmail.com> Acked-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/64: Use optimized checksum routines on little-endianPaul Mackerras
Currently we have optimized hand-coded assembly checksum routines for big-endian 64-bit systems, but for little-endian we use the generic C routines. This modifies the optimized routines to work for little-endian. With this, we no longer need to enable CONFIG_GENERIC_CSUM. This also fixes a couple of comments in checksum_64.S so they accurately reflect what the associated instruction does. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> [mpe: Use the more common __BIG_ENDIAN__] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-01-25powerpc/64: Fix checksum folding in csum_tcpudp_nofold and ip_fast_csum_nofoldPaul Mackerras
These functions compute an IP checksum by computing a 64-bit sum and folding it to 32 bits (the "nofold" in their names refers to folding down to 16 bits). However, doing (u32) (s + (s >> 32)) is not sufficient to fold a 64-bit sum to 32 bits correctly. The addition can produce a carry out from bit 31, which needs to be added in to the sum to produce the correct result. To fix this, we copy the from64to32() function from lib/checksum.c and use that. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>