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2020-01-13arm64: dts: rockchip: fix dwmmc clock name for rk3308Johan Jonker
An experimental test with the command below gives this error: rk3308-evb.dt.yaml: dwmmc@ff480000: clock-names:2: 'ciu-drive' was expected 'ciu-drv' is not a valid dwmmc clock name, so fix this by changing it to 'ciu-drive'. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200110161200.22755-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-13arm64: dts: rockchip: fix dwmmc clock name for px30Johan Jonker
An experimental test with the command below gives this error: px30-evb.dt.yaml: dwmmc@ff390000: clock-names:2: 'ciu-drive' was expected 'ciu-drv' is not a valid dwmmc clock name, so fix this by changing it to 'ciu-drive'. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200110161200.22755-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-13x86/mce: Fix use of uninitialized MCE message stringJan H. Schönherr
The function mce_severity() is not required to update its msg argument. In fact, mce_severity_amd() does not, which makes mce_no_way_out() return uninitialized data, which may be used later for printing. Assuming that implementations of mce_severity() either always or never update the msg argument (which is currently the case), it is sufficient to initialize the temporary variable in mce_no_way_out(). While at it, avoid printing a useless "Unknown". Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200103150722.20313-4-jschoenh@amazon.de
2020-01-13x86/mce: Fix mce=nobootlogJan H. Schönherr
Since commit 8b38937b7ab5 ("x86/mce: Do not enter deferred errors into the generic pool twice") the mce=nobootlog option has become mostly ineffective (after being only slightly ineffective before), as the code is taking actions on MCEs left over from boot when they have a usable address. Move the check for MCP_DONTLOG a bit outward to make it effective again. Also, since commit 011d82611172 ("RAS: Add a Corrected Errors Collector") the two branches of the remaining "if" at the bottom of machine_check_poll() do same. Unify them. Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200103150722.20313-3-jschoenh@amazon.de
2020-01-13x86/mce: Take action on UCNA/Deferred errors againJan H. Schönherr
Commit fa92c5869426 ("x86, mce: Support memory error recovery for both UCNA and Deferred error in machine_check_poll") added handling of UCNA and Deferred errors by adding them to the ring for SRAO errors. Later, commit fd4cf79fcc4b ("x86/mce: Remove the MCE ring for Action Optional errors") switched storage from the SRAO ring to the unified pool that is still in use today. In order to only act on the intended errors, a filter for MCE_AO_SEVERITY is used -- effectively removing handling of UCNA/Deferred errors again. Extend the severity filter to include UCNA/Deferred errors again. Also, generalize the naming of the notifier from SRAO to UC to capture the extended scope. Note, that this change may cause a message like the following to appear, as the same address may be reported as SRAO and as UCNA: Memory failure: 0x5fe3284: already hardware poisoned Technically, this is a return to previous behavior. Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Tony Luck <tony.luck@intel.com> Link: https://lkml.kernel.org/r/20200103150722.20313-2-jschoenh@amazon.de
2020-01-13arm64: dts: allwinner: a64: enable DVFSVasily Khoruzhick
Add CPU regulator and operating points for all the A64-based boards that are currently supported to enable DVFS. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-13arm64: dts: allwinner: a64: add dtsi with CPU operating pointsVasily Khoruzhick
Add operating points for A64. These are taken from FEX file from BSP for A64. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-13arm64: dts: allwinner: a64: add cooling maps and thermal tripping pointsVasily Khoruzhick
Add cooling maps and thermal tripping points to prevent CPU overheating when running at the highest frequency. Tripping points are taken from A33 dts since A64 user manual doesn't mention when we should start throttling. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-13arm64: dts: allwinner: a64: add CPU clock to CPU0-3 nodesVasily Khoruzhick
Add CPU clock to the CPU nodes since it is a prerequisite for enabling DVFS. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> [wens@csie.org: Replace CLK_CPUX macro with raw number] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-01-13ARM: davinci: remove legacy timer supportBartosz Golaszewski
All platforms have now been switched to the new clocksource driver. Remove the old code and various no longer needed bits and pieces. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2020-01-13ARM: davinci: dm365: switch to using the clocksource driverBartosz Golaszewski
We now have a proper clocksource driver for davinci. Switch the dm365 platform to using it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2020-01-12Merge tag 'riscv/for-v5.5-rc6' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Paul Walmsley: "Two fixes for RISC-V: - Clear FP registers during boot when FP support is present, rather than when they aren't present - Move the header files associated with the SiFive L2 cache controller to drivers/soc (where the code was recently moved)" * tag 'riscv/for-v5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Fixup obvious bug for fp-regs reset riscv: move sifive_l2_cache.h to include/soc
2020-01-12ARM/net: ixp4xx: Pass ethernet physical base as resourceLinus Walleij
In order to probe this ethernet interface from the device tree all physical MMIO regions must be passed as resources. Begin this rewrite by first passing the port base address as a resource for all platforms using this driver, remap it in the driver and avoid using any reference of the statically mapped virtual address in the driver. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-01-12ixp4xx_eth: move platform_data definitionArnd Bergmann
The platform data is needed to compile the driver as standalone, so move it to a global location along with similar files. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-01-12ptp: ixp46x: move adjacent to ethernet driverArnd Bergmann
The ixp46x ptp driver has a somewhat unusual setup, where the ptp driver and the ethernet driver are in different directories but access the same registers that are defined a platform specific header file. Moving everything into drivers/net/ makes it look more like most other ptp drivers and allows compile-testing this driver on other targets. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-01-12wan: ixp4xx_hss: prepare compile testingArnd Bergmann
The ixp4xx_hss driver needs the platform data definition and the system clock rate to be compiled. Move both into a new platform_data header file. This is a prerequisite for compile testing, but turning on compile testing requires further patches to isolate the SoC headers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-01-12riscv: Fixup obvious bug for fp-regs resetGuo Ren
CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine ISA Register misa. Every bit:1 indicate a feature, so we should beqz reset_done when there is no F/D bit in csr_misa register. Signed-off-by: Guo Ren <ren_guo@c-sky.com> [paul.walmsley@sifive.com: fix typo in commit message] Fixes: 9e80635619b51 ("riscv: clear the instruction cache and all registers when booting") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2020-01-12riscv: move sifive_l2_cache.h to include/socYash Shah
The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") moves the sifive L2 cache driver to driver/soc. It did not move the header file along with the driver. Therefore this patch moves the header file to driver/soc Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: updated to fix the include guard] Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2020-01-12m68k: defconfig: Update defconfigs for v5.5-rc3Geert Uytterhoeven
- Enable modular build of new crypto algorithms: - CONFIG_CRYPTO_BLAKE2S=m, - CONFIG_CRYPTO_CURVE25519=m, - CONFIG_CRYPTO_LIB_BLAKE2S=m, - CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m, - CONFIG_CRYPTO_LIB_CURVE25519=m. - Remove CONFIG_CRYPTO_XXHASH=m (auto-selected by CONFIG_BTRFS_FS since commit 3951e7f050ac6a38 ("btrfs: add xxhash64 to checksumming algorithms"), - Move CONFIG_EARLY_PRINTK. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-12m68k: Wire up clone3() syscallKars de Jong
Wire up the clone3() syscall for m68k. The special entry point is done in assembler as was done for clone() as well. This is needed because all registers need to be saved. The C wrapper then calls the generic sys_clone3() with the correct arguments. Tested on A1200 using the simple test program from: https://lore.kernel.org/lkml/20190716130631.tohj4ub54md25dys@brauner.io/ Signed-off-by: Kars de Jong <jongk@linux-m68k.org> Link: https://lore.kernel.org/r/20191124195225.31230-1-jongk@linux-m68k.org Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-12sparc: Add .exit.data section.David S. Miller
This fixes build errors of all sorts. Also, emit .exit.text unconditionally. Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-12ARM: dts: imx: Add GW5912 board supportRobert Jones
The Gateworks GW5912 is an IMX6 SoC based single board computer with: - IMX6Q or IMX6DL - 32bit DDR3 DRAM - GbE RJ45 front-panel - 4x miniPCIe socket with PCI Gen2, USB2 - 1x miniPCIe socket with PCI Gen2, USB2, mSATA - 1x miniPCIe socket with PCI Gen2, USB2, mezzanine - 10V to 60V DC input barrel jack - 3axis accelerometer (lis2de12) - GPS (ublox ZOE-M8Q) - bi-color front-panel LED - 256MB NAND boot device - nanoSIM/microSD socket (with UHS-I support) - user pushbutton - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) - CAN Bus transceiver (mcp2562) - RS232 transceiver (1x UART with flow-control or 2x UART (build option) - off-board SPI connector (1x chip-select) Signed-off-by: Robert Jones <rjones@gateworks.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12ARM: dts: imx: Add GW5913 board supportRobert Jones
The Gateworks GW5913 is an IMX6 SoC based single board computer with: - IMX6Q or IMX6DL - 32bit DDR3 DRAM - FEC GbE RJ45 front-panel - 1x miniPCIe socket with PCI Gen2, USB2 - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM - 6V to 60V DC input connector - GPS (ublox ZOE-M8Q) - bi-color front-panel LED - 256MB NAND boot device - nanoSIM socket - user pushbutton - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) Signed-off-by: Robert Jones <rjones@gateworks.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12ARM: dts: imx: Add GW5910 board supportTim Harvey
The Gateworks GW5910 is an IMX6 SoC based single board computer with: - IMX6Q or IMX6DL - 32bit DDR3 DRAM - FEC GbE RJ45 front-panel - 1x miniPCIe socket with PCI Gen2, USB2 - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM - 5V to 60V DC input barrel jack - 3axis accelerometer (lis2de12) - GPS (ublox ZOE-M8Q) - bi-color front-panel LED - 256MB NAND boot device - microSD socket (with UHS-I support) - user pushbutton - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) - Dual-Band Wireless MCU (CC1352, UART/I2S interrconnect to IMX6) - WiFi/Bluetooth/BLE module (Sterling-LSW, SDIO/UART interconnect to IMX6) - RS232 transceiver (1x UART with flow-control or 2x UART (build option) - off-board SPI connector (1x chip-select) Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Robert Jones <rjones@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12ARM: dts: imx: Add GW5907 board supportRobert Jones
The Gateworks GW5907 is an IMX6 SoC based single board computer with: - IMX6Q or IMX6DL - 32bit DDR3 DRAM - FEC GbE Phy - bi-color front-panel LED - 256MB NAND boot device - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) - Digital IO expander (pca9555) - Joystick 12bit adc (ads1015) Signed-off-by: Robert Jones <rjones@gateworks.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12arm64: defconfig: Enable CONFIG_CLK_IMX8MP by defaultAnson Huang
Select CONFIG_CLK_IMX8MP by default to support i.MX8MP clock driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-11Merge tag 'clone3-tls-v5.5-rc6' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux Pull thread fixes from Christian Brauner: "This contains a series of patches to fix CLONE_SETTLS when used with clone3(). The clone3() syscall passes the tls argument through struct clone_args instead of a register. This means, all architectures that do not implement copy_thread_tls() but still support CLONE_SETTLS via copy_thread() expecting the tls to be located in a register argument based on clone() are currently unfortunately broken. Their tls value will be garbage. The patch series fixes this on all architectures that currently define __ARCH_WANT_SYS_CLONE3. It also adds a compile-time check to ensure that any architecture that enables clone3() in the future is forced to also implement copy_thread_tls(). My ultimate goal is to get rid of the copy_thread()/copy_thread_tls() split and just have copy_thread_tls() at some point in the not too distant future (Maybe even renaming copy_thread_tls() back to simply copy_thread() once the old function is ripped from all arches). This is dependent now on all arches supporting clone3(). While all relevant arches do that now there are still four missing: ia64, m68k, sh and sparc. They have the system call reserved, but not implemented. Once they all implement clone3() we can get rid of ARCH_WANT_SYS_CLONE3 and HAVE_COPY_THREAD_TLS. This series also includes a minor fix for the arm64 uapi headers which caused __NR_clone3 to be missing from the exported user headers. Unfortunately the series came in a little late especially given that it touches a range of architectures. Due to the holidays not all arch maintainers responded in time probably due to their backlog. Will and Arnd have thankfully acked the arm specific changes. Given that the changes are straightforward and rather minimal combined with the fact the that clone3() with CLONE_SETTLS is broken I decided to send them post rc3 nonetheless" * tag 'clone3-tls-v5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux: um: Implement copy_thread_tls clone3: ensure copy_thread_tls is implemented xtensa: Implement copy_thread_tls riscv: Implement copy_thread_tls parisc: Implement copy_thread_tls arm: Implement copy_thread_tls arm64: Implement copy_thread_tls arm64: Move __ARCH_WANT_SYS_CLONE3 definition to uapi headers
2020-01-11Merge tag 'samsung-dt-5.6' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.6 1. Couple ARM and wcore bus regulators on Exynos542x so higher frequencies could be used with dynamic voltage and frequency scaling. Enable this higher frequencies. 2. Correct the polarity of USB3503 hub GPIOs. 3. Adjust the bus frequencies (scaled with devfreq framework) on Exynos5422 Odroid boards to match values possible to obtain from root PLLs. 4. Add display to Tiny4412 board. 5. Cleanups and minor improvements. * tag 'samsung-dt-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Enable FIMD node and add proper panel node to Tiny4412 ARM: dts: samsung: Rename Samsung and Exynos to lowercase ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids ARM: dts: exynos: Move Exynos5420 bus related OPPs to the Odroid boards DTS ARM: dts: exynos: Correct USB3503 GPIOs polarity ARM: dts: exynos: Add missing CPU frequencies for Exynos5422/5800 ARM: dts: exynos: Add initial data for coupled regulators for Exynos5422/5800 ARM: dts: exynos: Remove syscon compatible from chipid node on Exynos5 Link: https://lore.kernel.org/r/20200110172334.4767-3-krzk@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-11x86/nmi: Remove irq_work from the long duration NMI handlerChangbin Du
First, printk() is NMI-context safe now since the safe printk() has been implemented and it already has an irq_work to make NMI-context safe. Second, this NMI irq_work actually does not work if a NMI handler causes panic by watchdog timeout. It has no chance to run in such case, while the safe printk() will flush its per-cpu buffers before panicking. While at it, repurpose the irq_work callback into a function which concentrates the NMI duration checking and makes the code easier to follow. [ bp: Massage. ] Signed-off-by: Changbin Du <changbin.du@gmail.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20200111125427.15662-1-changbin.du@gmail.com
2020-01-10Merge tag 'samsung-soc-5.6' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/soc Samsung mach/soc changes for v5.6 Cleanups (Samsung and Exynos names, Kconfig help text correction). * tag 'samsung-soc-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: samsung: Rename Samsung and Exynos to lowercase ARM: exynos: Correct the help text for platform Kconfig option Link: https://lore.kernel.org/r/20200110172334.4767-4-krzk@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'v5.6-rockchip-dts64-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt New boards are the Radxa Rock Pi N10 using the VMARC SOM and Dalang carrier board, separate versions for the two rockpro64 hardware revisions which switched a pin between revisions. The rockpro64 also got bluetooth support now. The px30 got a lot of attention with dsi, gpu and thermal support. Similarly the rk3399-roc-pc board also got attention with mtd flash, sdr104 mode, hdmi sound, gpu and a lot of other smaller improvements. Other than that there is a new gpu-cooling device for rk3399 a cpu idle-state for rk3328 and more small improvements across a number of boards. * tag 'v5.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (37 commits) arm64: dts: rockchip: Enable mp8859 regulator on rk3399-roc-pc arm64: dts: rockchip: rk3399-hugsun-x99: remove supports-sd and supports-emmc options arm64: dts: rockchip: rk3399-firefly: remove num-slots from &sdio0 node arm64: dts: rockchip: Add PX30 LVDS arm64: dts: rockchip: add dsi controller for px30 arm64: dts: rockchip: Add PX30 DSI DPHY arm64: dts: rockchip: Add RK3328 idle state arm64: dts: rockchip: remove identical &uart0 node from rk3368-lion-haikou arm64: dts: rockchip: Add Radxa Rock Pi N10 initial support ARM: dts: rockchip: Add Radxa Dalang Carrier board arm64: dts: rockchip: Add VMARC RK3399Pro SOM initial support dt-bindings: arm: rockchip: Add Rock Pi N10 binding arm64: dts: rockchip: hook up bluetooth at uart0 on rockpro64 arm64: dts: rockchip: enable wifi module at sdio0 on rockpro64 arm64: dts: rockchip: split rk3399-rockpro64 for v2 and v2.1 boards arm64: dts: rockchip: enable the gpu on px30-evb arm64: dts: rockchip: add the gpu for px30 dt-bindings: gpu: mali-bifrost: Add Rockchip PX30 arm64: dts: rockchip: Add GPU cooling device for RK3399 arm64: dts: rockchip: Add regulators for PCIe for Radxa Rock Pi 4 board ... Link: https://lore.kernel.org/r/5115625.yBEeHQkg2z@phil Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'v5.6-rockchip-dts32-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt Pin-name corrections for Veyron-Fievel, bluetooth for a number of veyron boards and additional operating points for rk3288-tinker. * tag 'v5.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Use ABI name for recovery mode pin on veyron fievel/tiger ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tiger ARM: dts: rockchip: Add missing cpu operating points for rk3288-tinker ARM: dts: rockchip: Add brcm bluetooth for rk3288-veyron Link: https://lore.kernel.org/r/8215452.dU6eVM2tAM@phil Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'amlogic-defconfig' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/defconfig arm64: defconfig updates for v5.6 - enable FUSB302 as module * tag 'amlogic-defconfig' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: defconfig: enable FUSB302 as module Link: https://lore.kernel.org/r/7hftgoeaad.fsf@baylibre.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10ARM: multi_v7_defconfig: enable STM32 PWR regulatorAmelie Delaunay
This enables the driver for STM32 PWR regulators found on stm32mp1. Link: https://lore.kernel.org/r/20200109125531.13610-1-alexandre.torgue@st.com Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'stm32-dt-for-v5.6-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT updates for v5.6, round 1 Highlights: ---------- MPU part: -Add PWM support on DK2 board. -Add counter support to STM32 timers. -Add support of SDMMC 2&3 instances based on "arm,pl18x". SDMMC2 is connected to eMMC on ED1 board. SDMMC3 is connected to the GPIO extension connector on EV1 & DKx boards. -Add ADC support on ED1 board. -Update devicetree files split to better fit to STM32MP15 SOC & boards diversity. -Fix issues seen during YAML validation. -Enable Ethernet (MAC) TX clock gating during low-power mode. -Enable USB OTG HS support on DKx boards. -Enable USB Host EHCI on DKx boards. MCU part: -Fix issues seen during YAML validation. * tag 'stm32-dt-for-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (37 commits) ARM: dts: stm32: Add power-supply for RGB panel on stm32429i-eval ARM: dts: stm32: Add power-supply for DSI panel on stm32f469-disco ARM: dts: stm32: change nvmem node name on stm32mp1 ARM: dts: stm32: change nvmem node name on stm32f429 ARM: dts: stm32: update mlahb node according to the bindings on stm32mp15 ARM: dts: stm32: fix dma controller node name on stm32mp157c ARM: dts: stm32: fix dma controller node name on stm32f743 ARM: dts: stm32: fix dma controller node name on stm32f746 ARM: dts: stm32: add phy-names to usbotg_hs on stm32mp157c-ev1 ARM: dts: stm32: enable USB OTG HS on stm32mp15 DKx boards ARM: dts: stm32: enable USB Host (USBH) EHCI controller on stm32mp15 DKx ARM: dts: stm32: enable USBPHYC on stm32mp15 DKx boards ARM: dts: stm32: remove useless clock-names from RTC node on stm32f746 ARM: dts: stm32: remove useless clock-names from RTC node on stm32f429 ARM: dts: stm32: Enable MAC TX clock gating during TX low-power mode on stm32mp15 ARM: dts: stm32: adjust slew rate for Ethernet on stm32mp15 ARM: dts: stm32: remove syscfg clock on stm32mp15 ethernet ARM: dts: stm32: remove "@" and "_" from stm32f7 pinmux groups ARM: dts: stm32: remove "@" and "_" from stm32f4 pinmux groups ARM: dts: stm32: Adapt STM32MP157C ED1 board to STM32 DT diversity ... Link: https://lore.kernel.org/r/39df1dee-3c9f-cd35-bc55-a71223e07100@st.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'hisi-arm64-dt-for-5.6' of git://github.com/hisilicon/linux-hisi ↵Olof Johansson
into arm/dt ARM64: DT: Hisilicon SoCs DT updates for 5.6 - Add remote control map name of the IR device for the hi3798cv200 poplar board - Correct the PCIe bus range setting for the hi3798cv200 * tag 'hisi-arm64-dt-for-5.6' of git://github.com/hisilicon/linux-hisi: arm64: dts: hi3798cv200: correct PCIe 'bus-range' setting arm64: dts: hi3798cv200-poplar: add linux,rc-map-name for IR Link: https://lore.kernel.org/r/5E169EDE.8020809@hisilicon.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'arm-soc/for-5.6/soc' of https://github.com/Broadcom/stblinux into ↵Olof Johansson
arm/soc This pull request contains Broadcom ARM-based SoCs Kconfig/machine changes for 5.6, please pull the following: - Justin adds an entry for BCM7216's debug UART to support DEBUG_LL - Florian adds a select ARM_AMBA to support the ARM PL011 UART/console which is required on BCM7211 * tag 'arm-soc/for-5.6/soc' of https://github.com/Broadcom/stblinux: ARM: bcm: Select ARM_AMBA for ARCH_BRCMSTB ARM: brcmstb: Add debug UART entry for 7216 Link: https://lore.kernel.org/r/20200108191114.15987-3-f.fainelli@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'arm-soc/for-5.6/devicetree' of ↵Olof Johansson
https://github.com/Broadcom/stblinux into arm/dt This pull request contains Broadcom ARM-based SoCs Device Tree changes for 5.6, please pull the following: - Stephan adds support for the HWRNG on 2711 (Raspberry Pi 4) which is different than the previous Pi chips - Florian switches the BCM956265HR board to use the hardware I2C controllers for interfacing with the SFPs * tag 'arm-soc/for-5.6/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: bcm2711: Enable HWRNG support ARM: dts: bcm2835: Move rng definition to common location ARM: dts: NSP: Use hardware I2C for BCM958625HR Link: https://lore.kernel.org/r/20200108191114.15987-1-f.fainelli@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'v5.5-rockchip-dtsfixes' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes A fix for the Beelink A1 IR receiver setting the correct polarity. * tag 'v5.5-rockchip-dtsfixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Fix IR on Beelink A1 Link: https://lore.kernel.org/r/2054603.JKFSmqfO19@phil Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'sunxi-fixes-for-5.5' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes A couple of fixes for GPIO polarity and regulators on the A64 olinuxino. * tag 'sunxi-fixes-for-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: dts: sun8i: a83t: Correct USB3503 GPIOs polarity arm64: dts: allwinner: a64: olinuxino: Fix SDIO supply regulator arm64: dts: allwinner: a64: olinuxino: Fix eMMC supply regulator Link: https://lore.kernel.org/r/582f4fda-38af-43e8-af58-957aee5b9dd8.lettre@localhost Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'imx-fixes-5.5-2' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 5.5, round 2: - Fix i.MX8MM SDMA1 AHB clock setting to remove a "Timeout waiting for CH0" error seen with UART1. - Correct compatible of RV3029 RTC device on imx6q-dhcom board. - Correct interrupt trigger type for magnetometer on board imx8mq-librem5-devkit. - A series from Anson Huang to fix vdd3p0 power supplier for a few NXP development board. - Fix imx6q-icore-mipi board to use 1.5 version of i.Core MX6DL, so that Ethernet interface on the board works properly. - Fix Toradex Colibri board to get NAND flash support back. - Fix SGTL5000 VDDIO regulator connection for imx6q-dhcom, which is connected to PMIC SW2 output rather than a fixed 3V3 rail. - Fix 'reg' of CPU node on imx7ulp to get rid of a warning given by kernel. - Fix endian setting for DCFG on LS1028A SoC, so that register access of DCFG becomes correct. * tag 'imx-fixes-5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx7: Fix Toradex Colibri iMX7S 256MB NAND flash support ARM: dts: imx6sll-evk: Remove incorrect power supply assignment ARM: dts: imx6sl-evk: Remove incorrect power supply assignment ARM: dts: imx6sx-sdb: Remove incorrect power supply assignment ARM: dts: imx6qdl-sabresd: Remove incorrect power supply assignment ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL arm64: dts: imx8mq-librem5-devkit: use correct interrupt for the magnetometer ARM: dts: imx6q-dhcom: Fix SGTL5000 VDDIO regulator connection ARM: dts: imx7ulp: fix reg of cpu node arm64: dts: imx8mm: Change SDMA1 ahb clock for imx8mm arm64: dts: ls1028a: fix endian setting for dcfg ARM: dts: imx6q-dhcom: fix rtc compatible Link: https://lore.kernel.org/r/20200110011836.GW4456@T480 Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'amlogic-fixes' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/fixes arm-soc: Amlogic fixes for v5.5-rc * tag 'amlogic-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson-sm1-sei610: add gpio bluetooth interrupt dt-bindings: reset: meson8b: fix duplicate reset IDs soc: amlogic: meson-ee-pwrc: propagate errors from pm_genpd_init() soc: amlogic: meson-ee-pwrc: propagate PD provider registration errors ARM: dts: meson8: fix the size of the PMU registers arm64: dts: meson-sm1-sei610: gpio-keys: switch to IRQs Link: https://lore.kernel.org/r/7hmuaweavi.fsf@baylibre.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10ARM: at91: pm: use of_device_id array to find the proper shdwc nodeClaudiu Beznea
Use of_device_id array to find the proper shdwc compatibile node. SAM9X60's shdwc changes were not integrated when commit eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60") was integrated. Fixes: eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1576062248-18514-3-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-01-10ARM: at91: pm: use SAM9X60 PMC's compatibleClaudiu Beznea
SAM9X60 PMC's has a different PMC. It was not integrated at the moment commit 01c7031cfa73 ("ARM: at91: pm: initial PM support for SAM9X60") was published. Fixes: 01c7031cfa73 ("ARM: at91: pm: initial PM support for SAM9X60") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1576062248-18514-2-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-01-10ARM: configs: at91: enable config flags for sam9x60 SoCClaudiu Beznea
Enable config flags for SAM9X60 SoC. This includes SoC flag (CONFIG_SOC_SAM9X60) and IP/board specific flags as follows: - atmel maxtouch - flexcom - XDMA - I2S Multi-channel - mikroelectronica proto board - SAMA5D2's ADC - atmel QSPI - classd Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-10-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-01-10ARM: configs: at91: use savedefconfigClaudiu Beznea
Use savedefconfig. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-9-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-01-10MIPS: Loongson: Fix potential NULL dereference in loongson3_platform_init()Tiezhu Yang
If kzalloc fails, it should return -ENOMEM, otherwise may trigger a NULL pointer dereference. Fixes: 3adeb2566b9b ("MIPS: Loongson: Improve LEFI firmware interface") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2020-01-10MIPS: BPF: Use sizeof_field() instead of FIELD_SIZEOF()Kees Cook
The FIELD_SIZEOF() macro was redundant, and is being removed from the kernel. Since commit c593642c8be0 ("treewide: Use sizeof_field() macro") this is one of the last users of the old macro, so replace it. Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@vger.kernel.org
2020-01-10MIPS: use resource_sizeJulia Lawall
Use resource_size rather than a verbose computation on the end and start fields. The semantic patch that makes these changes is as follows: (http://coccinelle.lip6.fr/) <smpl> @@ struct resource ptr; @@ - (ptr.end - ptr.start + 1) + resource_size(&ptr) </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: kernel-janitors@vger.kernel.org Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2020-01-10efi: Allow disabling PCI busmastering on bridges during bootMatthew Garrett
Add an option to disable the busmaster bit in the control register on all PCI bridges before calling ExitBootServices() and passing control to the runtime kernel. System firmware may configure the IOMMU to prevent malicious PCI devices from being able to attack the OS via DMA. However, since firmware can't guarantee that the OS is IOMMU-aware, it will tear down IOMMU configuration when ExitBootServices() is called. This leaves a window between where a hostile device could still cause damage before Linux configures the IOMMU again. If CONFIG_EFI_DISABLE_PCI_DMA is enabled or "efi=disable_early_pci_dma" is passed on the command line, the EFI stub will clear the busmaster bit on all PCI bridges before ExitBootServices() is called. This will prevent any malicious PCI devices from being able to perform DMA until the kernel reenables busmastering after configuring the IOMMU. This option may cause failures with some poorly behaved hardware and should not be enabled without testing. The kernel commandline options "efi=disable_early_pci_dma" or "efi=no_disable_early_pci_dma" may be used to override the default. Note that PCI devices downstream from PCI bridges are disconnected from their drivers first, using the UEFI driver model API, so that DMA can be disabled safely at the bridge level. [ardb: disconnect PCI I/O handles first, as suggested by Arvind] Co-developed-by: Matthew Garrett <mjg59@google.com> Signed-off-by: Matthew Garrett <mjg59@google.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Arvind Sankar <nivedita@alum.mit.edu> Cc: Matthew Garrett <matthewgarrett@google.com> Cc: linux-efi@vger.kernel.org Link: https://lkml.kernel.org/r/20200103113953.9571-18-ardb@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-22 15:35:20 +0000