summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2025-07-21stackleak: Rename STACKLEAK to KSTACK_ERASEKees Cook
In preparation for adding Clang sanitizer coverage stack depth tracking that can support stack depth callbacks: - Add the new top-level CONFIG_KSTACK_ERASE option which will be implemented either with the stackleak GCC plugin, or with the Clang stack depth callback support. - Rename CONFIG_GCC_PLUGIN_STACKLEAK as needed to CONFIG_KSTACK_ERASE, but keep it for anything specific to the GCC plugin itself. - Rename all exposed "STACKLEAK" names and files to "KSTACK_ERASE" (named for what it does rather than what it protects against), but leave as many of the internals alone as possible to avoid even more churn. While here, also split "prev_lowest_stack" into CONFIG_KSTACK_ERASE_METRICS, since that's the only place it is referenced from. Suggested-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20250717232519.2984886-1-kees@kernel.org Signed-off-by: Kees Cook <kees@kernel.org>
2025-07-21KVM: arm64: Make RAS registers UNDEF when RAS isn't advertisedMarc Zyngier
We currently always expose FEAT_RAS when available on the host. As we are about to make this feature selectable from userspace, check for it being present before emulating register accesses as RAZ/WI, and inject an UNDEF otherwise. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250721101955.535159-4-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2025-07-21KVM: arm64: Filter out HCR_EL2 bits when running in hypervisor contextMarc Zyngier
Most HCR_EL2 bits are not supposed to affect EL2 at all, but only the guest. However, we gladly merge these bits with the host's HCR_EL2 configuration, irrespective of entering L1 or L2. This leads to some funky behaviour, such as L1 trying to inject a virtual SError for L2, and getting a taste of its own medecine. Not quite what the architecture anticipated. In the end, the only bits that matter are those we have defined as invariants, either because we've made them RESx (E2H, HCD...), or that we actively refuse to merge because the mess with KVM's own logic. Use the sanitisation infrastructure to get the RES1 bits, and let things rip in a safer way. Fixes: 04ab519bb86df ("KVM: arm64: nv: Configure HCR_EL2 for FEAT_NV2") Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250721101955.535159-3-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2025-07-21KVM: arm64: Check for SYSREGS_ON_CPU before accessing the CPU stateMarc Zyngier
Mark Brown reports that since we commit to making exceptions visible without the vcpu being loaded, the external abort selftest fails. Upon investigation, it turns out that the code that makes registers affected by an exception visible to the guest is completely broken on VHE, as we don't check whether the system registers are loaded on the CPU at this point. We managed to get away with this so far, but that's obviously as bad as it gets, Add the required checksm and document the absolute need to check for the SYSREGS_ON_CPU flag before calling into any of the __vcpu_write_sys_reg_to_cpu()__vcpu_read_sys_reg_from_cpu() helpers. Reported-by: Mark Brown <broonie@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/18535df8-e647-4643-af9a-bb780af03a70@sirena.org.uk Link: https://lore.kernel.org/r/20250720102229.179114-1-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2025-07-21Merge tag 'samsung-defconfig-6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/defconfig Samsung SoC defconfig changes for v6.17 1. Multiple SoCs (including Samsung, Apple): switch sound to module from a built-in, because it is not necessary for booting. Also drop redundant sound codec options. 2. Enable PMIC drivers for Google GS101 Pixel 6 phones: MAX77759 and Samsung PMIC over ACPM protocol. * tag 'samsung-defconfig-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: defconfig: enable Samsung PMIC over ACPM arm64: defconfig: enable Maxim max77759 driver arm64: defconfig: Drop unneeded unselectable sound drivers arm64: defconfig: Switch SOUND to module Link: https://lore.kernel.org/r/20250709191523.171359-4-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21arm64: dts: apple: Add Apple SoC GPUSasha Finkelstein
Add device tree entries for GPUs in M-series SoCs Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Sven Peter <sven@kernel.org> Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com> Link: https://lore.kernel.org/r/20250710-sgx-dt-v3-2-299bb3a65109@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2025-07-21arm64: dts: apple: t8012-j132: Include touchbar framebuffer nodeNick Chan
Apple T2 MacBookPro15,2 (j132) has a touchbar so include the framebuffer node. Cc: stable@vger.kernel.org Fixes: 4efbcb623e9bc ("arm64: dts: apple: Add T2 devices") Signed-off-by: Nick Chan <towinchenmi@gmail.com> Link: https://lore.kernel.org/stable/20250620-j132-fb-v1-1-bc6937baf0b9%40gmail.com Link: https://lore.kernel.org/r/20250620-j132-fb-v2-1-65f100182085@gmail.com Signed-off-by: Sven Peter <sven@kernel.org>
2025-07-21arm64: dts: apple: Add bit offset to PMIC NVMEM node namesSven Peter
Now that the dt-binding has been extended to allow indicating the bit position the following warning about a duplicate unit address with W=1 can be fixed: arch/arm64/boot/dts/apple/t8103.dtsi:764.46-767.8: Warning (unique_unit_address_if_enabled): /soc/spmi@23d0d9300/pmic@f/nvmem-layout/boot-error-count@9f02: duplicate unit-address (also used in node /soc/spmi@23d0d9300/pmic@f/nvmem-layout/panic-count@9f02) Fixes: d8bf82081c9e ("arm64: dts: apple: Add PMIC NVMEM") Link: https://lore.kernel.org/r/20250610-nvmem-bit-pattern-v1-2-55ed5c1b369c@kernel.org Signed-off-by: Sven Peter <sven@kernel.org>
2025-07-21Merge branch 'newsoc/cix-p1' into soc/newsocArnd Bergmann
Patches from Peter Chen <peter.chen@cixtech.com>: Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC. Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief introduction for SoC and related boards at: https://radxa.com/products/orion/o6#overview Currently, to run upstream kernel at Orion O6 board, you need to use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs. https://docs.radxa.com/en/orion/o6/bios/install-bios In this series, we add initial SoC and board support for Kernel building. Since mailbox is used for SCMI clock communication, mailbox driver is added in this series for the minimum SoC support. Patch 1-2: add dt-binding doc for CIX and its sky1 SoC Patch 3: add Arm64 build support Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol. Patch 6: add Arm64 defconfig support Patch 7-8: add initial dts support for SoC and Orion O6 board Patch 9: add MAINTAINERS entry * newsoc/cix-p1: MAINTAINERS: Add CIX SoC maintainer entry arm64: dts: cix: Add sky1 base dts initial support dt-bindings: clock: cix: Add CIX sky1 scmi clock id arm64: defconfig: Enable CIX SoC mailbox: add CIX mailbox driver dt-bindings: mailbox: add cix,sky1-mbox arm64: Kconfig: add ARCH_CIX for cix silicons dt-bindings: arm: add CIX P1 (SKY1) SoC dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21arm64: dts: cix: Add sky1 base dts initial supportPeter Chen
CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech, and Orion O6 is the motherboard launched by Radxa. See below for detail: https://docs.radxa.com/en/orion/o6/getting-started/introduction In this commit, it only adds limited components for running initramfs at Orion O6. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Enric Balletbo i Serra <eballetb@redhat.com> Tested-by: Kajetan Puchalski <kajetan.puchalski@arm.com> Signed-off-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com> Signed-off-by: Gary Yang <gary.yang@cixtech.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21arm64: defconfig: Enable CIX SoCPeter Chen
- Enable CIX SoC support at ARM64 defconfig - Enable CIX mailbox At CIX SoC platforms, the clock handling uses Arm SCMI protocol, the physical clock access is at sub processor, so it needs to enable mailbox by default. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21arm64: Kconfig: add ARCH_CIX for cix siliconsFugang Duan
Add ARCH_CIX for CIX SoC series support. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Fugang Duan <fugang.duan@cixtech.com> Signed-off-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge branch 'newsoc/andes' into soc/newsocArnd Bergmann
Patches from Ben Zong-You Xie <ben717@andestech.com>: The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including Andes QiLai SoC. This patch series adds minimal device tree files for the QiLai SoC and the Voyager board [1]. Now only support basic uart drivers to boot up into a basic console. Other features will be added later. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ [2] https://lore.kernel.org/all/20250602060747.689824-1-ben717@andestech.com/ * newsoc/andes: MAINTAINERS: Add entry for Andes SoC riscv: defconfig: enable Andes SoC riscv: dts: andes: add Voyager board device tree riscv: dts: andes: add QiLai SoC device tree dt-bindings: timer: add Andes machine timer dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller dt-bindings: interrupt-controller: add Andes QiLai PLIC dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings riscv: add Andes SoC family Kconfig support
2025-07-21Merge tag 'mtk-dts64-for-v6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt MediaTek ARM64 DeviceTree updates for v6.17 This adds new machines and improves support for already supported MediaTek SoCs. In particular: - New machine: MT8186 Steelix Squirtle Chromebook - Steelix-Voltorb's two dts are merged in one ...and improvements for already supported SoCs and machines: - Added reserved memory for AFE DMA for MT8173/83/86/92, aligning audio related memory allocation between all of the Chromebook SoCs - Added second source components for Steelix, and marked the multiple trackpads for Asurada as such - MediaTek Genio 1200: Enabled support for the Audio DSP and sound - MediaTek Genio 510/700/1200: Added support for the PMIC Keys - MediaTek MT7988: Added Cache Coherent Interconnect for CPU DVFS - MT7988A-BananaPi-R4: Enabled CCI, added GPIO LEDs - Airoha EN7581: Added ethernet nodes to Evaluation Board * tag 'mtk-dts64-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: arm64: dts: mediatek: mt8395-genio-1200-evk: Add MT6359 PMIC key support arm64: dts: mediatek: mt8390-genio-common: Add Home MT6359 PMIC key support arm64: dts: mediatek: mt7988a-bpi-r4: add gpio leds arm64: dts: mediatek: mt7988a-bpi-r4: drop unused pins arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci arm64: dts: mediatek: mt7988: add cci node dt-bindings: interconnect: add mt7988-cci compatible arm64: dts: airoha: en7581: Add ethernet nodes to EN7581 SoC evaluation board arm64: dts: mediatek: mt8192-asurada-spherion: Mark trackpads as fail-needs-probe arm64: dts: mediatek: mt8186: Add Squirtle Chromebooks arm64: dts: mediatek: mt8186: Merge Voltorb device trees arm64: dts: mediatek: mt8186-steelix: Mark second source components for probing dt-bindings: arm: mediatek: Add MT8186 Squirtle Chromebooks dt-bindings: arm: mediatek: Merge MT8186 Voltorb entries arm64: dts: mediatek: mt8395-genio-1200-evk: Enable Audio DSP and sound card arm64: dts: mediatek: mt8192-asurada: Reserve memory for audio frontend arm64: dts: mediatek: mt8186-corsola: Reserve memory for audio frontend arm64: dts: mediatek: mt8183-kukui: Reserve memory for audio frontend arm64: dts: mediatek: mt8173: Reserve memory for audio frontend Link: https://lore.kernel.org/r/20250711083656.33538-3-angelogioacchino.delregno@collabora.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'mtk-dts32-for-v6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt MediaTek mach ARM32 updates This adds support for the MediaTek MT6572 SoC, found in various old smartphones and tablets from various manufacturers. In particular, this adds a board_dt_compat entry for this SoC and its SMP bring up sequence to enable secondary cores. * tag 'mtk-dts32-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: ARM: dts: mediatek: add basic support for Lenovo A369i board ARM: dts: mediatek: add basic support for JTY D101 board ARM: dts: mediatek: add basic support for MT6572 SoC dt-bindings: arm: mediatek: add boards based on the MT6572 SoC dt-bindings: vendor-prefixes: add JTY dt-bindings: watchdog: mediatek,mtk-wdt: add MT6572 dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: add MT6572 Link: https://lore.kernel.org/r/20250711083656.33538-2-angelogioacchino.delregno@collabora.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'omap-for-v6.17/dt-signed' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt arm: dts: OMAP updates for v6.17 - new board support: Seeed BeagleBone Green Eco - misc. fixups / cleanups * tag 'omap-for-v6.17/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap: arm: dts: ti: omap: Fixup pinheader typo ARM: dts: am335x-pdu001: Fix RS-485 transceiver switching arm: dts: omap: Add support for BeagleBone Green Eco board dt-bindings: omap: Add Seeed BeagleBone Green Eco arm: dts: omap: am335x-bone-common: Rename tps to generic pmic node Revert "ARM: dts: Update pcie ranges for dra7" ARM: dts: omap: am335x: Use non-deprecated rts-gpios Link: https://lore.kernel.org/r/7h7c0gxczy.fsf@baylibre.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'stm32-dt-for-v6.17-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.17, round 1 Highlights: ---------- - MPU: - STM32MP13: -Add Ethernet MAC adress efuse support. - STMP32MP15: - Add stm32mp157f-DK2 board support. This board embedds the same conectivity devices, DDR ... than stm32mp157c-dk2. However there are two differences: STM32MP157F SoC which allows overdrive OPP and the SCMI support for system features like clocks and regulators. - STM32MP25: - Fix tick timer for low power use cases. - Add timer support. * tag 'stm32-dt-for-v6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: arm64: dts: st: remove empty line in stm32mp251.dtsi arm64: dts: st: fix timer used for ticks arm64: defconfig: Enable STM32 Octo Memory Manager and OcstoSPI driver ARM: dts: stm32: add stm32mp157f-dk2 board support dt-bindings: arm: stm32: add STM32MP157F-DK2 board compatible ARM: dts: stm32: optee async notif interrupt for MP15 scmi variants ARM: dts: stm32: use internal regulators bindings for MP15 scmi variants dt-bindings: regulator: Add STM32MP15 SCMI regulator identifiers ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkx ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCs ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkx arm64: defconfig: enable STM32 timers drivers arm64: dts: st: add timer nodes on stm32mp257f-ev1 arm64: dts: st: add timer pins for stm32mp257f-ev1 arm64: dts: st: add timer nodes on stm32mp251 ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addresses Link: https://lore.kernel.org/r/b3e3363b-1ea5-457c-b244-2cbe26f7d6e4@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'v6.17-rockchip-dts64-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards: ROC-RK3588S-PC, Luckfox Omni3576, Radxa Rock 5T, Sakura Pi RK3308B - all of them have the used soc in their name. New overlays: RockPro64 screen, optional Sige5 Wifi/BT module, ethernet-switch addon for Jaguar. Added peripherals on rk3528 (spi, power-domain controller, gpu) and sdio controller on rk3576. DSI display support for the Gameforce-ACE handheld, a fix for the cover-detection (closed/open) on the PineNote, camera support for the Haikou Video Demo overlay on PX30 Ringneck as well as a number of other newly enabled peripherals on a number of boards. * tag 'v6.17-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (40 commits) arm64: dts: rockchip: Enable eMMC HS200 mode on Radxa E20C arm64: dts: rockchip: Add bluetooth support to ArmSoM Sige7 arm64: dts: rockchip: enable PCIe on ROCK 4D arm64: dts: rockchip: Enable HDMI receiver on CM3588 arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576 arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576 arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PC dt-bindings: arm: rockchip: Add Firefly ROC-RK3588S-PC arm64: dts: rockchip: Enable GPU on Radxa E20C arm64: dts: rockchip: Add GPU node for RK3528 arm64: dts: rockchip: support camera module on Haikou Video Demo on PX30 Ringneck arm64: dts: rockchip: add label to first port of ISP on px30 arm64: dts: rockchip: fix endpoint dtc warning for PX30 ISP arm64: dts: rockchip: Add power controller for RK3528 arm64: dts: rockchip: enable USB on Sige5 arm64: dts: rockchip: add overlay for the WiFi/BT module on Sige5 v1.2 arm64: dts: rockchip: add version-independent WiFi/BT nodes on Sige5 arm64: dts: rockchip: add SDIO controller on RK3576 arm64: dts: rockchip: Enable gpu on rk3576-evb1-v10 arm64: dts: rockchip: Update the PinePhone Pro panel description ... Link: https://lore.kernel.org/r/15465458.uLZWGnKmhe@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21arm64: dts: nuvoton: npcm8xx: Drop the GIC "ppi-partitions" nodeRob Herring (Arm)
The Arm GIC "ppi-partitions" node is only relevant to GICv3 and makes no sense for GICv2 implementations which the GIC-400 is. PPIs in GICv2 have no CPU affinity. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250609203721.2852879-1-robh@kernel.org Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/r/20250710-nuvoton-arm64-dt-v1-1-ec7db96ea507@codeconstruct.com.au Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'aspeed-6.17-devicetree-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt ASPEED devicetree updates for 6.17 Removed platforms: - IBM's Swift BMC New platforms: - Meta's Santabarbara Santabarbara is a compute node with an accelerator module - NVIDIA's GB200NVL BMC NVIDIA GB200 NVL72 connects 36 Grace CPUs and 72 Blackwell GPUs in an NVIDIA NVLink-connected, liquid-cooled, rack-scale design. Updated BMC platforms: - Bletchley (Meta): GPIO hog names, remove ethernet-phy node, USB PD negotiation - Catalina (Meta): Various sensors added, MCTP support for NIC management - Harma (Meta): Various sensors added - System1 (IBM): IPMB and various GPIO-related updates - Yosemite4 (Meta): GPIO names for UART mux select lines The System1 series includes a devicetree binding patch for IPMI IPMB devices. * tag 'aspeed-6.17-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux: (34 commits) ARM: dts: aspeed: yosemite4: add gpio name for uart mux sel ARM: dts: aspeed: santabarbara: Add Meta Santabarbara BMC dt-bindings: arm: aspeed: add Meta Santabarbara board ARM: dts: aspeed: bletchley: enable USB PD negotiation ARM: dts: aspeed: lanyang: Fix 'lable' typo in LED nodes ARM: dts: aspeed: harma: add mmc health ARM: dts: aspeed: Harma: revise gpio bride pin for battery ARM: dts: aspeed: harma: add ADC128D818 for voltage monitoring ARM: dts: aspeed: harma: add fan board I/O expander ARM: dts: aspeed: harma: add E1.S power monitor ARM: dts: aspeed: catalina: Enable MCTP for frontend NIC management ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC dt-bindings: arm: aspeed: add Nvidia's GB200NVL BMC ARM: dts: aspeed: catalina: Enable MCTP support for NIC management ARM: dts: aspeed: catalina: Update CBC FRU EEPROM I2C bus and address ARM: dts: aspeed: catalina: Enable multi-master on additional I2C buses ARM: dts: aspeed: catalina: Remove INA238 and INA230 nodes ARM: dts: aspeed: catalina: Add second source HSC node support ARM: dts: aspeed: catalina: Add second source fan controller support ARM: dts: aspeed: catalina: Add fan controller support ... Link: https://lore.kernel.org/r/36d50489cac1fbae01ec699b742f6c6c459a01cb.camel@codeconstruct.com.au Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'renesas-dts-for-v6.17-tag2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.17 (take two) - Add support for the Renesas Gray Hawk Single board with R-Car V4M-7 (R8A779H2), - Add eMMC and microSD expansion board support for the RZ/V2H and RZ/V2N EVK development boards, - Add GPIO keys and Ethernet support for the RZ/G3E SoM and SMARC Carrier-II EVK development board, - Add QSPI FLASH support for the RZ/V2H and RZ/V2N SoCs and their EVK development boards, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH arm64: dts: renesas: r9a09g057: Add XSPI node arm64: dts: renesas: r9a09g056: Add XSPI node arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Fix pinctrl node name for GBETH1 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Fix pinctrl node name for GBETH1 arm64: dts: renesas: r8a779g3-sparrow-hawk-fan-pwm: Add missing install target arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs arm64: dts: renesas: r8a779h2: Add Gray Hawk Single support arm64: dts: renesas: Add Renesas R8A779H2 SoC support arm64: dts: renesas: Factor out Gray Hawk Single board support dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock Link: https://lore.kernel.org/r/cover.1752090401.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'samsung-dt64-6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.17 1. New SoC - Exynos2200 SoC - with basic nodes, pin controllers, clock controllers and initial USB support. Add board using it: Samsung Galaxy S22+ (SM-S906B), called G0S. 2. ExynosAutov920: Add CMU_HSI2 clock controller, remaining SPI nodes 3. Google GS101: - Prepare to switching to architected timer, instead of Exynos MCT as the primary one. - Add secondary Maxim MAX77759 PMIC to Pixel boards, managing USB Type-C and charger. - Add incomplete description of the primary Samsung S2MPG10 PMIC. Several bits, like regulators, are still missing, though. - Add also secondary reboot-mode, via MAX77759 NVMEM. - Switch the primary (SoC) reboot handler to Google specific google,gs101-reboot which gives additional GS101 features (cold and warm reboots). This change will affect other users of this DTS, but to our knowledge there is only Android, from which this change originates. 4. Exynos7870: - Fix speed problems in USB gadget mode. - Correct memory map to avoid crashes due to secure world. * tag 'samsung-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos7870-j6lte: reduce memory ranges to base amount arm64: dts: exynos7870-on7xelte: reduce memory ranges to base amount arm64: dts: exynos7870: add quirk to disable USB2 LPM in gadget mode arm64: dts: exynos: gs101: switch to gs101 specific reboot arm64: dts: exynos: gs101-pixel-common: add main PMIC node arm64: dts: exynos: gs101: ufs: add dma-coherent property arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC arm64: dts: exynos5433: Align i2c-gpio node names with dtschema arm64: dts: exynos: gs101: Add 'local-timer-stop' to cpuidle nodes arm64: dts: exynosautov920: Add DT node for all SPI ports arm64: dts: exynosautov920: add CMU_HSI2 clock DT nodes MAINTAINERS: add entry for Samsung Exynos2200 SoC arm64: dts: exynos: add initial support for Samsung Galaxy S22+ arm64: dts: exynos: add initial support for exynos2200 SoC dt-bindings: arm: samsung: document g0s board binding Link: https://lore.kernel.org/r/20250709191523.171359-6-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'samsung-dt-6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM changes for v6.17 Just few cleanups based on dtbs_check. * tag 'samsung-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: s5pv210: Align i2c-gpio node names with dtschema ARM: dts: exynos: Align i2c-gpio node names with dtschema Link: https://lore.kernel.org/r/20250709191523.171359-5-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'dt-vt8500-6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt VT8500 DTS ARM changes for v6.17 1. Several dtbs_check cleanups. 2. Add missing cache topology - L2 cache controller on WM8850/WM895. * tag 'dt-vt8500-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt: ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950 ARM: dts: vt8500: Fix the unit address of the VT8500 LCD controller ARM: dts: vt8500: Use generic node name for the SD/MMC controller ARM: dts: vt8500: Move memory nodes to board dts and fix addr/size ARM: dts: vt8500: Add node address and reg in CPU nodes Link: https://lore.kernel.org/r/20250709184800.168462-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'v6.16-rc7' into tty-nextGreg Kroah-Hartman
We need the tty/serial fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-21riscv: defconfig: enable Andes SoCBen Zong-You Xie
Enable Andes SoC config in defconfig to allow the default upstream kernel to boot on Voyager board. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20250711133025.2192404-9-ben717@andestech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21riscv: dts: andes: add Voyager board device treeBen Zong-You Xie
Introduce the device tree support for Voyager development board. Currently only support booting into console with only uart, other features will be added later. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20250711133025.2192404-8-ben717@andestech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21riscv: dts: andes: add QiLai SoC device treeBen Zong-You Xie
Introduce the initial device tree support for the Andes QiLai SoC. For further information, you can refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20250711133025.2192404-7-ben717@andestech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21riscv: add Andes SoC family Kconfig supportBen Zong-You Xie
The first SoC in the Andes series is QiLai. It includes a high-performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. For further information, refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20250711133025.2192404-2-ben717@andestech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21KVM: s390: Rework guest entry logicMark Rutland
In __vcpu_run() and do_vsie_run(), we enter an RCU extended quiescent state (EQS) by calling guest_enter_irqoff(), which lasts until __vcpu_run() calls guest_exit_irqoff(). However, between the two we enable interrupts and may handle interrupts during the EQS. As the IRQ entry code will not wake RCU in this case, we may run the core IRQ code and IRQ handler without RCU watching, leading to various potential problems. It is necessary to unmask (host) interrupts around entering the guest, as entering the guest via SIE will not automatically unmask these. When a host interrupt is taken from a guest, it is taken via its regular host IRQ handler rather than being treated as a direct exit from SIE. Due to this, we cannot simply mask interrupts around guest entry, and must handle interrupts during this window, waking RCU as required. Additionally, between guest_enter_irqoff() and guest_exit_irqoff(), we use local_irq_enable() and local_irq_disable() to unmask interrupts, violating the ordering requirements for RCU/lockdep/tracing around entry/exit sequences. Further, since this occurs in an instrumentable function, it's possible that instrumented code runs during this window, with potential usage of RCU, etc. To fix the RCU wakeup problem, an s390 implementation of arch_in_rcu_eqs() is added which checks for PF_VCPU in current->flags. PF_VCPU is set/cleared by guest_timing_{enter,exit}_irqoff(), which surround the actual guest entry. To fix the remaining issues, the lower-level guest entry logic is moved into a shared noinstr helper function using the guest_state_{enter,exit}_irqoff() helpers. These perform all the lockdep/RCU/tracing manipulation necessary, but as sie64a() does not enable/disable interrupts, we must do this explicitly with the non-instrumented arch_local_irq_{enable,disable}() helpers: guest_state_enter_irqoff() arch_local_irq_enable(); sie64a(...); arch_local_irq_disable(); guest_state_exit_irqoff(); [ajd@linux.ibm.com: rebase, fix commit message] Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Frederic Weisbecker <frederic@kernel.org> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Janosch Frank <frankja@linux.ibm.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Paul E. McKenney <paulmck@kernel.org> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: Claudio Imbrenda <imbrenda@linux.ibm.com> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com> Reviewed-by: Janosch Frank <frankja@linux.ibm.com> Link: https://lore.kernel.org/r/20250708092742.104309-3-ajd@linux.ibm.com Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Message-ID: <20250708092742.104309-3-ajd@linux.ibm.com>
2025-07-21s390/stp: Default to enabledSven Schnelle
With time steering moved to userspace, stp can be enabled by default. Signed-off-by: Sven Schnelle <svens@linux.ibm.com> Acked-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2025-07-21s390/stp: Remove leap second supportSven Schnelle
With moving time steering to userspace, there's no need to handle leap seconds inside the kernel. Remove it. Signed-off-by: Sven Schnelle <svens@linux.ibm.com> Acked-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2025-07-21s390/time: Remove in-kernel time steeringSven Schnelle
Remove the in-kernel time steering in favour of the new ptp s390 driver, which allows the kernel clock to be steered more precise. Signed-off-by: Sven Schnelle <svens@linux.ibm.com> Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2025-07-21s390/smp: Use monotonic clock in smp_emergency_stop()Sven Schnelle
This is a cosmetic change because when in smp_emergency_stop() the system is going to die anyway. But still change the code to use get_tod_clock_monotonic() to prevent people from copying broken code. Signed-off-by: Sven Schnelle <svens@linux.ibm.com> Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2025-07-21s390/time: Use monotonic clock in get_cycles()Sven Schnelle
Otherwise the code might not work correctly when the clock is changed. Signed-off-by: Sven Schnelle <svens@linux.ibm.com> Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2025-07-21Merge tag 'v6.16-rc7' into usb-nextGreg Kroah-Hartman
We need the USB/Thunderbolt fixes in here for other patches to be on top of. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-07-21LoongArch: KVM: Add tracepoints for CPUCFG and CSR emulation exitsYulong Han
This patch adds tracepoints to track KVM exits caused by CPUCFG and CSR emulation. Note that IOCSR emulation tracing is already covered by the generic trace_kvm_iocsr(). Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Yulong Han <wheatfox17@icloud.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-21LoongArch: KVM: Add stat information with kernel irqchipBibo Mao
Move stat information about kernel irqchip from VM to vCPU, since all vm exiting events should be vCPU relative. And also add entry with structure kvm_vcpu_stats_desc[], so that it can display with directory /sys/kernel/debug/kvm. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-21LoongArch: KVM: Replace eiointc_enable_irq() with eiointc_update_irq()Bibo Mao
Function eiointc_enable_irq() checks mask value with char type, and call eiointc_update_irq() eventually. Function eiointc_update_irq() will update one single irq status directly. Here it can check mask value with unsigned long type and call function eiointc_update_irq(), that is simple and direct. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-21LoongArch: KVM: Use generic function loongarch_eiointc_write()Bibo Mao
With all eiointc iocsr register write operation with 1/2/4/8 bytes size, generic function loongarch_eiointc_write() is used here. And function loongarch_eiointc_writeb(), loongarch_eiointc_writew(), loongarch_eiointc_writel() are removed. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-21LoongArch: KVM: Use generic function loongarch_eiointc_read()Bibo Mao
Generic read function loongarch_eiointc_read() is used for 1/2/4/8 bytes read access. It reads 8 bytes from emulated software state and shift right from address offset. Also the similar with kvm_complete_iocsr_read(), destination register of IOCSRRD.{B/H/W} is sign extension from byte/half word/word. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-21LoongArch: KVM: Use standard bitops API with eiointcBibo Mao
Standard bitops APIs such test_bit() is used here, rather than manually calculating the offset and mask. Also use non-atomic API __set_bit() and __clear_bit() rather than set_bit() and clear_bit(), since the global spinlock is held already. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-21LoongArch: KVM: Remove never called default case statementBibo Mao
IOCSR instruction supports 1/2/4/8 bytes access, len must be 1/2/4/8 bytes from iocsr exit emulation function kvm_emu_iocsr(), remove the default case in switch case statements. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-21LoongArch: KVM: Remove unused parameter lenBibo Mao
Parameter len is unused in some functions with eiointc emulation driver, remove it here. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-21LoongArch: KVM: Remove unnecessary local variableBibo Mao
Local variable device1 can be replaced with existing variable device, it makes code concise. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-21LoongArch: KVM: Simplify kvm_deliver_intr()Yury Norov (NVIDIA)
The function opencodes for_each_set_bit() macro, which makes it bulky. Using the proper API makes all the housekeeping code going away. Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-21LoongArch: KVM: Rework kvm_send_pv_ipi()Yury Norov (NVIDIA)
The function in fact traverses a "bitmap" stored in GPR regs A1 and A2, but does it in a non-obvious way by creating a single-word bitmap twice. This patch switches the function to create a single 2-word bitmap, and also employs for_each_set_bit() macro, as it helps to drop most of the housekeeping code. While there, convert the function to return void to not confuse readers with unchecked result. Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-07-20Merge tag 'x86-urgent-2025-07-20' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 bug fix from Thomas Gleixner: "A single fix for a GCC wreckage, which emits a KCSAN instrumentation call in __sev_es_nmi_complete() despite the function being annotated with 'noinstr'. As all functions in that source file are noinstr, exclude the whole file from KCSAN in the Makefile to cure it" * tag 'x86-urgent-2025-07-20' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/sev: Work around broken noinstr on GCC
2025-07-20Merge tag 'hyperv-fixes-signed-20250718' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux Pull hyperv fixes from Wei Liu: - Select use CONFIG_SYSFB only if EFI is enabled (Michael Kelley) - An assorted set of fixes to remove warnings for missing export.h header inclusion (Naman Jain) - An assorted set of fixes for when Linux run as the root partition for Microsoft Hypervisor (Mukesh Rathor, Nuno Das Neves, Stanislav Kinsburskii) - Fix the check for HYPERVISOR_CALLBACK_VECTOR (Naman Jain) - Fix fcopy tool to handle irregularities with size of ring buffer (Naman Jain) - Fix incorrect file path conversion in fcopy tool (Yasumasa Suenaga) * tag 'hyperv-fixes-signed-20250718' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux: tools/hv: fcopy: Fix irregularities with size of ring buffer PCI: hv: Use the correct hypercall for unmasking interrupts on nested x86/hyperv: Expose hv_map_msi_interrupt() Drivers: hv: Use nested hypercall for post message and signal event x86/hyperv: Clean up hv_map/unmap_interrupt() return values x86/hyperv: Fix usage of cpu_online_mask to get valid cpu PCI: hv: Don't load the driver for baremetal root partition net: mana: Fix warnings for missing export.h header inclusion PCI: hv: Fix warnings for missing export.h header inclusion clocksource: hyper-v: Fix warnings for missing export.h header inclusion x86/hyperv: Fix warnings for missing export.h header inclusion Drivers: hv: Fix warnings for missing export.h header inclusion Drivers: hv: Fix the check for HYPERVISOR_CALLBACK_VECTOR tools/hv: fcopy: Fix incorrect file path conversion Drivers: hv: Select CONFIG_SYSFB only if EFI is enabled
2025-07-19riscv: optimize gcd() performance on RISC-V without Zbb extensionKuan-Wei Chiu
The binary GCD implementation uses FFS (find first set), which benefits from hardware support for the ctz instruction, provided by the Zbb extension on RISC-V. Without Zbb, this results in slower software-emulated behavior. Previously, RISC-V always used the binary GCD, regardless of actual hardware support. This patch improves runtime efficiency by disabling the efficient_ffs_key static branch when Zbb is either not enabled in the kernel (config) or not supported on the executing CPU. This selects the odd-even GCD implementation, which is faster in the absence of efficient FFS. This change ensures the most suitable GCD algorithm is chosen dynamically based on actual hardware capabilities. Link: https://lkml.kernel.org/r/20250606134758.1308400-4-visitorckw@gmail.com Co-developed-by: Yu-Chun Lin <eleanor15x@gmail.com> Signed-off-by: Yu-Chun Lin <eleanor15x@gmail.com> Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Acked-by: Alexandre Ghiti <alexghiti@rivosinc.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Ching-Chun (Jim) Huang <jserv@ccns.ncku.edu.tw> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
generated by cgit (git 2.34.1) at 2025-09-13 14:38:25 +0000