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path: root/drivers/clk
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2019-07-12Merge branches 'clk-qcom-gdsc-warn', 'clk-ingenic', 'clk-qcom-qcs404-reset', ↵Stephen Boyd
'clk-xgene-limit' and 'clk-meson' into clk-next * clk-qcom-gdsc-warn: clk: qcom: gdsc: WARN when failing to toggle * clk-ingenic: MIPS: Remove dead code clk: ingenic: Remove unused functions MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep mode clk: ingenic: Handle setting the Low-Power Mode bit clk: ingenic: Add missing header in cgu.h clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly clk: ingenic/jz4725b: Fix incorrect dividers for main clocks clk: ingenic/jz4770: Fix incorrect dividers for main clocks clk: ingenic/jz4740: Fix incorrect dividers for main clocks clk: ingenic: Add support for divider tables * clk-qcom-qcs404-reset: clk: gcc-qcs404: Add PCIe resets * clk-xgene-limit: clk: xgene: Don't build COMMON_CLK_XGENE by default * clk-meson: clk: meson: g12a: mark fclk_div3 as critical clk: meson: g12a: Add support for G12B CPUB clocks dt-bindings: clk: meson: add g12b periph clock controller bindings clk: meson-g12a: add temperature sensor clocks dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs clk: meson: meson8b: add the cts_i958 clock clk: meson: meson8b: add the cts_mclk_i958 clocks clk: meson: meson8b: add the cts_amclk clocks dt-bindings: clock: meson8b: add the audio clocks clk: meson: g12a: add controller register init clk: meson: eeclk: add init regs clk: meson: g12a: add mpll register init sequences clk: meson: mpll: add init callback and regs clk: meson: axg: spread spectrum is on mpll2 clk: meson: gxbb: no spread spectrum on mpll0 clk: meson: mpll: properly handle spread spectrum clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
2019-07-12Merge branches 'clk-pwm-duty', 'clk-bcm', 'clk-mtk', 'clk-qcom-msm8998-gpu' ↵Stephen Boyd
and 'clk-renesas' into clk-next - Add support to get duty cycle of generic pwm clks * clk-pwm-duty: clk: pwm: implement the .get_duty_cycle callback * clk-bcm: clk: bcm: Allow CLK_BCM2835 for ARCH_BRCMSTB clk: bcm: Make BCM2835 clock drivers selectable * clk-mtk: clk: mediatek: Remove MT8183 unused clock clk: mediatek: add audsys clock driver for MT8516 dt-bindings: mediatek: audsys: add support for MT8516 * clk-qcom-msm8998-gpu: dt-bindings: clock: Document gpucc for msm8998 * clk-renesas: clk: renesas: cpg-mssr: Use [] to denote a flexible array member clk: renesas: cpg-mssr: Combine driver-private and clock array allocation clk: renesas: mstp: Combine group-private and clock array allocation clk: renesas: div6: Combine clock-private and parent array allocation clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv clk: renesas: r8a774a1: Add TMU clock clk: renesas: r8a77995: Add CMM clocks clk: renesas: r8a77990: Add CMM clocks clk: renesas: r8a77965: Add CMM clocks clk: renesas: r8a7795: Add CMM clocks clk: renesas: r9a06g032: Add clock domain support dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains clk: renesas: mstp: Remove error messages on out-of-memory conditions clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions clk: renesas: cpg-mssr: Use genpd of_node instead of local copy clk: renesas: r8a7796: Add CMM clocks clk: renesas: r8a779{5|6|65}: Add TPU clock
2019-07-12scripts/spelling.txt: add spelling fix for prohibitedChris Paterson
Misspelling 'prohibited' is quite common in the real world, although surprisingly not so much in the Linux Kernel. In addition to fixing the typo we may as well add it to the spelling checker. Also adding the present participle (prohibiting). Link: http://lkml.kernel.org/r/20190514153341.22540-1-chris.paterson2@renesas.com Fixes: 5bf2fbbef50c ("clk: renesas: cpg-mssr: Add r8a77470 support") Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2019-07-12clk: consoldiate the __clk_get_hw() declarationsStephen Rothwell
Without this we were getting errors like: In file included from drivers/clk/clkdev.c:22:0: drivers/clk/clk.h:36:23: error: static declaration of '__clk_get_hw' follows non-static declaration include/linux/clk-provider.h:808:16: note: previous declaration of '__clk_get_hw' was here Fixes: 59fcdce425b7 ("clk: Remove ifdef for COMMON_CLK in clk-provider.h") fixes: 73e0e496afda ("clkdev: Always allocate a struct clk and call __clk_get() w/ CCF") Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-02Merge branches 'ib-mfd-clk-gpio-power-regulator-rtc-5.3', ↵Lee Jones
'ib-mfd-clk-regulator-rtc-5.3', 'ib-mfd-cros-5.3' and 'ib-mfd-regulator-5.3' into ibs-for-mfd-merged
2019-06-28Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A handful of clk driver fixes and one core framework fix - Do a DT/firmware lookup in clk_core_get() even when the DT index is a nonsensical value - Fix some clk data typos in the Amlogic DT headers/code - Avoid returning junk in the TI clk driver when an invalid clk is looked for - Fix dividers for the emac clks on Stratix10 SoCs - Fix default HDA rates on Tegra210 to correct distorted audio" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: socfpga: stratix10: fix divider entry for the emac clocks clk: Do a DT parent lookup even when index < 0 clk: tegra210: Fix default rates for HDA clocks clk: ti: clkctrl: Fix returning uninitialized data clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
2019-06-27clk: sprd: Add check for return value of sprd_clk_regmap_init()Chunyan Zhang
sprd_clk_regmap_init() doesn't always return success, adding check for its return value should make the code more strong. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Reviewed-by: Baolin Wang <baolin.wang@linaro.org> [sboyd@kernel.org: Add a missing int ret] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: Add Si5341/Si5340 driverMike Looijmans
Adds a driver for the Si5341 and Si5340 chips. The driver does not fully support all features of these chips, but allows the chip to be used without any support from the "clockbuilder pro" software. If the chip is preprogrammed, that is, you bought one with some defaults burned in, or you programmed the NVM in some way, the driver will just take over the current settings and only change them on demand. Otherwise the input must be a fixed XTAL in its most basic configuration (no predividers, no feedback, etc.). The driver supports dynamic changes of multisynth, output dividers and enabling or powering down outputs and multisynths. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> [sboyd@kernel.org: Mark some things static, use BIT_ULL for big bits and ULL for big constants] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: clk-si544: Implement small frequency change supportMike Looijmans
The Si544 supports changing frequencies "on the fly" when the change is less than 950 ppm from the current center frequency. The driver now uses the small adjustment routine for implementing this. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: add BCM63XX gated clock controller driverJonas Gorski
Add a driver for the gated clock controller found on MIPS based BCM63XX SoCs. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [sboyd@kernel.org: Remove module.h include and associated things for a non-modular driver, add static on data tables, drop of_match_ptr() usage, fix spdx tag to be a C++ style comment] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: at91: sckc: use dedicated functions to unregister clockClaudiu Beznea
Use at91 specific functions to free all resources in case of error. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: at91: sckc: improve error path for sama5d4 sck registrationClaudiu Beznea
Improve error path for sama5d4 sck registration. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: at91: sckc: remove unnecessary lineClaudiu Beznea
Remove unnecessary line. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: at91: sckc: improve error path for sam9x5 sck registerClaudiu Beznea
Improve error path for sam9x5 slow clock registration. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: at91: sckc: add support to free slow clock osclillatorClaudiu Beznea
Add support to free slow clock oscillator resources. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: at91: sckc: add support to free slow rc oscillatorClaudiu Beznea
Add support to free slow rc oscillator resources. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: at91: sckc: add support to free slow oscillatorClaudiu Beznea
Add support to free slow oscillator resources. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27clk: RK808: Add RK809 and RK817 support.Tony Xie
RK809 and RK817 are power management IC chips for multimedia products. most of their functions and registers are same, including the clkout funciton. Signed-off-by: Tony Xie <tony.xie@rock-chips.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-06-27clk: bd718x7: Support ROHM BD70528 clk blockMatti Vaittinen
ROHM BD70528 is an ultra low power PMIC with similar 32K clk as bd718x7. Only difference (from clk perspective) is register address. Add support for controlling BD70528 clk using bd718x7 driver. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-06-27mfd: regulator: clk: Split rohm-bd718x7.hMatti Vaittinen
Split the bd718x7.h to ROHM common and bd718x7 specific parts so that we do not need to add same things in every new ROHM PMIC header. Please note that this change requires changes also in bd718x7 sub-device drivers for regulators and clk. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-06-27clk: rockchip: export HDMIPHY clock on rk3228Heiko Stuebner
Export the hdmiphy clock mux via the newly added clock-id. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Justin Swartz <justin.swartz@risingedge.co.za>
2019-06-27clk: rockchip: add watchdog pclk on rk3328Heiko Stuebner
The watchdog pclk is controlled from the secure GRF but we still want to mention it explicitly to not use arbitary parent clocks in the devicetree wdt node, so add a SGRF_GATE for it. Suggested-by: Leonidas P. Papadakos <papadakospan@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-26clk: at91: sckc: add support for SAM9X60Claudiu Beznea
Add support for SAM9X60's slow clock. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26clk: at91: sckc: add support to specify registers bit offsetsClaudiu Beznea
Different IPs uses different bit offsets in registers for the same functionality, thus adapt the driver to support this. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26clk: at91: sckc: sama5d4 has no bypass supportClaudiu Beznea
The slow clock of SAMA5D4 has no bypass support thus remove it. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26clk: sprd: Check error only for devm_regmap_init_mmio()Chunyan Zhang
The function devm_regmap_init_mmio() wouldn't return NULL pointer for now, so only need to ensure the return value is not an error code. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Reviewed-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26clk: sprd: Switch from of_iomap() to devm_ioremap_resource()Chunyan Zhang
devm_ioremap_resources() automatically requests resources and devm_ wrappers do better error handling and unmapping of the I/O region when needed, that would make drivers more clean and simple. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Reviewed-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: lochnagar: Use new parent_data approach to register clock parentsCharles Keepax
Switch over to the more modern style of registering parents and simplify the code in the process. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: tegra: Do not enable PLL_RE_VCO on Tegra210Thierry Reding
It turns out that this PLL is not used on Tegra210, so there's no need to enable it via the init table. Remove the init table entry for this PLL to avoid it getting enabled at boot time. If the bootloader enabled it and forgot to turn it off, the common clock framework will now know to disable it because it is unused. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: tegra: Warn if an enabled PLL is in IDDQThierry Reding
A PLL in IDDQ doesn't work, whether it's enabled or not. This is not a configuration that makes sense, so warn about it. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: tegra: Do not warn unnecessarilyThierry Reding
There is no need to warn if the reference PLL is enabled with the correct defaults. Only warn if the boot values don't match the defaults. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: tegra210: fix PLLU and PLLU_OUT1JC Kuo
Full-speed and low-speed USB devices do not work with Tegra210 platforms because of incorrect PLLU/PLLU_OUT1 clock settings. When full-speed device is connected: [ 14.059886] usb 1-3: new full-speed USB device number 2 using tegra-xusb [ 14.196295] usb 1-3: device descriptor read/64, error -71 [ 14.436311] usb 1-3: device descriptor read/64, error -71 [ 14.675749] usb 1-3: new full-speed USB device number 3 using tegra-xusb [ 14.812335] usb 1-3: device descriptor read/64, error -71 [ 15.052316] usb 1-3: device descriptor read/64, error -71 [ 15.164799] usb usb1-port3: attempt power cycle When low-speed device is connected: [ 37.610949] usb usb1-port3: Cannot enable. Maybe the USB cable is bad? [ 38.557376] usb usb1-port3: Cannot enable. Maybe the USB cable is bad? [ 38.564977] usb usb1-port3: attempt power cycle This commit fixes the issue by: 1. initializing PLLU_OUT1 before initializing XUSB_FS_SRC clock because PLLU_OUT1 is parent of XUSB_FS_SRC. 2. changing PLLU post-divider to /2 (DIVP=1) according to Technical Reference Manual. Fixes: e745f992cf4b ("clk: tegra: Rework pll_u") Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: raspberrypi: register platform device for raspberrypi-cpufreqNicolas Saenz Julienne
As 'clk-raspberrypi' depends on RPi's firmware interface, which might be configured as a module, the cpu clock might not be available for the cpufreq driver during it's init process. So we register the 'raspberrypi-cpufreq' platform device after the probe sequence succeeds. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: bcm283x: add driver interfacing with Raspberry Pi's firmwareNicolas Saenz Julienne
Raspberry Pi's firmware offers an interface though which update it's clock's frequencies. This is specially useful in order to change the CPU clock (pllb_arm) which is 'owned' by the firmware and we're unable to scale using the register interface provided by clk-bcm2835. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: bcm2835: remove pllbNicolas Saenz Julienne
Raspberry Pi's firmware controls this pll, we should use the firmware interface to access it. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: qoriq: add support for lx2160aVabhav Sharma
Add clockgen support and configuration for NXP SoC lx2160a with compatible property as "fsl,lx2160a-clockgen". Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Acked-by: Scott Wood <oss@buserror.net> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: clk-cdce706: simplify getting the adapter of a clientWolfram Sang
We have a dedicated pointer for that, so use it. Much easier to read and less computation involved. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: qcom: Fix -Wunused-const-variableNathan Huckleberry
Clang produces the following warning drivers/clk/qcom/gcc-msm8996.c:133:32: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map' [-Wunused-const-variable] static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = { ^drivers/clk/qcom/gcc-msm8996.c:141:27: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div' [-Wunused-const-variable] static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = { ^ drivers/clk/qcom/gcc-msm8996.c:187:32: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map' [-Wunused-const-variable] static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = { ^ drivers/clk/qcom/gcc-msm8996.c:197:27: warning: unused variable 'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div' [-Wunused-const-variable] static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = { It looks like these were never used. Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Cc: clang-built-linux@googlegroups.com Link: https://github.com/ClangBuiltLinux/linux/issues/518 Suggested-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Nathan Huckleberry <nhuck@google.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: ingenic: Remove unused functionsPaul Cercueil
These functions are not called anywhere anymore, they can safely be removed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil
The Low-Power Mode, when enabled, will make the "wait" MIPS instruction suspend the system. This is not really clock-related, but this bit happens to be in the register set of the CGU. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: ingenic: Add missing header in cgu.hPaul Cercueil
The cgu.h has structures that contain 'clk_onecell_data' and 'clk_hw' structures (no pointers), so the <linux/clk-provider.h> header should be included. Signed-off-by: Paul Cercueil <paul@crapouillou.net> [sboyd@kernel.org: Drop removal of includes in drivers] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: Add clk_parent entry in debugfsLeonard Crestez
This allows to easily determine the parent in shell scripts without parsing more complex files. Add the clk_parent file for all clks which can have a parent, not just muxes. This way it can be used to determine the clk tree structure without parsing more complex files. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: Grammar missing "and", Spelling s/statisfied/satisfied/Geert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: Simplify clk_core_can_round()Geert Uytterhoeven
A boolean expression already evaluates to true or false, so there is no need to check the result and return true or false explicitly. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: socfpga: stratix10: fix divider entry for the emac clocksDinh Nguyen
The fixed dividers for the emac clocks should be 2 not 4. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: socfpga: stratix10: add additional clocks needed for the NAND IPDinh Nguyen
The nand_clk is actually called the nand_x_clk and the parent is the l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the nand_x_clk and has a fixed divider of 4. The same is true for the nand_ecc_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: kirkwood: Add support for MV98DX1135Chris Packham
The 98DX1135 is a switch chip with an integrated CPU. This is similar to the 98DX4122 except that the core clock speed is fixed to 166Mhz. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: Add devm_clk_bulk_get_optional() functionSylwester Nawrocki
Add managed version of the clk_bulk_get_optional() helper function. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> [sboyd@kernel.org: Mark __devm_clk_bulk_get() static] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: Add clk_bulk_get_optional() functionSylwester Nawrocki
clk_bulk_get_optional() allows to get a group of clocks where one or more is optional. For a not available clock, e.g. not specifed in the clock consumer node in DT, its respective struct clk pointer will be NULL. This allows for operating on a group of returned clocks (struct clk_bulk_data array) with existing clk_bulk* APIs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25clk: socfpga: stratix10: fix divider entry for the emac clocksDinh Nguyen
The fixed dividers for the emac clocks should be 2 not 4. Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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