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path: root/drivers/clk
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2021-10-26clk: use clk_core_get_rate_recalc() in clk_rate_get()Claudiu Beznea
In case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get() will return the cached rate. Thus, use clk_core_get_rate_recalc() which takes proper action when clock flags contains CLK_GET_RATE_NOCACHE. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-16-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> [sboyd@kernel.org: Grab prepare lock around operation] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: sama7g5: set low limit for mck0 at 32KHzClaudiu Beznea
MCK0 could go as low as 32KHz. Set this limit. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-15-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: sama7g5: remove prescaler part of master clockClaudiu Beznea
On SAMA7G5 the prescaler part of master clock has been implemented as a changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has been discovered that in some conditions the PMC_SR.MCKRDY is not rising but the rate it provides it's stable. The workaround is to add a timeout when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler will be removed from Linux clock tree as all the frequencies for CPU could be obtained from PLL and also there will be less overhead when changing frequency via DVFS. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-14-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: clk-master: add notifier for dividerClaudiu Beznea
SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same parent with cpuck as seen in the following clock tree: +----------> cpuck | FRAC PLL ---> DIV PLL -+-> DIV ---> mck0 mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking while changing FRAC PLL or DIV PLL the commit implements a notifier for mck0 which applies a safe divider to register (maximum value of the divider which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE events. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: clk-sam9x60-pll: add notifier for div part of PLLClaudiu Beznea
SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts: one fractional part and one divider. On SAMA7G5 the CPU PLL could be changed at run-time to implement DVFS. The hardware clock tree on SAMA7G5 for CPU PLL is as follows: +---- div1 ----------------> cpuck | FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0 The div1 block is not implemented in Linux; on prescaler block it has been discovered a bug on some scenarios and will be removed from Linux in next commits. Thus, the final clock tree that will be used in Linux will be as follows: +-----------> cpuck | FRAC PLL ---> DIV PLL -+-> div0 ---> mck0 It has been proposed in [1] to not introduce a new CPUFreq driver but to overload the proper clock drivers with proper operation such that cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement clock notifiers which applies safe dividers before FRAC PLL is changed. The current commit treats only the DIV PLL by adding a notifier that sets a safe divider on PRE_RATE_CHANGE events. The safe divider is provided by initialization clock code (sama7g5.c). The div0 is treated in next commits (to keep the changes as clean as possible). [1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/ Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: clk-master: fix prescaler logicClaudiu Beznea
When prescaler value read from register is MASTER_PRES_MAX it means that the input clock will be divided by 3. Fix the code to reflect this. Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: clk-master: mask mckr against layout->maskClaudiu Beznea
Mask values read/written from/to MCKR against layout->mask as this mask may be different b/w PMC versions. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-10-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: clk-master: check if div or pres is zeroClaudiu Beznea
Check if div or pres is zero before using it as argument for ffs(). In case div is zero ffs() will return 0 and thus substracting from zero will lead to invalid values to be setup in registers. Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") Fixes: 75c88143f3b87 ("clk: at91: clk-master: add master clock support for SAMA7G5") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULLClaudiu Beznea
Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate computed in sam9x60_frac_pll_recalc_rate() and the one computed in sam9x60_frac_pll_compute_mul_frac(). Fixes: 43b1bb4a9b3e1 ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-8-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: pmc: add sama7g5 to the list of available pmcsClaudiu Beznea
Add SAMA7G5 to the list of available PMCs such that the suspend/resume code for clocks to be used on backup mode. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-7-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: clk-master: improve readability by using local variablesClaudiu Beznea
Improve readability in clk_sama7g5_master_set() by using local variables. Suggested-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-6-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: clk-master: add register definition for sama7g5's master clockClaudiu Beznea
SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the register at offset 0x30 (relative to PMC). In the last/first phase of suspend/resume procedure (which is architecture specific) the parent of master clocks are changed (via assembly code) for more power saving (see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable and at91_mckx_ps_restore). Thus the macros corresponding to register at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S. commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's master clock") introduced the proper macros but didn't adapted the clk-master.c as well. Thus, this commit adapt the clk-master.c to use the macros introduced in commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's master clock"). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: sama7g5: add securam's peripheral clockClaudiu Beznea
Add SECURAM's peripheral clock. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-4-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: pmc: execute suspend/resume only for backup modeClaudiu Beznea
Before going to backup mode architecture specific PM code sets the first word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()). Thus take this into account when suspending/resuming clocks. This will avoid executing unnecessary instructions when suspending to non backup modes. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-3-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: at91: re-factor clocks suspend/resumeClaudiu Beznea
SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where most of the SoC's components are powered off (including PMC). Resuming from this mode is done with the help of bootloader. Peripherals are not aware of the power saving mode thus most of them are disabling clocks in proper suspend API and re-enable them in resume API without taking into account the previously setup rate. Moreover some of the peripherals are acting as wakeup sources and are not disabling the clocks in this scenario, when suspending. Since backup mode cuts the power for peripherals, in resume part these clocks needs to be re-configured. The initial PMC suspend/resume code was designed only for SAMA5D2's PMC (as it was the only one supporting backup mode). SAMA7G supports also backup mode and its PMC is different (few new functionalities, different registers offsets, different offsets in registers for each functionalities). To address both SAMA5D2 and SAMA7G5 PMC add .save_context()/.resume_context() support to each clocks driver and call this from PMC driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-26clk: ux500: Add driver for the reset portions of PRCCLinus Walleij
The Ux500 PRCC (peripheral reset and clock controller) can also control reset of the IP blocks, not just clocks. As the PRCC is probed as a clock controller and we have other platforms implementing combined clock and reset controllers, follow this pattern and implement the PRCC rest controller as part of the clock driver. The reset controller needs to be selected from the machine as Ux500 has traditionally selected its mandatory subsystem prerequisites from there. Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210921184803.1757916-2-linus.walleij@linaro.org Acked-by: Ulf Hansson <ulf.hansson@linaro.org> [sboyd@kernel.org: Dropped allocation error message] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-25clk: bcm-2835: Remove rounding up the dividersMaxime Ripard
The driver, once it found a divider, tries to round it up by increasing the least significant bit of the fractional part by one when the round_up argument is set and there's a remainder. However, since it increases the divider it will actually reduce the clock rate below what we were asking for, leading to issues with clk_set_min_rate() that will complain that our rounded clock rate is below the minimum of the rate. Since the dividers are fairly precise already, let's remove that part so that we can have clk_set_min_rate() working. This is effectively a revert of 9c95b32ca093 ("clk: bcm2835: add a round up ability to the clock divisor"). Fixes: 9c95b32ca093 ("clk: bcm2835: add a round up ability to the clock divisor") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenz@kernel.org> # boot and basic functionality Tested-by: Michael Stapelberg <michael@stapelberg.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210922125419.4125779-3-maxime@cerno.tech
2021-10-25clk: bcm-2835: Pick the closest clock rateMaxime Ripard
The driver currently tries to pick the closest rate that is lower than the rate being requested. This causes an issue with clk_set_min_rate() since it actively checks for the rounded rate to be above the minimum that was just set. Let's change the logic a bit to pick the closest rate to the requested rate, no matter if it's actually higher or lower. Fixes: 6d18b8adbe67 ("clk: bcm2835: Support for clock parent selection") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenz@kernel.org> # boot and basic functionality Tested-by: Michael Stapelberg <michael@stapelberg.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210922125419.4125779-2-maxime@cerno.tech
2021-10-20clk: ti: am43xx: Add clkctrl data for am43xx ADC1Miquel Raynal
Declare ADC1 clkctrl which feeds the magnetic-reader/ADC1 hardware module. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211015081506.933180-2-miquel.raynal@bootlin.com
2021-10-18clk: composite: Use rate_ops.determine_rate when also a mux is availableMartin Blumenstingl
Update clk_composite_determine_rate() to use rate_ops.determine_rate when available in combination with a mux. So far clk_divider_ops provide both, .round_rate and .determine_rate. Removing the former would make clk-composite fail silently for example on Rockchip platforms (which heavily use composite clocks). Add support for using rate_ops.determine_rate when either rate_ops.round_rate is not available or both (.round_rate and .determine_rate) are provided. Suggested-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20211016105022.303413-3-martin.blumenstingl@googlemail.com Tested-by: Alex Bee <knaerzche@gmail.com> Tested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-18clk: composite: Also consider .determine_rate for rate + mux compositesMartin Blumenstingl
Commit 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default") switches clk_divider_ops to implement .determine_rate by default. This breaks composite clocks with multiple parents because clk-composite.c does not use the special handling for mux + divider combinations anymore (that was restricted to rate clocks which only implement .round_rate, but not .determine_rate). Alex reports: This breaks lot of clocks for Rockchip which intensively uses composites, i.e. those clocks will always stay at the initial parent, which in some cases is the XTAL clock and I strongly guess it is the same for other platforms, which use composite clocks having more than one parent (e.g. mediatek, ti ...) Example (RK3399) clk_sdio is set (initialized) with XTAL (24 MHz) as parent in u-boot. It will always stay at this parent, even if the mmc driver sets a rate of 200 MHz (fails, as the nature of things), which should switch it to any of its possible parent PLLs defined in mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p (see clk-rk3399.c) - which never happens. Restore the original behavior by changing the priority of the conditions inside clk-composite.c. Now the special rate + mux case (with rate_ops having a .round_rate - which is still the case for the default clk_divider_ops) is preferred over rate_ops which have .determine_rate defined (and not further considering the mux). Fixes: 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default") Reported-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20211016105022.303413-2-martin.blumenstingl@googlemail.com Tested-by: Alex Bee <knaerzche@gmail.com> Tested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-18clk: samsung: describe drivers in KconfigKrzysztof Kozlowski
Describe better which driver applies to which SoC, to make configuring kernel for Samsung SoC easier. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20210924133624.112593-1-krzysztof.kozlowski@canonical.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-15clk: samsung: exynos5433: update apollo and atlas clock probingWill McVicker
Use the samsung common clk driver to initialize the apollo and atlas clocks. This removes their custom init functions and uses the samsung_cmu_register_one() instead. Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211014195347.3635601-3-willmcvicker@google.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-15clk: samsung: add support for CPU clocksWill McVicker
Adds 'struct samsung_cpu_clock' and corresponding CPU clock registration function to the samsung common clk driver. This allows samsung clock drivers to register their CPU clocks with the samsung_cmu_register_one() API. Currently the exynos5433 apollo and atlas clks have their own custom init functions to handle registering their CPU clocks. With this patch we can drop their custom CLK_OF_DECLARE functions and directly call samsung_cmu_register_one(). Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211014195347.3635601-2-willmcvicker@google.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-15clk: samsung: Introduce Exynos850 clock driverSam Protsenko
This is the initial implementation adding only basic clocks like UART, MMC, I2C and corresponding parent clocks. Design is influenced by Exynos5433 clock driver. Bus clock is enabled by default (in probe function) for all CMUs except CMU_TOP, the reasoning is as follows. By default if bus clock has no users its "enable count" value is 0. It might be actually running if it's already enabled in bootloader, but then in some cases it can be disabled by mistake. For example, such case was observed when dw_mci_probe() enabled the bus clock, then failed to do something and disabled that bus clock on error path. After that, even the attempt to read the 'clk_summary' file in DebugFS freezed forever, as CMU bus clock ended up being disabled and it wasn't possible to access CMU registers anymore. To avoid such cases, CMU driver must increment the ref count for that bus clock by running clk_prepare_enable(). There is already existing '.clk_name' field in struct samsung_cmu_info, exactly for that reason. It was added in commit 523d3de41f02 ("clk: samsung: exynos5433: Add support for runtime PM"), with next mentioning in commit message: > Also for each CMU there is one special parent clock, which has to be > enabled all the time when any access to CMU registers is being done. But that clock is actually only enabled in Exynos5433 clock driver right now. So the same code is added to exynos850_cmu_probe() function, As was described above, it might be helpful not only for PM reasons, but also to prevent possible erroneous clock gating on error paths. Another way to workaround that issue would be to use CLOCK_IS_CRITICAL flag for corresponding gate clocks. But that might be not very good design decision, as we might still want to disable that bus clock, e.g. on PM suspend. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211008154352.19519-6-semen.protsenko@linaro.org Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-10-15clk: renesas: r8a779[56]x: Add MLP clocksAndrey Gusakov
Add clocks for MLP modules on Renesas R-Car H3 and M3-W/N SoCs. Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20210929213431.5275-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-10-14clk: versatile: hide clock drivers from non-ARM usersJean Delvare
Commit 419b3ab6987f ("clk: versatile: remove dependency on ARCH_*") made the whole menu of ARM reference clock drivers visible on all architectures. I can't see how this is an improvement for non-ARM users. Unless build-testing, there is no point on presenting ARM-only clock drivers on other architectures. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Peter Collingbourne <pcc@google.com> Cc: Lee Jones <lee.jones@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210901180953.5bd2a994@endymion Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: versatile: Rename ICST to CLK_ICSTJean Delvare
For consistency, prefix the ICST config option with CLK as all other clock source drivers have. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210901180833.4558932d@endymion Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gdsc: enable optional power domain supportDmitry Baryshkov
On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Currently we use a regulator to enable this domain on demand, however this has some consequences, as genpd code is not reentrant. Make gdsc code also use pm_runtime calls to ensure that registers are accessible during the gdsc_enable/gdsc_disable operations. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829154757.784699-6-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: videocc-sm8250: use runtime PM for the clock controllerDmitry Baryshkov
On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829154757.784699-5-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: dispcc-sm8250: use runtime PM for the clock controllerDmitry Baryshkov
On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829154757.784699-4-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-14clk: qcom: gcc-sc7280: Drop unused arrayStephen Boyd
After commit 3165d1e3c737 ("clk: qcom: gcc: Remove CPUSS clocks control for SC7280") this array is unused. Remove it. Reported-by: kernel test robot <lkp@intel.com> Cc: Taniya Das <tdas@codeaurora.org> Fixes: 3165d1e3c737 ("clk: qcom: gcc: Remove CPUSS clocks control for SC7280") Link: https://lore.kernel.org/r/20211014191259.1689641-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: camcc: Add camera clock controller driver for SC7280Taniya Das
Add support for the camera clock controller found on SC7280 based devices. This would allow camera drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633567425-11953-2-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Make some VCOs unsigned long] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: Add lpass clock controller driver for SC7280Taniya Das
Add support for the lpass clock controller found on SC7280 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633484416-27852-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: Kconfig: Sort the symbol for SC_LPASS_CORECC_7180Taniya Das
Fix the order of the Kconfig symbol for SC_LPASS_CORECC_7180. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633484416-27852-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: mmcc-sdm660: Add hw_ctrl flag to venus_core0_gdscAngeloGioacchino Del Regno
As shown downstream[1], this GDSC supports HW trigger mode and we're supposed to enable it in order to ensure correct operation. [1]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/arch/arm/boot/dts/qcom/sdm630.dtsi#L2181 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211008102041.268253-2-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: mmcc-sdm660: Add necessary CXCs to venus_gdscAngeloGioacchino Del Regno
As also shown on downstream dts[1], for a correct operation of the Venus block, we have to retain MEM/PERIPH when halting the video_core, video_axi and video_subcore0 branches: add these CXCs to the main Venus GDSC. [1]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi#L80 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211008102041.268253-1-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-msm8994: Use ARRAY_SIZE() for num_parentsKonrad Dybcio
Don't rely on the programmer to enter the name of array elements, since the computer can compute it with much less chance of making a mistake. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-9-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-msm8994: Add proper msm8992 supportKonrad Dybcio
MSM8992 is a cut-down version of MSM8994, featuring largely the same hardware. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-8-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-msm8994: Add modem resetKonrad Dybcio
This will be required to support the modem. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-7-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIEKonrad Dybcio
This GDSC is not present on msm8994. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-6-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-msm8994: Add missing clocksKonrad Dybcio
This should be the last "add missing clocks" commit, as to my knowledge there are no more clocks registered within gcc. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-5-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-msm8994: Add missing NoC clocksKonrad Dybcio
Add necessary NoC clocks to provide frequency sources for relevant branch clocks. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-4-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-msm8994: Fix up SPI QUP clocksKonrad Dybcio
Fix up SPI QUP freq tables to account for the fact that not every QUP can run at the same set of frequencies. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-3-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-msm8994: Modernize the driverKonrad Dybcio
Switch to the newer-style parent_data and remove the hardcoded xo clock. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-2-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: smd-rpm: Add QCM2290 RPM clock supportShawn Guo
Add support for RPM-managed clocks on the QCM2290 platform. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210917030434.19859-4-shawn.guo@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: smd-rpm: Add .recalc_rate hook for clk_smd_rpm_branch_opsShawn Guo
As there is a `rate` field in clk_smd_rpm, clk_smd_rpm_recalc_rate() can be used by branch clocks to report rate as well, rather than assuming the rate is always same as parent clock. This assumption doesn't hold on platforms like QCM2290, where xo_board is 38.4MHz while bi_tcxo is 19.2MHz. To get this work, XO buffered clocks need the following updates. - Assign a correct rate rather than the fake one which is being used to generate binary value for clk_smd_rpm_req interface. - Explicitly handle the clk_smd_rpm_req interface value for XO buffered clocks (.rpm_res_type being QCOM_SMD_RPM_CLK_BUF_A). Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210917030434.19859-2-shawn.guo@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sboyd@kernel.org: Do cpu_to_le32() again to keep sparse happy] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: Add Global Clock Controller driver for QCM2290Shawn Guo
Add Global Clock Controller (GCC) driver for QCM2290. This is a porting of gcc-scuba driver from CAF msm-4.19, with GDSC support added on top. Because the alpha_pll on the platform has a different register layout (offsets), its own clk_alpha_pll_regs_offset[] is used in the driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210919023308.24498-3-shawn.guo@linaro.org Acked-by: Rob Herring <robh@kernel.org> [sboyd@kernel.org: Drop duplicate includes, clk.h include, module alias] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: add select QCOM_GDSC for SM6350Luca Weiss
QCOM_GDSC is needed for the gcc driver to probe. Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver") Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20211007212444.328034-2-luca@z3ntu.xyz Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-13clk: qcom: gcc-sm6115: Fix offset for hlos1_vote_turing_mmu_tbu0_gdscShawn Guo
It looks that the offset 0x7d060 is a copy & paste from above hlos1_vote_turing_mmu_tbu1_gdsc. Correct it to 0x7d07c as per downstream kernel. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210919022308.24046-1-shawn.guo@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-15 10:01:59 +0000