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path: root/drivers/clk
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2023-01-10clk: qcom: clk-alpha-pll: define alias of LUCID OLE reset ops to EVO reset opsNeil Armstrong
Add an alias of LUCID OLE reset ops to EVO reset ops similar to other aliases. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-2-8a03d348c572@linaro.org
2023-01-10Merge tag '1672656511-1931-1-git-send-email-quic_akhilpo@quicinc.com' into ↵Bjorn Andersson
clk-for-6.3 v6.2-rc1 + 1672656511-1931-1-git-send-email-quic_akhilpo@quicinc.com
2023-01-10clk: qcom: gdsc: Support 'synced_poweroff' genpd flagAkhil P Oommen
Add support for the newly added 'synced_poweroff' genpd flag. This allows some clients (like adreno gpu driver) to request gdsc driver to ensure a votable gdsc (like gpucc cx gdsc) has collapsed at hardware. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102161757.v5.2.Ic128c1df50b7fc9a6b919932a3b41a799b5ed5e8@changeid
2023-01-10clk: qcom: sdm845: Use generic clk_sync_state_disable_unused callbackAbel Vesa
By adding the newly added clk_sync_state_disable_unused as sync_state callback to all sdm845 clock providers, we make sure that no clock belonging to these providers gets disabled on clk_disable_unused, but rather they are disabled on sync_state, when it is safe, since all the consumers build as modules have had their chance of enabling their own clocks. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221227204528.1899863-2-abel.vesa@linaro.org
2023-01-10clk: Add generic sync_state callback for disabling unused clocksAbel Vesa
There are unused clocks that need to remain untouched by clk_disable_unused, and most likely could be disabled later on sync_state. So provide a generic sync_state callback for the clock providers that register such clocks. Then, use the same mechanism as clk_disable_unused from that generic callback, but pass the device to make sure only the clocks belonging to the current clock provider get disabled, if unused. Also, during the default clk_disable_unused, if the driver that registered the clock has the generic clk_sync_state_disable_unused callback set for sync_state, skip disabling its clocks. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221227204528.1899863-1-abel.vesa@linaro.org
2023-01-10clk: qcom: rpmh: add clocks for sa8775pBartosz Golaszewski
Extend the driver with a description of clocks for sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109174511.1740856-6-brgl@bgdev.pl
2023-01-10clk: qcom: krait-cc: fix wrong pointer passed to IS_ERR()Yang Yingliang
It should be 'mux' passed to IS_ERR/PTR_ERR(). Fixes: 56a655e1c41a ("clk: qcom: krait-cc: convert to parent_data API") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104080235.1748953-1-yangyingliang@huawei.com
2023-01-09clk: at91: do not compile dt-compat.c for sama7g5 and sam9x60Claudiu Beznea
There is no need to have dt-compat.c compiled for SAMA7G5 and SAM9X60 as there is no in kernel device tree that could use it. Thus avoid compiling dt-compat.c for them. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221208114515.35179-4-claudiu.beznea@microchip.com
2023-01-09clk: at91: mark ddr clocks as criticalClaudiu Beznea
Mark DDR clocks as critical for AT91 devices. These clocks are enabled by bootloader when initializing DDR and needs to stay enabled. Up to this patch the DDR clocks were requested from drivers/memory/atmel-sdramc.c which does only clock request and enable. There is no need to have a separate driver just for this, thus the atmel-sdramc.c will be deleted in a subsequent patch. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221208114515.35179-2-claudiu.beznea@microchip.com
2023-01-08clk: sunxi-ng: d1: Add CAN bus gates and resetsFabien Poussin
The D1 CCU contains gates and resets for two CAN buses. While the CAN bus controllers are only documented for the T113 SoC, the CCU is the same across all SoC variants. Signed-off-by: Fabien Poussin <fabien.poussin@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221231231429.18357-7-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: d1: Mark cpux clock as criticalAndrás Szemző
Some SoCs in the D1 family feature ARM CPUs instead of a RISC-V CPU. In that case, the CPUs are driven from the 'cpux' clock, so it needs to be marked as critical, since there is no consumer when DVFS is disabled. This matches the drivers for other SoCs, and the "riscv" clock in this driver. Signed-off-by: András Szemző <szemzo.andras@gmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221231231429.18357-5-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: d1: Allow building for R528/T113Samuel Holland
Allwinner released some 32-bit ARM (sun8i) SoCs which use the same CCU as D1. Allow them to reuse the driver. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221231231429.18357-4-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: Move SoC driver conditions to dependenciesSamuel Holland
Do not duplicate the same expression on the `default` line, so the two lines do not need to be kept in sync. Drivers stay disabled under COMPILE_TEST because of the `default ARCH_SUNXI` applied to SUNXI_CCU. Three drivers had no conditions. - SUN6I_RTC_CCU and SUN8I_DE2_CCU are used on current hardware regardless of CPU architecture. - SUN8I_R_CCU is only used on pre-H6 SoCs, which means no RISCV SoCs. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221231231429.18357-3-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependenciesSamuel Holland
SUNXI_CCU already depends on ARCH_SUNXI, so adding the dependency to individual SoC drivers is redundant. Drivers stay disabled under COMPILE_TEST because of the `default ARCH_SUNXI` applied to SUNXI_CCU. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221231231429.18357-2-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: Avoid computing the rate twiceSamuel Holland
The ccu_*_find_best() functions already compute a best_rate at the same time as the other factors. Return this value so the caller does not need to duplicate the computation. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20221231173055.42384-1-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clockSamuel Holland
The DRAM controller clock is only allowed to change frequency while the DRAM chips are in self-refresh. To support this, changes to the CLK_DRAM mux and divider have no effect until acknowledged by the memory dynamic frequency scaling (MDFS) hardware inside the DRAM controller. (There is a SDRCLK_UPD bit in DRAM_CFG_REG which should serve a similar purpose, but this bit actually does nothing.) However, the MDFS hardware in H3 appears to be broken. Triggering a frequency change using the procedure from similar SoCs (A64/H5) hangs the hardware. Additionally, the vendor BSP specifically avoids using the MDFS hardware on H3, instead performing all DRAM PHY parameter updates and resets in software. Thus, it is effectively impossible to change the CLK_DRAM mux/divider, so those features should not be modeled. Add CLK_SET_RATE_PARENT so frequency changes apply to PLL_DDR instead. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20221229042230.24532-1-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-08clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issuesRandy Dunlap
Use '-' to separate the function name and its description. Use '%' on constants in kernel-doc notation. Use the kernel-doc Return: format for function return values. Fixes this warning: ccu_mmc_timing.c:21: warning: No description found for return value of 'sunxi_ccu_set_mmc_timing_mode' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Yang Li <yang.lee@linux.alibaba.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: Samuel Holland <samuel@sholland.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20221122184844.6794-1-rdunlap@infradead.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-06clk: qcom: Add TCSR clock driver for SM8550Abel Vesa
The TCSR clock controller found on SM8550 provides refclks for PCIE, USB and UFS. Add clock driver for it. This patch is based on initial code downstream. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104093450.3150578-5-abel.vesa@linaro.org
2023-01-06clk: qcom: rpmh: Add support for SM8550 rpmh clocksAbel Vesa
Adds the RPMH clocks present in SM8550 SoC. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104093450.3150578-4-abel.vesa@linaro.org
2022-12-29clk: qcom: dispcc-sm6125: Fix compatible string to match bindingsMarijn Suijten
According to generic rules the SoC name should be first: arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: clock-controller@5f00000: compatible: 'oneOf' conditional failed, one must be fixed: 'qcom,dispcc-sm6125' does not match '^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$' And this is already reflected by the bindings submitted prior to the addition of this driver. Any DTS following these rules will end up with a non-probing driver because of this mismatch. Fixes: 6e87c8f07407 ("clk: qcom: Add display clock controller driver for SM6125") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221222210140.278077-1-marijn.suijten@somainline.org
2022-12-28clk: qcom: Add camera clock controller driver for SM6350Konrad Dybcio
Add support for the camera clock controller found on SM6350. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221213152617.296426-2-konrad.dybcio@linaro.org
2022-12-28clk: qcom: smd-rpm: remove usage of platform nameDmitry Baryshkov
Now that all clocks have individual names, remove the names of SoCs from the SMD RPM clock definitions. Replace it with the common clk_smd_rpm_ prefix. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-20-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: rename SMD_RPM_BUS clocksDmitry Baryshkov
Add special macro for the clocks of QCOM_SMD_RPM_BUS_CLK type. Use it to insert the _bus_N part into the clock symbol name. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-19-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: rename the qcm2290 rf_clk3 clocksDmitry Baryshkov
Rename the qcm2290_rf_clk3 clocks adding 38m4 prefix to distinguish it from the common (19.2 MHz) rf_clk3. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-18-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: rename SMD_RPM_BRANCH clock symbolsDmitry Baryshkov
To ease distinguishing between branch and non-branch clocks (e.g. aggre1_noc, aggre2_noc and qdss) add '_branch' to all SMD_RPM_BRANCH* clocks. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-17-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: simplify SMD_RPM/_BRANCH/_QDSS clock definitionsDmitry Baryshkov
Remove the duplication between the names of the normal and active-only clocks by moving common sufixes to the clock definition macros. This simplifies adding new clock definitions and reviewing existing defs. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-16-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: simplify XO_BUFFER clocks definitionsDmitry Baryshkov
Remove the duplication between the names of the normal and active-only XO_BUFFER and XO_BUFFER_PINCTRL clocks by using preprocessor logic to add _a suffix. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-15-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: rename some msm8974 active-only clocksDmitry Baryshkov
Rename msm8974_diff_a_clk, msm8974_div_a_clk1 and msm8974_div_a_clk2 to move the _a suffix to the end of the name. This follows the pattern used by other active-only clocks and thus makes it possible to simplify clock definitions. This changes the userspace-visible names for this clocks. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-14-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: move clock definitions togetherDmitry Baryshkov
To ease review and reuse group all clock definitions together. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-13-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: fix alignment of line breaking backslashesDmitry Baryshkov
The commit 52a436e0b7fe ("clk: qcom: smd-rpm: Switch to parent_data") introduced ragged right alignment for the line breaking backslash. Fix it to make the code look consistently. Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-12-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: drop the rpm_status_id fieldDmitry Baryshkov
The rpm_status_id field is a leftover from the non-SMD clocks. It is of no use for the SMD-RPM clock driver and is always equal to zero. Drop it completely. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-11-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: add XO_BUFFER clock for each XO_BUFFER_PINCTRL clockDmitry Baryshkov
For each XO_BUFFER_PINCTRL there is a corresponding XO_BUFFER clock. Add them automatically to drop the duplication between the clock definitions. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-10-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: remove duplication between sm6375 and sm6125 clocksDmitry Baryshkov
Reuse sm6125's MMAXI clocks for sm6375. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-9-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: rename msm8992_ln_bb_* clocks to qcs404_ln_bb_*Dmitry Baryshkov
For each of XO_BUFFER_PINCTRL clocks there is a corresponding XO_BUFFER clock with the similar name (e.g. msm8998_ln_bb_clk3_pin vs msm8998_ln_bb_clk3). For qcs404_ln_bb_clk_pin there is no qcs404_ln_bb_clk, since the msm8992_ln_bb_clk was used instead (even for qcs404 platform). Follow the usual practice and rename msm8992_ln_bb_clk clocks to qcs404_ln_bb_clk (and rename active-only clock in a similar way). This is a preparation step for the next patch, which will merge XO_BUFFER and XO_BUFFER_PINCTRL definitions. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-8-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: use msm8998_ln_bb_clk2 for qcm2290 SoCDmitry Baryshkov
The qcm2290's ln_bb_clk2 is identical to the freshly added msm8998's ln_bb_clk2 one. Use the latter and drop the SoC-specific version. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-7-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: add missing ln_bb_clkN clocksDmitry Baryshkov
Newer platforms (msm8998, sdm660, sm6125) have low noise LN_BB_CLKn clocks. The driver already uses proper clock indices (RPM_SMD_LN_BB_CLKn). Fix clock names used by these platforms. Fixes: a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical entries") Fixes: edeb2ca74716 ("clk: qcom: smd: Add support for SM6125 rpm clocks") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-6-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: remove duplication between qcs404 and qcm2290 clocksDmitry Baryshkov
Reuse qcs404's QPIC and BIMC_GPU clock for qcm2290. Fixes: 78b727d02815 ("clk: qcom: smd-rpm: Add QCM2290 RPM clock support") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-5-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: remove duplication between MMXI and MMAXI definesDmitry Baryshkov
The commit 644c42295592 ("clk: qcom: smd: Add SM6375 clocks") added a duplicate of the existing define QCOM_SMD_RPM_MMAXI_CLK, drop it now. Fixes: 644c42295592 ("clk: qcom: smd: Add SM6375 clocks") Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-4-dmitry.baryshkov@linaro.org
2022-12-28clk: qcom: smd-rpm: enable pin-controlled ln_bb_clk clocks on qcs404Dmitry Baryshkov
The commit eaeee28db289 ("clk: qcom: smd: Add support for QCS404 rpm clocks") defined the pin-controlled ln_bb_clk clocks, but didn't add them to the qcs404_clks array. Add them to make these clocks usable to platform devices. Fixes: eaeee28db289 ("clk: qcom: smd: Add support for QCS404 rpm clocks") Reviewed-by: Alex Elder <elder@linaro.org? Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-3-dmitry.baryshkov@linaro.org
2022-12-27clk: qcom: gcc-sm6115: Use floor_ops for SDCC1/2 core clkKonrad Dybcio
Just like in case of other SoCs change SDCC1/SDCC2 ops to floor to avoid overclocking the controller. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Iskren Chernev <me@iskren.info> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209123910.178609-1-konrad.dybcio@linaro.org
2022-12-27clk: qcom: gcc-qcs404: add support for GDSCsDmitry Baryshkov
Add support for two GDSCs provided by this clock controller. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-13-dmitry.baryshkov@linaro.org
2022-12-27clk: qcom: gcc-qcs404: sort out the cxo clockDmitry Baryshkov
The GCC driver registers the cxo clock as a thin wrapper around board's xo_board clock. Nowadays we can use the xo_board directly in all the clocks that use it. Use the fw_name "cxo" for this clock. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-12-dmitry.baryshkov@linaro.org
2022-12-27clk: qcom: gcc-qcs404: use parent_hws/_data instead of parent_namesDmitry Baryshkov
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-11-dmitry.baryshkov@linaro.org
2022-12-27clk: qcom: gcc-qcs404: move PLL clocks upDmitry Baryshkov
Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-10-dmitry.baryshkov@linaro.org
2022-12-27clk: qcom: gcc-qcs404: get rid of the test clockDmitry Baryshkov
The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-9-dmitry.baryshkov@linaro.org
2022-12-27clk: qcom: gcc-qcs404: fix the name of the HDMI PLL clockDmitry Baryshkov
The QCS404 uses 28nm HDMI PHY. The in-kernel driver doesn't provide the PLL (yet), but the out of tree patches used the name "hdmi_pll" for it. Other Qualcomm HDMI PHYs use either the name "hdmi_pll" (8960) or "hdmipll" (8996). Thus change the expected HDMI PLL clock name to "hdmi_pll". Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-8-dmitry.baryshkov@linaro.org
2022-12-27clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parentsDmitry Baryshkov
The QCS404 uses 28nm LPM DSI PHY, which registers dsi0pll and dsi0pllbyte clocks. Fix all DSI PHY clock names used as parents inside the GCC driver. Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-7-dmitry.baryshkov@linaro.org
2022-12-27clk: qcom: gcc-qcs404: disable gpll[04]_out_aux parentsDmitry Baryshkov
On the QCS404 platform the driver for the Global Clock Controller doens't define gpll0_out_aux and gpll4_out_aux clocks, so it's not possible to use them as parents. Remove entries for these clocks. Note: backporting this patch to earlier kernels would also require a previous patch which switches the gcc driver to use ARRAY_SIZE for parent data arrays. Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-6-dmitry.baryshkov@linaro.org
2022-12-27clk: qcom: gcc-qcs404: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data/names/hws easy and errorproof. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-5-dmitry.baryshkov@linaro.org
2022-12-27clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entriesPhil Edworthy
Add SDHI/eMMC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221213230129.549968-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2025-09-11 14:57:06 +0000