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path: root/drivers/clk
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2022-06-22clk: Fix pointer casting to prevent oops in devm_clk_release()Uwe Kleine-König
The release function is called with a pointer to the memory returned by devres_alloc(). I was confused about that by the code before the generalization that used a struct clk **ptr. Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Fixes: abae8e57e49a ("clk: generalize devm_clk_get() a bit") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20220620171815.114212-1-u.kleine-koenig@pengutronix.de Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-17clk: renesas: r8a779f0: Add HSCIF clocksWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220614094937.8104-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17clk: renesas: r8a779f0: Add PCIe clocksYoshihiro Shimoda
Add the module clocks used by the PCIe controllers on the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220613115627.2831257-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-17clk: renesas: r8a779f0: Add Z0 and Z1 clock supportGeert Uytterhoeven
Add support for the Z0 and Z1 (Cortex-A55 Sub-System 0 (CPU 0-3) and Sub-System 1 (CPU 4-7)) clocks on R-Car S4-8, based on the existing support for Z clocks on R-Car Gen4. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/43009e25be1223a717e00c392cb2d416f5d47032.1654695893.git.geert+renesas@glider.be
2022-06-16clk: imx: clk-fracn-gppll: Add more freq config for video pllPeng Fan
Add the [484,498,445.3]MHz frequency support that will be used by video subsystem on imx93. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220609132902.3504651-8-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2022-06-16clk: imx: clk-fracn-gppll: correct rdivPeng Fan
According to Reference Manual: 000b - Divide by 1 001b - Divide by 1 010b - Divide by 2 011b - Divide by 3 100b - Divide by 4 101b - Divide by 5 110b - Divide by 6 111b - Divide by 7 So only need increase rdiv by 1 when the register value is 0. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220609132902.3504651-7-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2022-06-16clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate()Liu Ying
The PLL parameters in rate table should be directly compared with those read from PLL registers instead of the cooked ones. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220609132902.3504651-6-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2022-06-16clk: imx: clk-fracn-gppll: fix mfd valuePeng Fan
According to spec: A value of 0 is disallowed and should not be programmed in this register Fix to 1. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220609132902.3504651-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2022-06-16clk: imx93: Correct the edma1's parent clockJacky Bai
For EDMA1 in AONMIX, its parent clock should be from cm33_root, so Correct it. Fixes: 24defbe194b65("clk: imx: add i.MX93 clk") Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220609132902.3504651-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2022-06-16clk: imx93: correct nic_media parentPeng Fan
NIC_MEDIA sources from media_axi_root, not media_apb_root. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220609132902.3504651-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2022-06-16clk: imx93: use adc_root as the parent clock of adc1Haibo Chen
When debug, find after system boot up, all adc register operation will trigger system hang, this is because the internal adc ipg clock is gate off. In dts, only reference the IMX93_CLK_ADC1_GATE, which is adc1, no one touch the adc_root, so adc_root will be gate off automatically after system boot up. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220609132902.3504651-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2022-06-16clk: ti: Stop using legacy clkctrl names for omap4 and 5Tony Lindgren
With the addition of clock-output-names, we can now unify the internal clock naming for omap4 and 5 to follow the other TI SoCs. We are still using legacy clkctrl names for omap4 and 5 based on the clock manager name which is wrong. Instead, we want to use the clkctrl clock based naming. We must now also drop the legacy TI_CLK_CLKCTRL_COMPAT quirk for the clkctrl clock. This change will allow further devicetree warning cleanup as already done for am3/4 and dra7. Cc: linux-clk@vger.kernel.org Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <kristo@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220615064306.22254-1-tony@atomide.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()Uwe Kleine-König
The clk API just got a function with a slightly different name and the same functionality. Remove the duplication. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20220520075737.758761-5-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: Provide new devm_clk helpers for prepared and enabled clocksUwe Kleine-König
When a driver keeps a clock prepared (or enabled) during the whole lifetime of the driver, these helpers allow to simplify the drivers. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alexandru Ardelean <aardelean@deviqon.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20220520075737.758761-4-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: generalize devm_clk_get() a bitUwe Kleine-König
Allow to add an exit hook to devm managed clocks. Also use clk_get_optional() in devm_clk_get_optional instead of open coding it. The generalisation will be used in the next commit to add some more devm_clk helpers. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alexandru Ardelean <aardelean@deviqon.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20220520075737.758761-3-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Add infra_ao reset support for MT8186Rex-BC Chen
The infra_ao reset is needed for MT8186. - Add mtk_clk_rst_desc for MT8186. - Add register reset controller function for MT8186 infra_ao. - Add infra_ao_idx_map for MT8186. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-20-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195Rex-BC Chen
The infra_ao reset is needed for MT8192 and MT8195. - Add mtk_clk_rst_desc for MT8192 and MT8195 - Add register reset controller function for MT8192 infra_ao. - Move definition of infra reset from cl-mt8183.c to reset.h because it's the same definition with MT8192 and MT8195. - Add new definition of infra reset_4 for MT8192 and MT8195. - Add infra_ao_idx_map for MT8192 and MT8195. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> [Nícolas: Test for MT8192] Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-15-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Add reset support for simple probeRex-BC Chen
- Add a pointer of "mtk_clk_rst_desc" to "mtk_clk_desc". - Add register reset with device function in mtk_clk_simple_probe(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-12-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen
Using device to register reset controller is a better implementation in current drivers. Howerver, some clock drviers of MediaTek only provide device_node. Therefore, we still remain the register reset function with device_node and add a new function with device to register reset controller. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-11-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Change return type for clock reset register functionRex-BC Chen
To deal with error handling, we change the function return type from void to int for mtk_clk_register_rst_ctrl(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-10-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Support inuput argument index modeRex-BC Chen
There is a large number of mediatek infra reset bits, but we do not use all of them. In addition, the proper input argement of reset controller soulde be index. Therefore, to be compatible with previous drivers and usage, we add description variables to store the ids which can mapping to index. To use this mode, we need to put the id in rst_idx_map to map from index to ids. For example, if we want to input index 1 (this index is used to set bank 1 bit 14) for svs, we need to declare the reset controller like this: In drivers: static u16 rst_ofs[] = { 0x120, 0x130, 0x140, 0x150, 0x730, }; static u16 rst_idx_map[] = { 0 * 32 + 0, 1 * 32 + 14, .... }; static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SET_CLR, .rst_bank_ofs = rst_ofs, .rst_bank_nr = ARRAY_SIZE(rst_ofs), .rst_idx_map = rst_idx_map, .rst_idx_map_nr = ARRAY_SIZE(rst_idx_map), }; In dts: svs: { ... resets = <&infra 1>; ... }; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-9-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen
The bank offsets are not serial for all reset registers. For example, there are five infra reset banks for MT8192: 0x120, 0x130, 0x140, 0x150 and 0x730. To support this, - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of the reset register. - Add a new define RST_NR_PER_BANK to define reset number for each reset bank. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen
To declare the reset data easier, we add a strucure to do this instead of using many input variables to mtk_register_reset_controller(). - Add mtk_clk_rst_desc to define the reset description when registering the reset controller. - Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store data of reset controller. - Document mtk_clk_rst_desc and mtk_clk_rst_data. - Modify the documentation of mtk_register_reset_controller. - Extract container_of in update functions to to_mtk_clk_rst_data(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-7-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen
There are two versions for clock reset register control for MediaTek SoCs. The old hardware is one bit per reset control, and does not have separate registers for bit set, clear and read-back operations. This matches the scheme supported by the simple reset driver. However, because we need to use different data structure from reset_simple_data, we can not use the operation of simple reset driver. For this reason, we keep the original functions and name this version as "MTK_RST_SIMPLE". In this patch: - Add a version enumeration to separate different reset hardware. - Merge the reset register function of simple and set_clr into one function "mtk_register_reset_controller". - Rename input variable "num_regs" to "rst_bank_nr" to avoid confusion. This variable is used to define the quantity of reset bank. - Document mtk_reset_version and mtk_register_reset_controller. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-6-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Extract common drivers to update functionRex-BC Chen
To make drivers more clear and readable, we extract common code within assert and deassert to mtk_reset_update_set_clr() and mtk_reset_update(). Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-5-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Refine and reorder functions in reset.cRex-BC Chen
To make drivers more readable, we modify the indentation of the drivers and reorder the location of functions. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-4-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Fix written reset bit offsetRex-BC Chen
Original assert/deassert bit is BIT(0), but it's more resonable to modify them to BIT(id % 32) which is based on id. This patch will not influence any previous driver because the reset is only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0. Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-3-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-15clk: mediatek: reset: Add reset.hRex-BC Chen
Add a new file "reset.h" to place some definitions for clock reset. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-2-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-13clk: renesas: rza1: Remove struct rz_cpgGeert Uytterhoeven
The register block base pointer as stored in the reg member of the rz_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to rz_cpg_register_clock(). After this, the data member is the only remaining member of the rz_cpg structure, so the whole structure can be replaced by the data member. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/2380285576edaa4ad3dc5eca7e0ca418f068c6ef.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: r8a7779: Remove struct r8a7779_cpgGeert Uytterhoeven
All but the data member of the r8a7779_cpg structure are unused, so the whole structure can be replaced by the single member used. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/eb94c0f6c54a4f3a7e0e07f12781333a700c0a05.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: r8a7778: Remove struct r8a7778_cpgGeert Uytterhoeven
All but the data member of the r8a7778_cpg structure are unused, so the whole structure can be replaced by the single member used. Remove the mapping of the CPG registers, as no code uses the mapped registers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/4123c1c40a901195f00a825d434553d2052829aa.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: sh73a0: Remove sh73a0_cpg.regGeert Uytterhoeven
The register block base pointer as stored in the reg member of the sh73a0_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to sh73a0_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/5423e43d0cf518691965412fb510097d23ac5955.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: r8a7740: Remove r8a7740_cpg.regGeert Uytterhoeven
The register block base pointer as stored in the reg member of the r8a7740_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to r8a7740_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/7ec676bcc36ef1eda02c2db328c527fc5fd44e99.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: r8a73a4: Remove r8a73a4_cpg.regGeert Uytterhoeven
The register block base pointer as stored in the reg member of the r8a73a4_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to r8a73a4_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f835f3dfcf3bf754065e5002663952cc6341caac.1654694831.git.geert+renesas@glider.be
2022-06-13clk: renesas: r8a779f0: Add SDHI0 clockWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220603233437.21819-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-13clk: renesas: r8a779f0: Add thermal clockWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220525151130.24103-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-12platform/x86: Drop the PMC_ATOM Kconfig optionHans de Goede
The def_bool y PMC_ATOM Kconfig option provides a couple of symbols used by the code enabled by the X86_INTEL_LPSS option and it registers some clocks. These clocks are only registered on Bay Trail, Cherry Trail and Brasswell Intel SoCs and kernels targeting these SoCs must always have the X86_INTEL_LPSS option enabled otherwise many things will not work. Building the PMC_ATOM code on kernels which are not targeting the mentioned SoCs and which do not have the X86_INTEL_LPSS enabled is not useful. This means that we can simplify things by replacing the PMC_ATOM Kconfig option in Makefiles with X86_INTEL_LPSS and then drop the option. Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220503140207.101218-2-hdegoede@redhat.com
2022-06-10treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULEThomas Gleixner
Based on the normalized pattern: this program is free software you can redistribute it and/or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed as is without any warranty of any kind whether express or implied without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-10treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE ↵Thomas Gleixner
(part 2) Based on the normalized pattern: this file is licensed under the terms of the gnu general public license version 2 this program is licensed as is without any warranty of any kind whether express or implied extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-10treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE ↵Thomas Gleixner
(part 1) Based on the normalized pattern: this program is free software you can redistribute it and/or modify it under the terms of the gnu general public license as published by the free software foundation version 2 this program is distributed as is without any warranty of any kind whether express or implied without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-09clk: mediatek: Delete MT8192 msdc gateMatthias Brugger
The msdc gate is part of the MMC driver. Delete the not used code. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220523102339.21927-3-matthias.bgg@kernel.org Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-09clk: fixed: Remove Allwinner A10 special-case logicSamuel Holland
This compatible is part of the legacy sunxi clock support, and has not been used since commit 6b48644b1d29 ("ARM: gr8: Convert to CCU") in October 2016. Since supporting this compatible adds some overhead to generic clock code, let's clean it up. Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220531051742.43273-1-samuel@sholland.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-09clk: stm32: rcc_reset: Fix missing spin_lock_init()Wei Yongjun
The driver allocates the spinlock but not initialize it. Use spin_lock_init() on it to initialize it correctly. Fixes: 637cee5ffc71 ("clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20220608021154.990347-1-weiyongjun1@huawei.com Tested-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-06-07clk: renesas: rzg2l: Fix reset status functionBiju Das
As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means reset signal is not applied (deassert state) and 1 means reset signal is applied (assert state). reset_control_status() expects a positive value if the reset line is asserted. But rzg2l_cpg_status function returns zero for asserted state. This patch fixes the issue by adding double inverted logic, so that reset_control_status returns a positive value if the reset line is asserted. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220531071657.104121-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-06clk: sunxi-ng: Deduplicate ccu_clks arraysSamuel Holland
The ccu_clks arrays are used to link ccu_common objects to a platform device during probe. There is no requirement that the clk_hw inside the ccu_common object ever gets registered with the clock framework. So the drivers do not need a separate ccu_clks array for each CCU variant. A single array per driver, containing the union of the CCU clocks from all variants, is sufficient. Let's save some space by combining the ccu_clks arrays in each driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220531043539.41549-1-samuel@sholland.org
2022-06-06clk: renesas: r9a06g032: Fix UART clkgrp bitselRalph Siemsen
There are two UART clock groups, each having a mux to select its upstream clock source. The register/bit definitions for accessing these two muxes appear to have been reversed since introduction. Correct them so as to match the hardware manual. Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220518182527.1693156-1-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-06clk: renesas: r9a06g032: Drop some unused fieldsRalph Siemsen
Remove unused fields from struct r9a06g032_clkdesc. As the D_UGATE macro no longer uses _gi, drop it from all declarations. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220518172808.1691450-2-ralph.siemsen@linaro.org Link: https://lore.kernel.org/r/20220518172808.1691450-3-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-06clk: renesas: r9a09g011: Add WDT clock and reset entriesPhil Edworthy
Add WDT0 clock and reset entries to CPG driver. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220518150105.48167-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-06clk: renesas: r9a09g011: Add PFC clock and reset entriesPhil Edworthy
Add PFC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220518135208.39885-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-06clk: renesas: r9a07g044: Add POEG clock and reset entriesBiju Das
Add POEG clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220510110653.7326-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2025-09-14 21:23:01 +0000