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path: root/drivers/clk
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2019-09-17clk: imx: pll14xx: avoid glitch when set ratePeng Fan
According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to output unstable clock until lock time passes. PLL1416X/PLL1443XA may generate a glitch at FOUT." So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch. In the end of set rate, BYPASS will be cleared. When prepare clock, also need to take care to avoid glitch. So we also follow Spec to set BYPASS before RESETB changed from 0 to 1. And add a check if the RESETB is already 0, directly return 0; Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lkml.kernel.org/r/1568043491-20680-2-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: mvebu: ap80x: add AP807 clock supportBen Peled
Add driver support for AP807 clock. Signed-off-by: Ben Peled <bpeled@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lkml.kernel.org/r/20190805100310.29048-9-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: mvebu: ap806: Prepare the introduction of AP807 clock supportBen Peled
Factor out the code that is only useful to AP806 so it will be easier to support AP807. No functional changes. Signed-off-by: Ben Peled <bpeled@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lkml.kernel.org/r/20190805100310.29048-8-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driverOmri Itach
Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK is half the rate of DDR clock, so its derrived from Sample At Reset configuration. The clock frequency is required for AP806 AXI monitor profiling feature. Signed-off-by: Omri Itach <omrii@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lkml.kernel.org/r/20190805100310.29048-7-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: mvebu: ap806: be more explicit on what SaR isMiquel Raynal
"SaR" means Sample at Reset. DIP switches can be changed on the board, their states at reset time is available through a register read. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lkml.kernel.org/r/20190805100310.29048-6-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: mvebu: ap80x-cpu: add AP807 CPU clock supportBen Peled
Enhance the ap-cpu-clk driver to support both AP806 and AP807 CPU clocks. Signed-off-by: Ben Peled <bpeled@marvell.com> [<miquel.raynal@bootlin.com>: use device data instead of conditions on the compatible] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lkml.kernel.org/r/20190805100310.29048-5-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clockChristine Gharzuzi
This patch allows same flow to be executed on chips with different register mappings like AP806 and, in the future, AP807. Note: this patch has no functional effect, and only prepares the driver for additional chips to be supported by retrieving the right device data depenging on the compatible property. Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lkml.kernel.org/r/20190805100310.29048-4-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: sprd: add missing kfreeChunyan Zhang
The number of config registers for different pll clocks probably are not same, so we have to use malloc, and should free the memory before return. Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support") Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com> Link: https://lkml.kernel.org/r/20190905103009.27166-1-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: at91: allow 24 Mhz clock as input for PLLEugen Hristev
The PLL input range needs to be able to allow 24 Mhz crystal as input Update the range accordingly in plla characteristics struct Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: Make clk_bulk_get_all() return a valid "id"Bjorn Andersson
The adreno driver expects the "id" field of the returned clk_bulk_data to be filled in with strings from the clock-names property. But due to the use of kmalloc_array() in of_clk_bulk_get_all() it receives a list of bogus pointers instead. Zero-initialize the "id" field and attempt to populate with strings from the clock-names property to resolve both these issues. Fixes: 616e45df7c4a ("clk: add new APIs to operate on all available clocks") Fixes: 8e3e791d20d2 ("drm/msm: Use generic bulk clock function") Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20190913024029.2640-1-bjorn.andersson@linaro.org Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: actions: Fix factor clk struct member accessManivannan Sadhasivam
Since the helper "owl_factor_helper_round_rate" is shared between factor and composite clocks, using the factor clk specific helper function like "hw_to_owl_factor" to access its members will create issues when called from composite clk specific code. Hence, pass the "factor_hw" struct pointer directly instead of fetching it using factor clk specific helpers. This issue has been observed when a composite clock like "sd0_clk" tried to call "owl_factor_helper_round_rate" resulting in pointer dereferencing error. While we are at it, let's rename the "clk_val_best" function to "owl_clk_val_best" since this is an owl SoCs specific helper. Fixes: 4bb78fc9744a ("clk: actions: Add factor clock support") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190916154546.24982-2-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: qcom: rcg: Return failure for RCG updateTaniya Das
In case of update config failure, return -EBUSY, so that consumers could handle the failure gracefully. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1557339895-21952-2-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: remove extra ---help--- tags in KconfigLubomir Rintel
Sometimes an extraneous "---help---" follows "help". That is probably a copy&paste error stemming from their inconsistent use. Remove those. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20190822093126.594013-1-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: Evict unregistered clks from parent cachesStephen Boyd
We leave a dangling pointer in each clk_core::parents array that has an unregistered clk as a potential parent when that clk_core pointer is freed by clk{_hw}_unregister(). It is impossible for the true parent of a clk to be set with clk_set_parent() once the dangling pointer is left in the cache because we compare parent pointers in clk_fetch_parent_index() instead of checking for a matching clk name or clk_hw pointer. Before commit ede77858473a ("clk: Remove global clk traversal on fetch parent index"), we would check clk_hw pointers, which has a higher chance of being the same between registration and unregistration, but it can still be allocated and freed by the clk provider. In fact, this has been a long standing problem since commit da0f0b2c3ad2 ("clk: Correct lookup logic in clk_fetch_parent_index()") where we stopped trying to compare clk names and skipped over entries in the cache that weren't NULL. There are good (performance) reasons to not do the global tree lookup in cases where the cache holds dangling pointers to parents that have been unregistered. Let's take the performance hit on the uncommon registration path instead. Loop through all the clk_core::parents arrays when a clk is unregistered and set the entry to NULL when the parent cache entry and clk being unregistered are the same pointer. This will fix this problem and avoid the overhead for the "normal" case. Based on a patch by Bjorn Andersson. Fixes: da0f0b2c3ad2 ("clk: Correct lookup logic in clk_fetch_parent_index()") Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190828181959.204401-1-sboyd@kernel.org
2019-09-17clk: mediatek: Runtime PM support for MT8183 mcucfg clock providerWeiyi Lu
Enable the runtime PM support and forward the struct device pointer for registration of MT8183 mcucfg clocks. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Link: https://lkml.kernel.org/r/1567414859-3244-3-git-send-email-weiyi.lu@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: mediatek: Register clock gate with deviceWeiyi Lu
Allow those clocks under a power domain to do the runtime pm operation by forwarding the struct device pointer from clock provider. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Link: https://lkml.kernel.org/r/1567414859-3244-2-git-send-email-weiyi.lu@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: mediatek: add pericfg clocks for MT8183Chunfeng Yun
Add pericfg clocks for MT8183, it's used when support USB remote wakeup Cc: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lkml.kernel.org/r/1566980533-28282-2-git-send-email-chunfeng.yun@mediatek.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: bcm2835: Mark PLLD_PER as CRITICALStefan Wahren
The VPU firmware assume that the PLLD_PER isn't modified by the ARM core. Otherwise this could cause firmware lookups. So mark the clock as critical to avoid this. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-17clk: bcm2835: Add BCM2711_CLOCK_EMMC2 supportStefan Wahren
The new BCM2711 supports an additional clock for the emmc2 block. So add a new compatible and register this clock only for BCM2711. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-17clk: bcm2835: Introduce SoC specific clock registrationStefan Wahren
In order to support SoC specific clocks (e.g. emmc2 for BCM2711), we extend the description with a SoC support flag. This approach avoids long and mostly redundant lists of clock IDs. Since PLLH is specific to BCM2835, we register only rest of the clocks as common to all SoC. Suggested-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-16Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM DT updates from Arnd Bergmann: "This is another huge branch with close to 450 changessets related to devicetree files, roughly half of this for 32-bit and 64-bit respectively. There are lots of cleanups and additional hardware support for platforms we already support based on SoCs from Renesas, ST-Microelectronics, Intel/Altera, Rockchips, Allwinner, Broadcom and other manufacturers. A total of 6 new SoCs and 37 new boards gets added this time, one more SoC will come in a follow-up branch. Most of the new boards are for 64-bit ARM SoCs, the others are typically for the 32-bit Cortex-A7. Going more into details for SoC platforms with new hardware support: - The Snapdragon 855 (SM8150) is Qualcomm's current high-end phone platform, usually paired with an external 5G modem. So far we only support the Qualcomm SM8150 MTP reference platform, but no actual products. - For the slightly older Qualcomm platforms, support for several interesting products is getting added: Three laptops based on Snapdragon 835/MSM8998 (Asus NovaGo, HP Envy X2 and Lenovo Miix 630), one laptop based on Snapdragon 850/sdm850 (Lenovo Yoga C630) and several phones based on the older Snapdragon 410/MSM8916 (Samsung A3 and A5, Longcheer L8150 aka Android One 2nd gen "seed" aka Wileyfox Swift). - Mediatek MT7629 is a new wireless network router chip, similar to the older MT7623. It gets added together with the reference board implementation. - Allwinner V3 is a repackaged version of the existing low-end V3s chip, and is used in the tiny Lichee Pi Zero plus, also added here. There is also a new TV set-top box based on Allwinner H6, the Tanix TX6, and the eMMC variant of the Olimex A64-Olinuxino development board. - NXP i.MX8M Nano is a new member of the ever-expanding i.MX SoC family, similar to the i.MX8M Mini. As usual, there is a large number of new boards for i.MX SoCs: Einfochips i.MX8QXP AI_ML, SolidRun Hummingboard Pulse baseboard and System-on-Module, Boundary Devices i.MX8MQ Nitrogen8M, and TechNexion PICO-PI-IMX8M-DEV for the 64-bit i.MX8 line. For 32-bit, we get the Kontron i.MX6UL N6310 SoM with two baseboards, the PHYTEC phyBOARD-Segin SoM with three baseboards, and the Zodiac Inflight Innovations i.MX7 RMU2 board. - In a different NXP product line, the Layerscape LS1046A "Freeway" reference board gets added. - Amlogic SM1 (S905X3) and G12B (S922X, A311D) are updated chips from their set-top-box line and smart speaker with newer CPU and GPU cores compared to their predecessors. Both are now also supported by the Khadas VIM3 development board series, and the dts files for that get reorganized a bit to better deal with all variants. Another board based on SM1 that gets added is the SEI Robotics SEI610. - There are a handful of new x86 and Power9 server boards using Aspeed BMC chips that are gaining support for running Linux on the BMC through the OpenBMC project: Facebook Minipack/Wedge100/Wedge40, Lenovo Hr855xg2, and Mihawk. Notably these are still new machines using SoCs based on the ARM9 and ARM11 CPU cores, as support for the new Cortex-A7 based AST2600 is still ramping up. - There are three new end-user products using 32-bit Rockchips SoCs: Mecer Xtreme Mini S6 is an Android "mini PC" box based on the low-end RK3229 chip, while the two AOpen products Chromebox Mini (Fievel) and Chromebase Mini (Tiger) run ChromeOS and are meant for commercial settings(digital signage, PoS, ...). - One more single-board computer based on the popular 64-bit RK3399 is added: the Leez RK3399 P710" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (467 commits) arm64: dts: qcom: Add Lenovo Yoga C630 ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit ARM; dts: aspeed: mihawk: File should not be executable ARM: dts: aspeed: swift: Change power supplies to version 2 ARM: dts: aspeed: vesnin: Add secondary SPI flash chip ARM: dts: aspeed: vesnin: Add wdt2 with alt-boot option ARM: dts: aspeed-g4: Add all flash chips ARM: dts: exynos: Enable GPU/Mali T604 on Arndale board ARM: dts: exynos: Enable GPU/Mali T604 on Chromebook Snow ARM: dts: exynos: Add GPU/Mali T604 node to Exynos5250 ARM: dts: exynos: Fix min/max buck4 for GPU on Arndale board ARM: dts: exynos: Mark LDO10 as always-on on Peach Pit/Pi Chromebooks ARM: dts: exynos: Remove not accurate secondary ADC compatible arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328 arm64: dts: meson-sm1-sei610: add stdout-path property back arm64: dts: meson-sm1-sei610: enable DVFS arm64: dts: khadas-vim3: add support for the SM1 based VIM3L dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi arm64: dts: meson: g12a: add reset to tdm formatters ...
2019-09-16Merge tag 'armsoc-drivers' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "This contains driver changes that are tightly connected to SoC specific code. Aside from smaller cleanups and bug fixes, here is a list of the notable changes. New device drivers: - The Turris Mox router has a new "moxtet" bus driver for its on-board pluggable extension bus. The same platform also gains a firmware driver. - The Samsung Exynos family gains a new Chipid driver exporting using the soc device sysfs interface - A similar socinfo driver for Qualcomm Snapdragon chips. - A firmware driver for the NXP i.MX DSP IPC protocol using shared memory and a mailbox Other changes: - The i.MX reset controller driver now supports the NXP i.MX8MM chip - Amlogic SoC specific drivers gain support for the S905X3 and A311D chips - A rework of the TI Davinci framebuffer driver to allow important cleanups in the platform code - A couple of device drivers for removed ARM SoC platforms are removed. Most of the removals were picked up by other maintainers, this contains whatever was left" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (123 commits) bus: uniphier-system-bus: use devm_platform_ioremap_resource() soc: ti: ti_sci_pm_domains: Add support for exclusive and shared access dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access firmware: ti_sci: Allow for device shared and exclusive requests bus: imx-weim: remove incorrect __init annotations fbdev: remove w90x900/nuc900 platform drivers spi: remove w90x900 driver net: remove w90p910-ether driver net: remove ks8695 driver firmware: turris-mox-rwtm: Add sysfs documentation firmware: Add Turris Mox rWTM firmware driver dt-bindings: firmware: Document cznic,turris-mox-rwtm binding bus: moxtet: fix unsigned comparison to less than zero bus: moxtet: remove set but not used variable 'dummy' ARM: scoop: Use the right include dt-bindings: power: add Amlogic Everything-Else power domains bindings soc: amlogic: Add support for Everything-Else power domains controller fbdev: da8xx: use resource management for dma fbdev: da8xx-fb: drop a redundant if fbdev: da8xx-fb: use devm_platform_ioremap_resource() ...
2019-09-16clk: at91: select parent if main oscillator or bypass is enabledEugen Hristev
Selecting the right parent for the main clock is done using only main oscillator enabled bit. In case we have this oscillator bypassed by an external signal (no driving on the XOUT line), we still use external clock, but with BYPASS bit set. So, in this case we must select the same parent as before. Create a macro that will select the right parent considering both bits from the MOR register. Use this macro when looking for the right parent. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1568042692-11784-2-git-send-email-eugen.hristev@microchip.com Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-16clk: at91: fix update bit maps on CFG_MOR writeEugen Hristev
The regmap update bits call was not selecting the proper mask, considering the bits which was updating. Update the mask from call to also include OSCBYPASS. Removed MOSCEN which was not updated. Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1568042692-11784-1-git-send-email-eugen.hristev@microchip.com Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-12Merge branch 'aspeed/dt-3' into arm/lateArnd Bergmann
* aspeed/dt-3: ARM: dts: aspeed: Add AST2600 pinmux nodes ARM: dts: aspeed: Add AST2600 and EVB clk: Add support for AST2600 SoC clk: aspeed: Move structures to header clk: aspeed: Add SDIO gate
2019-09-09clk: mediatek: Add MT6779 clock supportmtk01761
Add MT6779 clock support, include topckgen, apmixedsys, infracfg, and subsystem clocks. Signed-off-by: mtk01761 <wendell.lin@mediatek.com> Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09clk: qcom: fix QCS404 TuringCC regmapJorge Ramirez-Ortiz
The max register is 0x23004 as per the manual (the current max_register that this commit is fixing is actually out of bounds). Fixes: 892df0191b29 ("clk: qcom: Add QCS404 TuringCC") Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Link: https://lkml.kernel.org/r/20190909085430.8700-1-jorge.ramirez-ortiz@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09clk: qcom: clk-rpmh: Add support for SM8150Vinod Koul
Add support for rpmh clocks found in SM8150 Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20190826173120.2971-5-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09clk: qcom: clk-rpmh: Convert to parent data schemeVinod Koul
Convert the rpmh clock driver to use the new parent data scheme by specifying the parent data for board clock. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20190826173120.2971-3-vkoul@kernel.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09clk: qcom: gcc: Use floor ops for SDCC clocksTaniya Das
Update global clock controller SDCC2/4 clocks to use the floor rcg ops, so as to use the rounded down clock rates for these clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20190909074410.18977-1-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09clk: qcom: gcc-qcs404: Use floor ops for sdcc clksVinod Koul
Update the gcc qcs404 clock driver to use floor ops for sdcc clocks. As disuccsed in [1] it is good idea to use floor ops for sdcc clocks as we dont want the clock rates to do round up. [1]: https://lore.kernel.org/linux-arm-msm/20190830195142.103564-1-swboyd@chromium.org/ Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20190906045659.20621-1-vkoul@kernel.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09clk: qcom: gcc-sdm845: Use floor ops for sdcc clksStephen Boyd
Some MMC cards fail to enumerate properly when inserted into an MMC slot on sdm845 devices. This is because the clk ops for qcom clks round the frequency up to the nearest rate instead of down to the nearest rate. For example, the MMC driver requests a frequency of 52MHz from clk_set_rate() but the qcom implementation for these clks rounds 52MHz up to the next supported frequency of 100MHz. The MMC driver could be modified to request clk rate ranges but for now we can fix this in the clk driver by changing the rounding policy for this clk to be round down instead of round up. Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") Reported-by: Douglas Anderson <dianders@chromium.org> Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lkml.kernel.org/r/20190830195142.103564-1-swboyd@chromium.org Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: Add support for AST2600 SoCJoel Stanley
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks than the previous iterations, so support is broken out into it's own driver. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lkml.kernel.org/r/20190825141848.17346-3-joel@jms.id.au [sboyd@kernel.org: Mark arrays const] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: aspeed: Move structures to headerJoel Stanley
They will be reused by the ast2600 driver. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lkml.kernel.org/r/20190825141848.17346-2-joel@jms.id.au Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk/ti: Use kmemdup rather than duplicating its implementationFuqian Huang
kmemdup is introduced to duplicate a region of memory in a neat way. Rather than kmalloc/kzalloc + memcpy, which the programmer needs to write the size twice (sometimes lead to mistakes), kmemdup improves readability, leads to smaller code and also reduce the chances of mistakes. Suggestion to use kmemdup rather than using kmalloc/kzalloc + memcpy. Signed-off-by: Fuqian Huang <huangfq.daxian@gmail.com> Link: https://lkml.kernel.org/r/20190703162700.32091-1-huangfq.daxian@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: clk-cdce925: Add regulator supportPhil Reid
The cdce925 power supplies could be controllable on some platforms. Enable them before communicating with the cdce925. Signed-off-by: Phil Reid <preid@electromag.com.au> Link: https://lkml.kernel.org/r/1561691950-42154-3-git-send-email-preid@electromag.com.au Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: fix devm_platform_ioremap_resource.cocci warningskbuild test robot
drivers/clk/bcm/clk-bcm63xx-gate.c:174:1-9: WARNING: Use devm_platform_ioremap_resource for hw -> regs Use devm_platform_ioremap_resource helper which wraps platform_get_resource() and devm_ioremap_resource() together. Generated by: scripts/coccinelle/api/devm_platform_ioremap_resource.cocci Fixes: 1c099779c1e2 ("clk: add BCM63XX gated clock controller driver") CC: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: kbuild test robot <lkp@intel.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> Link: https://lkml.kernel.org/r/alpine.DEB.2.21.1908081809160.2995@hadrien Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: spear: Make structure i2s_sclk_masks constantNishka Dasgupta
Static structure i2s_sclk_masks, having type aux_clk_masks, is only used when it is passed as the sixth argument to function clk_register_aux(). However, clk_register_aux() is defined with its sixth argument as const. Hence i2s_sclk_masks is not modified by clk_register_aux, which is also the only usage of the former. Therefore make i2s_sclk_masks constant as it is never modified. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Link: https://lkml.kernel.org/r/20190813085714.8079-1-nishkadg.linux@gmail.com Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'YueHaibing
drivers/clk/st/clkgen-pll.c:64:37: warning: st_pll3200c32_407_a0 defined but not used [-Wunused-const-variable=] It is never used, so can be removed. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20190816135523.73520-1-yuehaibing@huawei.com Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops'YueHaibing
drivers/clk/st/clkgen-fsyn.c:70:29: warning: st_quadfs_fs660c32_ops defined but not used [-Wunused-const-variable=] It is never used, so can be removed. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20190816135341.52248-1-yuehaibing@huawei.com Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-05clk: Document of_parse_clkspec() some moreStephen Boyd
The return value of of_parse_clkspec() is peculiar. If the function is called with a NULL argument for 'name' it will return -ENOENT, but if it's called with a non-NULL argument for 'name' it will return -EINVAL. This peculiarity is documented by commit 5c56dfe63b6e ("clk: Add comment about __of_clk_get_by_name() error values"). Let's further document this function so that it's clear what the return value is and how to use the arguments to parse clk specifiers. Cc: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190826212042.48642-1-sboyd@kernel.org Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
2019-09-05clk: rockchip: Add clock controller for the rk3308Finley Xiao
Add the clock tree definition for the new RK3308 SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-09-04Merge tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann
arm/late mvebu dt64 for 5.4 (part 2) Add support for Turris Mox board (Armada 3720 SoC based) * tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu: (53 commits) arm64: dts: marvell: add DTS for Turris Mox dt-bindings: marvell: document Turris Mox compatible arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl arm64: dts: marvell: Add cpu clock node on Armada 7K/8K arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes arm64: dts: marvell: Add CP110 COMPHY clocks arm64: dts: marvell: armada-37xx: add mailbox node dt-bindings: gpio: Document GPIOs via Moxtet bus drivers: gpio: Add support for GPIOs over Moxtet bus bus: moxtet: Add sysfs and debugfs documentation dt-bindings: bus: Document moxtet bus binding bus: Add support for Moxtet bus reset: Add support for resets provided by SCMI firmware: arm_scmi: Add RESET protocol in SCMI v2.0 dt-bindings: arm: Extend SCMI to support new reset protocol firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels ... Link: https://lore.kernel.org/r/87h85two0r.fsf@FE-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04Merge tag 'omap-for-v5.4/ti-sysc-sgx-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late SoC glue layer changes for SGX on omap variants for v5.4 For a while we've had omap4 sgx glue layer defined in dts and probed with ti-sysc driver. This allows idling the sgx module for PM, and removes the need for custom platform glue layer code for any further driver changes. We first drop the unused legacy platform data for omap4 sgx. Then for omap5, we need add the missing clkctrl clock data so we can configure sgx. And we configure sgx for omap34xx, omap36xx and am3517. For am335x, we still have a dependency for rstctrl reset driver changes, so that will be added later on. Note that this branch is based on earlier ti-sysc branch for omap36xx glue layer quirk handling. * tag 'omap-for-v5.4/ti-sysc-sgx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: ARM: dts: Configure interconnect target module for am3517sgx ARM: dts: Configure interconnect target module for omap3 sgx ARM: dts: Configure sgx for omap5 clk: ti: add clkctrl data omap5 sgx ARM: OMAP2+: Drop legacy platform data for omap4 gpu Link: https://lore.kernel.org/r/pull-1567016893-318461@atomide.com-4 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux ↵Greg Kroah-Hartman
into char-misc-next Georgi writes: interconnect patches for 5.4 Here are the interconnect driver updates for the 5.4-rc1 merge window. - New feature is the path tagging support that helps with grouping and aggregating the bandwidth requests into separate buckets based on a tag. - The first user of the path tagging is the Qualcomm sdm845 driver that now implements support for wake/sleep sets. This allows consumer drivers to express their bandwidth needs for the different CPU power states. - New interconnect driver for the qcs404 platforms and a driver that communicates bandwidth requests with remote processor over shared memory. - Cleanups and fixes. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> * tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux: drivers: qcom: Add BCM vote macro to header interconnect: qcom: remove COMPILE_TEST from CONFIG_INTERCONNECT_QCOM_QCS404 interconnect: qcom: Add QCS404 interconnect provider driver interconnect: qcom: Add interconnect RPM over SMD driver dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings interconnect: qcom: Add tagging and wake/sleep support for sdm845 interconnect: Add pre_aggregate() callback interconnect: Add support for path tags
2019-09-03Merge tag 'imx-dt-clkdep-5.4' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX device tree update with new clocks: - A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board device tree support. - Add DSP device tree support for i.MX8QXP SoC. * tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8qxp: Add DSP DT node arm64: dts: imx8mn: Add cpu-freq support arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support arm64: dts: imx8mn-ddr4-evk: Add i2c1 support arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support arm64: dts: imx8mn: Add gpio-ranges property arm64: dts: freescale: Add i.MX8MN dtsi support clk: imx8: Add DSP related clocks clk: imx: Add support for i.MX8MN clock driver clk: imx: Add API for clk unregister when driver probe fail clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage dt-bindings: imx: Add clock binding doc for i.MX8MN Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'amlogic-dt64' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.4 Highlights - new SoCs (G12B family): S922X, A311D - new SoCs (SM1 family): S905X3 - new board: SEI Robotics SEI610 (SM1/S905X3) - new board: Khadas VIM3 (G12B/A311D) - DVFS/CPUfreq support on G12[AB] family * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (40 commits) arm64: dts: add support for SM1 based SEI Robotics SEI610 dt-bindings: arm: amlogic: add SEI Robotics SEI610 bindings dt-bindings: arm: amlogic: add SM1 bindings arm64: dts: meson-g12b-odroid-n2: enable DVFS arm64: dts: meson-g12b-khadas-vim3: add initial device-tree dt-bindings: arm: amlogic: fix x96-max/sei510 section in amlogic.yaml arm64: dts: amlogic: g12 CPU timers stop in suspend arm64: dts: meson-g12b: support a311d and s922x cpu operating points dt-bindings: arm: amlogic: add support for the Khadas VIM3 dt-bindings: arm: amlogic: add bindings for the Amlogic G12B based A311D SoC dt-bindings: arm: amlogic: add bindings for G12B based S922X SoC arm64: dts: meson: add video decoder entries arm64: dts: meson-gx: add video decoder entry dt-bindings: media: amlogic,vdec: add default compatible arm64: dts: meson: add ethernet fifo sizes arm64: dts: meson-g12b: add cpus OPP tables arm64: dts: meson-g12a: enable DVFS on G12A boards arm64: dts: meson-g12a: add cpus OPP table arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi ... Link: https://lore.kernel.org/r/7hr25fbi4v.fsf@baylibre.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-08-26clk: ti: add clkctrl data omap5 sgxTony Lindgren
Looks like we have sgx clock missing currently so let's add it. Cc: Adam Ford <aford173@gmail.com> Cc: Filip Matijević <filip.matijevic.pz@gmail.com> Cc: "H. Nikolaus Schaller" <hns@goldelico.com> Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Cc: moaz korena <moaz@korena.xyz> Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Cc: Philipp Rossak <embed3d@gmail.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: linux-clk@vger.kernel.org Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-08-26clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocksNeil Armstrong
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by having a dedicate tree for each core similar to the CPU0 tree. Like the DSU tree, a supplementaty mux has been added to use the CPU0 frequency instead. But since the cluster only has a single power rail and shares a single PLL, it's not worth adding 3 unsused clock tree, so we add only the mux to select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores. They are set read-only because the early boot stages sets them to select the CPU0 input clock. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clockNeil Armstrong
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to the CPU clock tree with a supplementaty mux to select the CPU0 clock instead. Leave this as read-only since it's set up by the early boot stages. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
generated by cgit (git 2.34.1) at 2025-09-11 20:07:27 +0000