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path: root/drivers/clk
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2019-02-21clk: imx8mq: Fix the CLKO2 source select listFabio Estevam
The CLKO2 clock source select list is the following as per the i.MX8M Reference Manual: 000 - 25M_REF_CLK 001 - SYSTEM_PLL2_DIV5 010 - SYSTEM_PLL1_DIV2 011 - SYSTEM_PLL2_DIV6 100 - SYSTEM_PLL3_CLK 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL1_CLK 111 - 32K_REF_CLK However, in imx8mq_clko2_sels[] only the first four entries are correct. Fix it by adding the missing "sys3_pll2_out" entry in order to match the description from the manual. Fixes: b80522040cd3f ("clk: imx: Add clock driver for i.MX8MQ CCM") Reported-by: Rogerio Pimentel <rogerio.silva@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Add missing M4 clocksCarlo Caione
The clocks list is missing the clocks for the M4 core. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: Add clock driver support for imx8mmBai Ping
Add clock driver support for i.MX8MM SOC. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: Add PLLs driver for imx8mm socBai Ping
New PLLs are introduced on i.MX8M Mini SOC. PLL1416X is Integer PLL, PLL1443X is a Frac PLL. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx5: add imx5_SCC2_IPG_GATEMichael Grzeschik
This adds the missing clock for the SCC2 peripheral unit. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: scu: add set parent supportAisheng Dong
Add clk scu set parents support. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Remove le32_to_cpu() on get_parent op] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: scu: add fallback compatible string supportAisheng Dong
SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs. Make the driver support "fsl,scu-clk" fallback compatible string to allow other SoCs to reuse the common part. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Make parent names arrays const pointersAbel Vesa
The arrays containing the mux selectors need to be of const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: Make parents const pointer in mux wrappersAbel Vesa
The parents needs to be pointer to const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: Make parent_names const pointer in composite-8mAbel Vesa
The parent_names needs to be pointer to const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-20clk: at91: fix masterck nameAlexandre Belloni
The master clock is actually named masterck earlier in the driver. Having "mck" in the parent list means that it can never be selected. Fixes: 1eabdc2f9dd8 ("clk: at91: add at91sam9x5 PMCs driver") Fixes: a2038077de9a ("clk: at91: add sama5d2 PMC driver") Fixes: 084b696bb509 ("clk: at91: add sama5d4 pmc driver") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: <stable@vger.kernel.org> # v4.20+ Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-20clk: at91: fix at91sam9x5 peripheral clock numberAlexandre Belloni
nck() looks at the last id in an array and unfortunately, at91sam9x35_periphck has a sentinel, hence the id is 0 and the calculated number of peripheral clocks is 1 instead of a maximum of 31. Fixes: 1eabdc2f9dd8 ("clk: at91: add at91sam9x5 PMCs driver") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: <stable@vger.kernel.org> # v4.20+ Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-18clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' staticWei Yongjun
Fixes the following sparse warning: drivers/clk/tegra/clk-tegra124-dfll-fcpu.c:244:18: warning: symbol 'tegra210_cpu_cvb_tables' was not declared. Should it be static? Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'tegra-for-5.1-clk' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers clk: tegra: Changes for v5.1-rc1 This contains a couple of prerequisite patches to enable CPU frequency scaling on Tegra210. * tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 clk: tegra: dfll: add CVB tables for Tegra210 clk: tegra: dfll: round down voltages based on alignment clk: tegra: dfll: support PWM regulator control clk: tegra: dfll: CVB calculation alignment with the regulator clk: tegra: dfll: registration for multiple SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15clk: ti: check clock type before doing autoidle opsAndreas Kemnade
Code might use autoidle api with clocks not being omap2 clocks, so check if clock type is really omap2. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-02-15clk: ti: add a usecount for autoidleAndreas Kemnade
Multiple users might deny autoidle on a clock. So we should have some counting here, also according to the comment in _setup_iclk_autoidle(). Also setting autoidle regs is not atomic, so there is another reason for locking. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-02-15clk: ti: generalize the init sequence of clk_hw_omap clocksTero Kristo
Add a generic API for initializing clocks of clk_hw_omap type clocks, and convert the whole TI clock driver suite to use this for registering the clocks. Also, get rid of the now redundant API for adding the clocks to the OMAP HW clocks list; instead this is used directly from the register API. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15clk: ti: remove usage of CLK_IS_BASICTero Kristo
Remove the usage of CLK_IS_BASIC flag completely from TI clock driver. In most cases, the use is completely redundant, but in some cases we need to use the new API to check if the clock is an OMAP clock or not. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15clk: ti: add new API for checking if a provided clock is an OMAP clockTero Kristo
omap2_clk_is_hw_omap can now be used to verify if the provided clk_hw is an omap HW clock or not. This is done to replace the usage of CLK_IS_BASIC flag within the TI clock drivers. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15clk: ti: move clk_hw_omap list handling under generic part of the driverTero Kristo
Currently the clk_hw_omap list is handled under the autoidle code, but it should be accessible generically. Add a few APIs towards this, and update the autoidle code to use the generic implementations. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-13Merge tag 'sunxi-clk-fixes-for-5.0' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull Allwinner clock fixes from Maxime Ripard: Two fixes for clock indices, one for the A31 and one for the V3s. * tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi: A31: Fix wrong AHB gate number clk: sunxi-ng: v3s: Fix TCON reset de-assert bit
2019-02-13clk: meson: meson8b: fix the naming of the APB clocksMartin Blumenstingl
Fix a typo in the APB clock names by renaming them from "abp" to "apb". No functional changes. Fixes: a7d19b05ce817d ("clk: meson: meson8b: add the CPU clock post divider clocks") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190210222603.6404-2-martin.blumenstingl@googlemail.com
2019-02-13clk: meson: Add G12A AO Clock + Reset ControllerNeil Armstrong
Add the Amlogic G12A AO Clock and Reset controller driver handling generation of Always-On clocks : - AO Clocks and Reset for Always-On modules - 32K Generation for USB and CEC - SAR ADC controller clock Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190212162859.20743-3-narmstrong@baylibre.com
2019-02-06clk: clk-st: avoid clkdev lookup leak at removeMatti Vaittinen
Use devm based clkdev lookup registration to avoid leaking lookup structures. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06clk: clk-max77686: Clean clkdev lookup leak and use devmMatti Vaittinen
clk-max77686 never clean clkdev lookup at remove. This can cause oops if clk-max77686 is removed and inserted again. Fix leak by using new devm clkdev lookup registration. Simplify also error path by using new devm_of_clk_add_hw_provider. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06clkdev: add managed clkdev lookup registrationMatti Vaittinen
Clkdev registration lacks of managed registration functions and it seems few drivers do not drop clkdev lookups at exit. Add devm_clk_hw_register_clkdev and devm_clk_release_clkdev to ease lookup releasing at exit. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06clk: Add (devm_)clk_get_optional() functionsPhil Edworthy
This adds clk_get_optional() and devm_clk_get_optional() functions to get optional clocks. They behave the same as (devm_)clk_get() except where there is no clock producer. In this case, instead of returning -ENOENT, the function returns NULL. This makes error checking simpler and allows clk_prepare_enable, etc to be called on the returned reference without additional checks. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Russell King <linux@armlinux.org.uk> [sboyd@kernel.org: Document in devres.txt] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06clk: Add comment about __of_clk_get_by_name() error valuesPhil Edworthy
It's not immediately obvious from the code that failure to get a clock provider can return either -ENOENT or -EINVAL. Therefore, add a comment to highlight this. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Russell King <linux@armlinux.org.uk> [sboyd@kernel.org: Fix comment to be proper C with ==] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Peter De Schrijver
Tegra210 has a DFLL as well and can share the majority of the code with the Tegra124 implementation. So build the same code for both platforms. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06clk: tegra: dfll: add CVB tables for Tegra210Joseph Lo
Add CVB tables with different chip characterization, so that we can generate the customize OPP table that suitable for different chips with different SKUs. The parameter 'tune_high_min_millivolts' is first time introduced in this patch, which didn't use in the DFLL driver for clock and voltage tuning before. It will be used later when DFLL in high voltage range. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06clk: tegra: dfll: round down voltages based on alignmentJoseph Lo
When generating the OPP table, the voltages are round down with the alignment from the regulator. The alignment should be applied for voltages look up as well. Based on the work of Penny Chiu <pchiu@nvidia.com>. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06clk: tegra: dfll: support PWM regulator controlJoseph Lo
The DFLL hardware supports two modes (I2C and PWM) for voltage control when requesting a frequency. In this patch, we introduce PWM mode support. To support that, we re-organize the LUT for unifying the table for both cases of I2C and PWM mode. And generate that based on regulator info. For the PWM-based regulator, we get this info from DT. And do the same as the case of I2C LUT, which can help to map the PMIC voltage ID and voltages that the regulator supported. The other parts are the support code for initializing the DFLL hardware to support PWM mode. Also, the register debugfs file is slightly reworked to only show the i2c registers when I2C mode is in use. Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo
The CVB table contains calibration data for the CPU DFLL based on process characterization. The regulator step and offset parameters depend on the regulator supplying vdd-cpu, not on the specific Tegra SKU. When using a PWM controlled regulator, the voltage step and offset are determined by the regulator type in use. This is specified in DT. When using an I2C controlled regulator, we can retrieve them from CPU regulator Then pass this information to the CVB table calculation function. Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>" and "Alex Frid <afrid@nvidia.com>". Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06clk: tegra: dfll: registration for multiple SoCsPeter De Schrijver
In a future patch, support for the DFLL in Tegra210 will be introduced. This requires support for more than 1 set of CVB and CPU max frequency tables. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-05clk: ingenic: jz4740: Fix gating of UDC clockPaul Cercueil
The UDC clock is gated when the bit is cleared, not when it is set. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Artur Rojek <contact@artur-rojek.eu> Fixes: 2b555a4b9cae ("clk: ingenic: Add missing flag for UDC clock") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-05clk: mediatek: update clock driver of MT2712Weiyi Lu
According to 3rd ECO design change, 1. Add new fixed factor clock of audio. 2. Add the parent clocks for audio clock mux. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-05clk: renesas: r8a774c0: Add TMU clockBiju Das
This patch adds the TMU clocks to the R8A774C0 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-05clk: renesas: r8a77980: Add RPC clocksSergei Shtylyov
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the R-Car V3H (R8A77980) CPG/MSSR driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-05clk: renesas: rcar-gen3: Add RPC clocksSergei Shtylyov
The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field is different between SoCs; it makes sense to support the most common case of this encoding in the R-Car gen3 CPG driver... After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except V3M (R8A77970); the composite clock driver seems handy for this task, using the spinlock added in the previous patch... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-04clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet
The function used to probe the peripheral clock controller of the arm64 amlogic SoCs is mostly the same. We now have 3 of those controllers so it is time to factorize things a bit. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com
2019-02-04clk: meson: g12a: add peripheral clock controllerJian Hu
Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com
2019-02-04clk: meson: pll: update driver for the g12aJerome Brunet
The g12a use fractional parameter of 17 useful bits. At the moment, this parameter in encoded using u16 value. Use this opportunity to switch all the pll to parameter to unsigned int. This should save us some annoying trouble shooting when and m and n field eventually grow as well. This patch also introduce pll multiplier range. On the g12a, the hifi and gp0 plls are able to lock as long as the following condition is met: 55 <= m/n <= 255. The param table describing this would be huge which is a waste of memory. Using ranges, we can save memory. Ranges also help find the best pll parameter significantly faster since we don't have to try all the possible settings. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [jbrunet: fixed fix pll settings calculation with arm32] Link: https://lkml.kernel.org/r/20190201145345.6795-2-jbrunet@baylibre.com
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet
Initially, the meson clock directory only hosted 2 controllers drivers, for meson8 and gxbb. At the time, both used the same set of clock drivers so managing the dependencies was not a big concern. Since this ancient time, entropy did its job, controllers with different requirement and specific clock drivers have been added. Unfortunately, we did not do a great job at managing the dependencies between the controllers and the different clock drivers. Some drivers, such as clk-phase or vid-pll-div, are compiled even if they are useless on the target (meson8). As we are adding new controllers, we need to be able to pick a driver w/o pulling the whole thing. The patch aims to clean things up by: * providing a dedicated CONFIG_ for each clock drivers * allowing clock drivers to be compiled as a modules, if possible * stating explicitly which drivers are required by each controller. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com
2019-02-02clk: meson: axg-audio does not require sysconJerome Brunet
The axg audio clock controller uses regmap mmio, not syscon. Fixes: 1cd50181750f ("clk: meson: axg: add the audio clock controller driver") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-4-jbrunet@baylibre.com
2019-02-02clk: meson: use CONFIG_ARCH_MESON to enter meson clk directoryJerome Brunet
Use CONFIG_ARCH_MESON to let make enter the meson clock directory. As part of a rework, CONFIG_COMMON_CLK_AMLOGIC is about to be removed. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-3-jbrunet@baylibre.com
2019-02-02clk: export some clk_hw function symbols for module driversJerome Brunet
clk-provider.h provides clk_hw_is_prepared(), clk_hw_is_enabled() and clk_hw_is_prepared() but these symbols are not exported for the modules which prevents a clock driver using them to be compiled as a module. Export them to fix the problem. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-2-jbrunet@baylibre.com
2019-02-01clk: Document and simplify clk_core_get_rate_nolock()Stephen Boyd
This function uses a few gotos and doesn't explain why parents and numbers of parents are being checked before returning different values for the clk's rate. Document and simplify this function somewhat to make this better. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-01clk: samsung: exynos5433: Add selected IMEM clocksKamil Konieczny
This patch adds clocks required for the Exynos5433 SoC Slim Security SubSystem (SlimSSS) IP block. Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com> [s.nawrocki@samsung.com: edited commit description] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-02-01clk: samsung: exynos5433: Fix name typo in sssxKamil Konieczny
Fix typo in sssx name, there should be three letters 's'. Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-02-01clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocksKamil Konieczny
This fixes typos in CLK_ACLK_IMEM_200 and CLK_ACLK_IMEM_266 clock definition, leading to incorrect parent clock assignment. Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com> [s.nawrocki@samsung.com: edited commit description] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
generated by cgit (git 2.34.1) at 2025-09-14 20:10:22 +0000