summaryrefslogtreecommitdiff
path: root/drivers/clk
AgeCommit message (Collapse)Author
2017-12-29clk: sunxi-ng: add support for Allwinner H3 DE2 CCUIcenowy Zheng
Allwinner H3 features a DE2 CCU like the one on A83T, however the parent of the clocks is the DE module clock, not the PLL_DE clock. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-12-28clk: divider: fix incorrect usage of container_ofJerome Brunet
divider_recalc_rate() is an helper function used by clock divider of different types, so the structure containing the 'hw' pointer is not always a 'struct clk_divider' At the following line: > div = _get_div(table, val, flags, divider->width); in several cases, the value of 'divider->width' is garbage as the actual structure behind this memory is not a 'struct clk_divider' Fortunately, this width value is used by _get_val() only when CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so far when the structure is not a 'struct clk_divider'. This is probably why we did not notice this bug before Fixes: afe76c8fd030 ("clk: allow a clk divider with max divisor when zero") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO()Gomonovych, Vasyl
Fix ptr_ret.cocci warnings: drivers/clk/mvebu/armada-37xx-periph.c:362:1-3: WARNING: PTR_ERR_OR_ZERO can be used Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Generated by: scripts/coccinelle/api/ptr_ret.cocci Signed-off-by: Vasyl Gomonovych <gomonovych@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28clk: iproc: Minor tidy up of iproc pll data structuresLori Hikichi
There were a few fields in the iproc pll data structures that were holding information that was not true state information. Using stack variables is sufficient and simplifies the structure. There are not any functional changes in this commit. Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28clk: iproc: Allow plls to do minor rate changes without resetLori Hikichi
The iproc plls are capable of doing small rate changes without the need for a full reset and re-lock procedure. This feature will allow for small tweaks to the PLL rate to occur smoothly. Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28clk: iproc: Fix error in the pll post divider rate calculationLori Hikichi
The pll post divider code was using DIV_ROUND_UP when determining the divider value best suited to produce the target frequency. Using DIV_ROUND_CLOSEST will give us better divider values when the division results in a small remainder. Also, change the post divider clock over to the determine_rate api instead of round_rate. Signed-off-by: Simran Rai <ssimran@broadcom.com> Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28clk: iproc: Allow iproc pll to runtime calculate vco parametersLori Hikichi
Add the ability for the iproc pll to calculate the pll parameters at runtime instead of only using predefined tables. This ability allows the clock users to select from the full range of vco frequencies. The old method of table based programming is retained so that existing users will retain expected behavior. The flag IPROC_CLK_PLL_CALC_PARAM will need to be set to enable the new runtime calculation method. Currently, this is only being enabled for the audio pll. This feature also revealed a problem with the driver using the round_rate api. The round_rate api does not allow for frequencies larger than 2^31 to be returned. Those large frequencies are interpreted as an error code. Therefore, we are moving to the determine_rate api which solves this problem. Signed-off-by: Simran Rai <ssimran@broadcom.com> Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28clk: si5351: _si5351_clkout_reset_pll() can be staticWu Fengguang
Fixes: b26ff127c52c ("clk: si5351: Apply PLL soft reset before enabling the outputs") Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28clk: pxa: unbreak lookup of CLK_POUTIgor Grinberg
Since switching to clk drivers, the CLK_POUT cannot be searched for by clk_get() API and thus it returns with ENOENT. Register it with the clk_lookup and thus unbreak the users of it. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28clk: meson-axg: make local symbol axg_gp0_params_table staticweiyongjun (A)
Fixes the following sparse warning: drivers/clk/meson/axg.c:260:25: warning: symbol 'axg_gp0_params_table' was not declared. Should it be static? Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28clk: meson-axg: fix return value check in axg_clkc_probe()weiyongjun (A)
In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-26clk: use atomic runtime pm api in clk_core_is_enabledDong Aisheng
Current clk_pm_runtime_put is using pm_runtime_put_sync which is not safe to be called in clk_core_is_enabled as it should be able to run in atomic context. Thus use pm_runtime_put instead which is atomic safe. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Fixes: 9a34b45397e5 ("clk: Add support for runtime PM") Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-26clk: mediatek: Fix all warnings for missing struct clk_onecell_dataSean Wang
Even though the header file linux/clk-provider.h is already being properly included in clk-mtk.h, the definition of struct clk_onecell_data still must depend on CONFIG_COMMON_CLK defined and thus it's possible that below build warnings occur when CONFIG_COMMON_CLK is not being selected. Therefore, these functions which need struct clk_onecell_data without declaring that structure first requires simply declaring that this struct exists prior to referencing it in clk-mtk.h Changes from v1->v2: enhance v1 based on two useful solutions Jean Delvare kindly suggested. All warnings (new ones prefixed by >>): In file included from drivers/clk/mediatek/reset.c:22:0: >>drivers/clk/mediatek/clk-mtk.h:44:19: warning: 'struct clk_onecell_data' declared inside parameter list will not be visible outside of this definition or declaration int num, struct clk_onecell_data *clk_data); ^~~~~~~~~~~~~~~~ drivers/clk/mediatek/clk-mtk.h:63:19: warning: 'struct clk_onecell_data' declared inside parameter list will not be visible outside of this definition or declaration int num, struct clk_onecell_data *clk_data); ^~~~~~~~~~~~~~~~ drivers/clk/mediatek/clk-mtk.h:145:10: warning: 'struct clk_onecell_data' declared inside parameter list will not be visible outside of this definition or declaration struct clk_onecell_data *clk_data); ^~~~~~~~~~~~~~~~ drivers/clk/mediatek/clk-mtk.h:164:11: warning: 'struct clk_onecell_data' declared inside parameter list will not be visible outside of this definition or declaration struct clk_onecell_data *clk_data); ^~~~~~~~~~~~~~~~ drivers/clk/mediatek/clk-mtk.h:190:12: warning: 'struct clk_onecell_data' declared inside parameter list will not be visible outside of this definition or declaration struct clk_onecell_data *clk_data); ^~~~~~~~~~~~~~~~ Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Cc: kbuild-all@01.org Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Jean Delvare <jdelvare@suse.de> Cc: linux-clk@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-23clk: meson: mpll: use 64-bit maths in params_from_rateMartin Blumenstingl
"rem * SDM_DEN" can easily overflow on the 32-bit Meson8 and Meson8b SoCs if the "remainder" (after the division operation) is greater than 262143Hz. This is likely to happen since the input clock for the MPLLs on Meson8 and Meson8b is "fixed_pll", which is running at a rate of 2550MHz. One example where this was observed to be problematic was the Ethernet clock calculation (which takes MPLL2 as input). When requesting a rate of 125MHz there is a remainder of 2500000Hz. The resulting MPLL2 rate before this patch was 127488329Hz. The resulting MPLL2 rate after this patch is 124999103Hz. Commit b609338b26f5 ("clk: meson: mpll: use 64bit math in rate_from_params") already fixed a similar issue in rate_from_params. Fixes: 007e6e5c5f01d3 ("clk: meson: mpll: add rw operation") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-12-21clk: si5351: Do not enable parent clocks on probeSergej Sawazki
The si5351 driver should not prepare or enable other clocks in the tree on probe. Let the clients decide when to prepare or enable the clocks. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Sergej Sawazki <ce3a@gmx.de> [sboyd@codeaurora.org: Remove most of the .remove function too] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: si5351: Rename internal plls to avoid name collisionsSergej Sawazki
This drivers probe fails due to a clock name collision if a clock named 'plla' or 'pllb' is already registered when registering this drivers internal plls. Fix it by renaming internal plls to avoid name collisions. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Sergej Sawazki <sergej@taudac.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: si5351: Apply PLL soft reset before enabling the outputsSergej Sawazki
The "Si5351A/B/C Data Sheet" states to apply a PLL soft reset before enabling the output clocks [1]. This is required to get a deterministic phase relationship between the output clocks. Without resetting the PLL, the phase relationship between the clocks is unpredictable. Fix this by resetting the PLL in si5351_clkout_prepare(). References: [1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf Figure 12 ("I2C Programming Procedure") Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Sergej Sawazki <sergej@taudac.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: si5351: Add DT property to enable PLL resetSergej Sawazki
Add optional output clock DT property to enable PLL reset when a clock output is enabled. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Sergej Sawazki <sergej@taudac.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: si5351: implement remove handlerAlexey Khoroshilov
The driver has no remove function, so it does not cleanup resources that are not under devm management. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: axi-clkgen: Round closest in round_rate() and recalc_rate()Lars-Peter Clausen
To minimize the rounding error round to the closest integer when calculating the result in the recalc_rate() and set_rate() callbacks. Also in order to improve precision multiply first and then divide. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()Lars-Peter Clausen
If the nocount bit is set the divider is bypassed and the settings for the divider count should be ignored and a divider value of 1 should be assumed. Handle this correctly in the driver recalc_rate() callback. While the driver sets up the part so that the read back dividers values yield the correct result the power-on reset settings of the part might not reflect this and hence calling e.g. clk_get_rate() without prior calls to clk_set_rate() will yield the wrong result. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: Don't touch hardware when reparenting during registrationStephen Boyd
The orphan clocks reparent operation shouldn't touch the hardware if clocks are enabled, otherwise it may get a chance to disable a newly registered critical clock which triggers the warning below. Assuming we have two clocks: A and B, B is the parent of A. Clock A has flag: CLK_OPS_PARENT_ENABLE Clock B has flag: CLK_IS_CRITICAL Step 1: Clock A is registered, then it becomes orphan. Step 2: Clock B is registered. Before clock B reach the critical clock enable operation, orphan A will find the newly registered parent B and do reparent operation, then parent B will be finally disabled in __clk_set_parent_after() due to CLK_OPS_PARENT_ENABLE flag as there's still no users of B which will then trigger the following warning. WARNING: CPU: 0 PID: 0 at drivers/clk/clk.c:597 clk_core_disable+0xb4/0xe0 Modules linked in: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.11.0-rc1-00056-gdff1f66-dirty #1373 Hardware name: Generic DT based system Backtrace: [<c010c4bc>] (dump_backtrace) from [<c010c764>] (show_stack+0x18/0x1c) r6:600000d3 r5:00000000 r4:c0e26358 r3:00000000 [<c010c74c>] (show_stack) from [<c040599c>] (dump_stack+0xb4/0xe8) [<c04058e8>] (dump_stack) from [<c0125c94>] (__warn+0xd8/0x104) r10:c0c21cd0 r9:c048aa78 r8:00000255 r7:00000009 r6:c0c1cd90 r5:00000000 r4:00000000 r3:c0e01d34 [<c0125bbc>] (__warn) from [<c0125d74>] (warn_slowpath_null+0x28/0x30) r9:00000000 r8:ef00bf80 r7:c165ac4c r6:ef00bf80 r5:ef00bf80 r4:ef00bf80 [<c0125d4c>] (warn_slowpath_null) from [<c048aa78>] (clk_core_disable+0xb4/0xe0) [<c048a9c4>] (clk_core_disable) from [<c048be88>] (clk_core_disable_lock+0x20/0x2c) r4:000000d3 r3:c0e0af00 [<c048be68>] (clk_core_disable_lock) from [<c048c224>] (clk_core_disable_unprepare+0x14/0x28) r5:00000000 r4:ef00bf80 [<c048c210>] (clk_core_disable_unprepare) from [<c048c270>] (__clk_set_parent_after+0x38/0x54) r4:ef00bd80 r3:000010a0 [<c048c238>] (__clk_set_parent_after) from [<c048daa8>] (clk_register+0x4d0/0x648) r6:ef00d500 r5:ef00bf80 r4:ef00bd80 r3:ef00bfd4 [<c048d5d8>] (clk_register) from [<c048dc30>] (clk_hw_register+0x10/0x1c) r9:00000000 r8:00000003 r7:00000000 r6:00000824 r5:00000001 r4:ef00d500 [<c048dc20>] (clk_hw_register) from [<c048e698>] (_register_divider+0xcc/0x120) [<c048e5cc>] (_register_divider) from [<c048e730>] (clk_register_divider+0x44/0x54) r10:00000004 r9:00000003 r8:00000001 r7:00000000 r6:00000003 r5:00000001 r4:f0810030 [<c048e6ec>] (clk_register_divider) from [<c0d3ff58>] (imx7ulp_clocks_init+0x558/0xe98) r7:c0e296f8 r6:c165c808 r5:00000000 r4:c165c808 [<c0d3fa00>] (imx7ulp_clocks_init) from [<c0d24db0>] (of_clk_init+0x118/0x1e0) r10:00000001 r9:c0e01f68 r8:00000000 r7:c0e01f60 r6:ef7f8974 r5:ef0035c0 r4:00000006 [<c0d24c98>] (of_clk_init) from [<c0d04a50>] (time_init+0x2c/0x38) r10:efffed40 r9:c0d61a48 r8:c0e78000 r7:c0e07900 r6:ffffffff r5:c0e78000 r4:00000000 [<c0d04a24>] (time_init) from [<c0d00b8c>] (start_kernel+0x218/0x394) [<c0d00974>] (start_kernel) from [<6000807c>] (0x6000807c) r10:00000000 r9:410fc075 r8:6000406a r7:c0e0c930 r6:c0d61a44 r5:c0e07918 r4:c0e78294 We know that the clk isn't enabled with any sort of prepare_count here so we don't need to enable anything to prevent a race. And we're holding the prepare mutex so set_rate/set_parent can't race here either. Based on an earlier patch by Dong Aisheng. Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)") Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Reported-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: mediatek: fixup test-building of MediaTek clock driversSean Wang
Let the build system looking into the directiory where the clock drivers resides for the COMPILE_TEST alternative dependency allows test-building the drivers. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: mediatek: group drivers under indpendent menuSean Wang
Getting much MediaTek clock driver have been added to CCF, so it's better adding the cleanup for grouping drivers under the independent menu to simplify configuration selection. In addition, really trivial fixups for typos are added in the same patch. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: at91: pmc: Support backup for programmable clocksRomain Izard
When an AT91 programmable clock is declared in the device tree, register it into the Power Management Controller driver. On entering suspend mode, the driver saves and restores the Programmable Clock registers to support the backup mode for these clocks. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: at91: pmc: Save SCSR during suspendRomain Izard
The contents of the System Clock Status Register (SCSR) needs to be restored into the System Clock Enable Register (SCER). As the bootloader will restore some clocks by itself, the issue can be missed as only the USB controller, the LCD controller, the Image Sensor controller and the programmable clocks will be impacted. Fix the obvious typo in the suspend/resume code, as the IMR register does not need to be saved twice. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: at91: pmc: Wait for clocks when resumingRomain Izard
Wait for the syncronization of all clocks when resuming, not only the UPLL clock. Do not use regmap_read_poll_timeout, as it will call BUG() when interrupts are masked, which is the case in here. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: qcom: ipq8074: add misc resets for PCIE and NSSAbhishek Sahu
PCIE and NSS has MISC reset register in which single register has multiple reset bit. The patch adds these resets with its corresponding reset bits. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: qcom: ipq8074: add GP and Crypto clocksAbhishek Sahu
- It has 3 general purpose clock controller which supplies the clock in GPIO pins. - It has Crypto Engine which has AXI, AHB and Core clocks. Other non APSS processors can also use Crypto Engine so these clocks are marked as VOTED clocks. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: qcom: ipq8074: add NSS ethernet port clocksAbhishek Sahu
IPQ8074 has 6 ethernet ports which supports all ethernet speeds from 10Mpbs to 10 Gpbs and each speed requires different clock rates. Each port has separate TX and RX clocks. These clocks use separate external UNIPHY PLL’s which will be registered with separate NSS driver. The clock frequency is 125 Mhz for UNIPHY0 and 312.5 Mhz for UNIPHY1 and UNIPHY2. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: qcom: ipq8074: add NSS clocksAbhishek Sahu
IPQ8074 has NSS (Network Switching System) which has 2 UBI cores and hardware crypto engine. Some clocks are separate for each UBI core and remaining NSS clocks are common. The BIAS_PLL (300 Mhz) and BIAS_PLL_NSS_NOC (416.5 Mhz) are external fixed clocks and will be registered from dtsi or NSS driver. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: qcom: ipq8074: add PCIE, USB and SDCC clocksAbhishek Sahu
- It has 2 instances of PCIE which uses AXI, AHB, AUX, SYS NOC AXI and PIPE clocks. - It has 2 instances of USB 3.0 which uses AUX, SLEEP, PIPE, SYS NOC, mock UTMI and master clocks. - It has 2 instances of SDCC which uses APSS and AHB clock. SDCC1 requires ICE core clock also. - All the PIPE clocks are external clocks which will be registered in clock framework by PHY drivers. The enabling and disabling of PIPE RCG clocks are dependent upon PHY initialization sequence so BRANCH_HALT_DELAY flag is required for these clocks. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: qcom: ipq8074: add remaining PLL’sAbhishek Sahu
- GPLL2, GPLL4 and GPLL6 are general PLL clocks and parent for all core peripherals. - UBI PLL is mainly used by NSS (Network Switching System). IPQ8074 has 2 instances of NSS UBI cores and UBI PLL will be used to control the core frequency. - NSS Crypto PLL is mainly used by NSS Crypto Engine which supports the multiple cryptographic algorithm used in Ethernet. - IPQ8074 frequency plan does not require change in PLL post dividers so marked the same as read-only. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: qcom: ipq8074: fix missing GPLL0 divider widthAbhishek Sahu
GPLL0 uses 4 bits post divider which should be specified in clock driver structure. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: qcom: add parent map for regmap muxAbhishek Sahu
Currently the driver assumes the register configuration value is identical to its index in the parent map. This patch adds the parent map field in regmap mux clock node which contains the mapping of parent index with actual register configuration value. If regmap node contains this parent map then the configuration value will be taken from this parent map instead of simply writing the index value. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: qcom: add read-only divider operationsAbhishek Sahu
Some of the divider settings are preconfigured and should not be changed by the clock framework during frequency change. This patch adds the read-only divider operation for QCOM dividers which is equivalent to generic divider operations in 'commit 79c6ab509558 ("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: imx51: uart4, uart5 gates only exist on imx50, imx53Philipp Zabel
i.MX51 only has 3 UARTs and no CCGR7 register. In place of the CCGR7 register on i.MX50/i.MX53 that contains the ipg and per clock gates for UARTs 4 and 5, on i.MX51 there is the CMEOR register. Without this patch, the code disabling the UART clocks would also clear the mod_en_ov_vpu bit in the CMEOR register, among others, which causes register accesses to the VPU to lock up the system. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: qoriq: add more divider clocks supportYuantian Tang
More divider clocks are needed by IP. So enlarge the PLL divider array to accommodate more divider clocks. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocksGregory CLEMENT
When DVFS is enabled the CPU clock setting is done using an other set of registers. These Power Management registers are exposed through a syscon as they will also be used by other drivers such as the cpufreq. This patch add the possibility to modify the CPU frequency using the associate load level matching the target frequency. Then all the frequency switch is handle by the hardware. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> [sboyd@codeaurora.org: Grow a local variable for regmap pointer to keep lines shorter] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFSGregory CLEMENT
When DVFS will be enabled then the cpu clk will use a different set of register at run time. That means that we won't be able to use the common callback and need to use our own ones. This patch prepares this change by switching on our own set of callbacks without modifying the behavior of the clocks. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: mvebu: armada-37xx-periph: cosmetic changesGregory CLEMENT
This patches fixes few cosmetic issues such as alignment, blank lines and required space. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: sprd: add clocks support for SC9860Chunyan Zhang
This patch added the list of clocks for Spreadtrum's SC9860 SoC, together with clock initialization code. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: sprd: add adjustable pll supportChunyan Zhang
Introduced a common adjustable pll clock driver for Spreadtrum SoCs. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: sprd: add composite clock supportChunyan Zhang
This patch introduced composite driver for Spreadtrum's SoCs. The functions of this composite clock simply consist of divider and mux clocks. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: sprd: add divider clock supportChunyan Zhang
This is a feature that can also be found in sprd composite clocks, provide a bunch of helpers that can be reused later on. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: sprd: add mux clock supportChunyan Zhang
This patch adds clock multiplexor support for Spreadtrum platforms, the mux clocks also can be found in sprd composite clocks, so provides two helpers that can be reused later on. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: sprd: add gate clock supportChunyan Zhang
Some clocks on the Spreadtrum's SoCs are just simple gates. Add support for those clocks. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: sprd: Add common infrastructureChunyan Zhang
Added Spreadtrum's clock driver framework together with common structures and interface functions. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21clk: move clock common macros out from vendor directoriesChunyan Zhang
These macros are used by more than one SoC vendor platforms, avoid to have many copies of these code, this patch moves them to the common header file which every clock drivers can access to. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-19clk: fix set_rate_range when current rate is out of rangeJerome Brunet
Calling clk_core_set_rate() with core->req_rate is basically a no-op because of the early bail-out mechanism. This may leave the clock in inconsistent state if the rate is out the requested range. Calling clk_core_set_rate() with the closest rate limit could solve the problem but: - The underlying determine_rate() callback needs to account for this corner case (rounding within the range, if possible) - if only round_rate() is available, we rely on luck unfortunately. Fixes: 1c8e600440c7 ("clk: Add rate constraints to clocks") Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20171201215200.23523-11-jbrunet@baylibre.com
generated by cgit (git 2.34.1) at 2025-10-02 08:52:54 +0000