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path: root/drivers/clk
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2023-10-12clk: stm32: Fix a signedness issue in clk_stm32_composite_determine_rate()Dan Carpenter
The divider_ro_round_rate() function could potentially return -EINVAL on error but the error handling doesn't work because "rate" is unsigned. It should be a type long. Fixes: 06ed0fc0fbac ("clk: stm32: composite: Switch to determine_rate") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/d9a78453-9b40-48c1-830e-00751ba3ecb8@kili.mountain Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-12clk: Sanitize possible_parent_show to Handle Return Value of ↵Alessandro Carminati
of_clk_get_parent_name In the possible_parent_show function, ensure proper handling of the return value from of_clk_get_parent_name to prevent potential issues arising from a NULL return. The current implementation invokes seq_puts directly on the result of of_clk_get_parent_name without verifying the return value, which can lead to kernel panic if the function returns NULL. This patch addresses the concern by introducing a check on the return value of of_clk_get_parent_name. If the return value is not NULL, the function proceeds to call seq_puts, providing the returned value as argument. However, if of_clk_get_parent_name returns NULL, the function provides a static string as argument, avoiding the panic. Fixes: 1ccc0ddf046a ("clk: Use seq_puts() in possible_parent_show()") Reported-by: Philip Daly <pdaly@redhat.com> Signed-off-by: Alessandro Carminati (Red Hat) <alessandro.carminati@gmail.com> Link: https://lore.kernel.org/r/20230921073217.572151-1-alessandro.carminati@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-12clk: socfpga: gate: Account for the divider in determine_rateMaxime Ripard
Commit 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") added a determine_rate implementation set to the clk_hw_determine_rate_no_reparent, but failed to account for the internal divider that wasn't used before anywhere but in recalc_rate. This led to inconsistencies between the clock rate stored in clk_core->rate and the one returned by clk_round_rate() that leverages determine_rate(). Since that driver seems to be widely used (and thus regression-prone) and not supporting rate changes (since it's missing a .set_rate implementation), we can just report the current divider programmed in the clock but not try to change it in any way. This should be good enough to fix the issues reported, and if someone ever wants to allow the divider to change then it should be easy enough using the clk-divider helpers. Link: https://lore.kernel.org/linux-clk/20231005095927.12398-2-b.spranger@linutronix.de/ Fixes: 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") Reported-by: Benedikt Spranger <b.spranger@linutronix.de> Signed-off-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20231012083729.2148044-1-mripard@kernel.org [sboyd@kernel.org: Fix hw -> hwclk] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-12clk: fractional-divider: tests: Add test suite for edge casesFrank Oltmanns
In light of the recent discovery that the fractional divisor approximation does not utilize the full available range for clocks that are flagged CLK_FRAC_DIVIDER_ZERO_BASED [1], implement tests for the edge cases of this clock type. Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/lkml/20230529133433.56215-1-frank@oltmanns.dev [1] Link: https://lore.kernel.org/r/20230617131041.18313-3-frank@oltmanns.dev [sboyd@kernel.org: Rename suite and tests slightly, drop unused includes, store parent rate to compare instead of repeating equation] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-12clk: fractional-divider: Improve approximation when zero based and exportFrank Oltmanns
Consider the CLK_FRAC_DIVIDER_ZERO_BASED flag when finding the best approximation for m and n. By doing so, increase the range of valid values for the numerator and denominator by 1. Furthermore, export the approximation function so that users of this function can be compiled as modules. Cc: A.s. Dong <aisheng.dong@nxp.com> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20230617131041.18313-2-frank@oltmanns.dev Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-12clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2Claudiu Beznea
Add clock and reset support for the SDHI1 and SDHI2 blocks on the RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231010132701.1658737-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-12clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()Claudiu Beznea
Use the %x format specifier to print CLK_ON_R(). This makes debugging easier as the value printed will be hexadecimal like in the hardware manual. Along with it add "0x" in front of the printed value. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231010132701.1658737-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-10clk: renesas: Add minimal boot support for RZ/G3S SoCClaudiu Beznea
Add minimal clock and reset support for the RZ/G3S SoC to be able to boot Linux from SD Card/eMMC. This includes necessary core clocks for booting and GIC, SCIF, GPIO, and SD0 module clocks and resets. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231006103959.197485-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-10clk: renesas: rzg2l: Add divider clock for RZ/G3SClaudiu Beznea
Add a divider clock driver for RZ/G3S. This will be used on RZ/G3S for the SDHI, SPI, OCTA, I, I2, I3, P0, P1, P2, and P3 core clocks. The divider has some limitation for SDHI, OCTA and SPI clocks: - SDHI div cannot be 1 if parent rate is 800MHz, - OCTA, SPI div cannot be 1 if parent rate is 400MHz. To handle these limitations, a notifier is registered from platform specific clock driver, which makes sure proper actions are taken before the clock rate is changed, when needed. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231006103959.197485-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-10clk: renesas: rzg2l: Refactor SD mux driverClaudiu Beznea
Refactor SD MUX driver to be able to reuse the same code on RZ/G3S. RZ/G2{L,UL} has a limitation with regards to switching the clock source for SD MUX (MUX clock source has to be switched to 266MHz before switching b/w 533MHz and 400MHz). Rework the handling of this limitation to use a clock notifier that is registered according to platform based initialization data, so the SD MUX code can be reused on RZ/G3S. As RZ/G2{L,UL} and RZ/G3S use different bits in different registers to check if the clock switching has been done, this configuration (register offset, register bits and bitfield width) is now passed through struct cpg_core_clk::sconf (status configuration) from platform specific initialization code. Along with struct cpg_core_clk::sconf the mux table indices are also passed from platform specific initialization code. Also, mux flags are now passed to DEF_SD_MUX() as they will be used later by RZ/G3S. CPG_WEN_BIT macro has been introduced to select properly the WEN bit of various registers. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231006103959.197485-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-09clk: versaclock7: Convert to use maple tree register cacheMark Brown
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-versaclk-v1-4-24dd5b3d8689@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: versaclock5: Convert to use maple tree register cacheMark Brown
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-versaclk-v1-3-24dd5b3d8689@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: versaclock3: Convert to use maple tree register cacheMark Brown
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-versaclk-v1-2-24dd5b3d8689@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: versaclock3: Remove redundant _is_writeable()Mark Brown
The versaclock3 driver provides an _is_writeable() function which returns true for all registers. This is the default assumption for regmaps so we can remove the function for a very minor improvement in performance and code size. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-versaclk-v1-1-24dd5b3d8689@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: si570: Convert to use maple tree register cacheMark Brown
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-si-v1-5-e26cfcaf27bd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: si544: Convert to use maple tree register cacheMark Brown
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-si-v1-4-e26cfcaf27bd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: si5351: Convert to use maple tree register cacheMark Brown
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-si-v1-3-e26cfcaf27bd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: si5341: Convert to use maple tree register cacheMark Brown
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-si-v1-2-e26cfcaf27bd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: si514: Convert to use maple tree register cacheMark Brown
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-si-v1-1-e26cfcaf27bd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: cdce925: Convert to use maple tree register cacheMark Brown
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-rbtree-cdce925-v1-1-a36b459002f7@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: Parameterize clk_leaf_mux_set_rate_parentStephen Boyd
Transform the existing clk_leaf_mux_set_rate_parent test into a parameterized test that calls the various determine rate APIs that exist for clk providers. This ensures that whatever determine rate API is used by a clk provider will return the correct parent in the best_parent_hw pointer of the clk_rate_request because clk_rate_requests are forwarded properly. Cc: Guenter Roeck <linux@roeck-us.net> Cc: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230912175534.2427862-3-sboyd@kernel.org Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-09clk: Drive clk_leaf_mux_set_rate_parent test from clk_opsStephen Boyd
Running this kunit test with lockdep enabled leads to warning splats about calling clk provider APIs without the clk_prepare lock held. I proposed adding a wrapper around these APIs to grab the prepare lock so we can call them from anywhere, and Maxime implemented that approach[1], but it didn't look great. That's because we had to make more kunit testing APIs just to call code from a place that isn't a clk provider when the prepare lock isn't held. Instead of doing that, let's implement a determine_rate clk_op for a new leaf clk that is the child of the existing leaf clk. We can call __clk_determine_rate() on the existing leaf clk from there, and stash away the clk_rate_request struct to check once the clk_op returns. Drive that clk_op by calling clk_round_rate() to keep things similar to how it was before (i.e. nothing actually changes rate, just the new rate is determined). This silences the warning by driving the test from a clk_op where we know the prepare lock is held. While looking at this in more detail, it was determined that the code we intended to test in commit 262ca38f4b6e ("clk: Stop forwarding clk_rate_requests to the parent") wasn't actually tested. The call to __clk_determine_rate() wasn't actually getting to the newly introduced code under the CLK_SET_RATE_PARENT if condition in clk_core_round_rate_nolock() because the parent clk (the mux) could round rates. We introduce a new leaf and make sure the parent of that clk has no clk_ops so that we can be certain that the CLK_SET_RATE_PARENT condition in clk_core_round_rate_nolock() is evaluated. Reported-by: Guenter Roeck <linux@roeck-us.net> Closes: https://lore.kernel.org/linux-clk/2b594e50-2bbf-4a2d-88e6-49fc39f3957a@roeck-us.net/ Reported-by: kernel test robot <yujie.liu@intel.com> Closes: https://lore.kernel.org/oe-lkp/202301310919.b9d56ee3-yujie.liu@intel.com Cc: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230721-clk-fix-kunit-lockdep-v1-0-32cdba4c8fc1@kernel.org [1] Fixes: 262ca38f4b6e ("clk: Stop forwarding clk_rate_requests to the parent") Link: https://lore.kernel.org/r/20230912175534.2427862-2-sboyd@kernel.org Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-10-08clk: scmi: Add support for clock {set,get}_parentPeng Fan
SCMI v3.2 adds set/get parent clock commands, so update the SCMI clock driver to support them. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20231004-scmi-clock-v3-v5-2-1b8a1435673e@nxp.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2023-10-08clk: scmi: Free scmi_clk allocated when the clocks with invalid info are skippedSudeep Holla
Add the missing devm_kfree() when we skip the clocks with invalid or missing information from the firmware. Cc: Cristian Marussi <cristian.marussi@arm.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Fixes: 6d6a1d82eaef ("clk: add support for clocks provided by SCMI") Link: https://lore.kernel.org/r/20231004193600.66232-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2023-10-05clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic headerClaudiu Beznea
Remove CPG_SDHI_DSEL and its bits from the generic header as RZ/G3S has different offset registers and bits for this, thus avoid mixing them. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-10-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05clk: renesas: rzg2l: Add struct clk_hw_dataClaudiu Beznea
Add clk_hw_data struct that keeps the core part of the clock data. sd_hw_data embeds a member of type struct clk_hw_data along with other members (in the next commits). This commit prepares the field for refactoring the SD MUX clock driver. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-9-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05clk: renesas: rzg2l: Add support for RZ/G3S PLLClaudiu Beznea
Add support for reading the frequency of PLL1/4/6 as available on RZ/G3S. The computation formula for the PLL frequency is as follows: Fout = (nir + nfr / 4096) * Fin / (mr * pr) Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-8-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05clk: renesas: rzg2l: Remove critical areaClaudiu Beznea
The spinlock in rzg2l_mod_clock_endisable() is intended to protect RMW-accesses to the hardware register. There is no need to protect instructions that set temporary variables which will be written afterwards to a hardware register. With this only one write to one clock register is executed thus locking/unlocking rmw_lock is removed. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-7-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05clk: renesas: rzg2l: Fix computation formulaClaudiu Beznea
According to the hardware manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf), the computation formula for PLL rate is as follows: Fout = ((m + k/65536) * Fin) / (p * 2^s) and k has values in the range [-32768, 32767]. Dividing k by 65536 with integer arithmetic gives zero all the time, causing slight differences b/w what has been set vs. what is displayed. Thus, get rid of this and decompose the formula before dividing k by 65536. Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-6-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05clk: renesas: rzg2l: Trust value returned by hardwareClaudiu Beznea
The onitial value of the CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b. The hardware user's manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that setting 0 is prohibited. Hence rzg2l_cpg_sd_clk_mux_get_parent() should just read CPG_PL2SDHI_DSEL, trust the value, and return the proper clock parent index based on the value read. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-5-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05clk: renesas: rzg2l: Lock around writes to mux registerClaudiu Beznea
The SD MUX output (SD0) is further divided by 4 in G2{L,UL}. The divided clock is SD0_DIV4. SD0_DIV4 is registered with CLK_SET_RATE_PARENT which means a rate request for it is propagated to the MUX and could reach rzg2l_cpg_sd_clk_mux_set_parent() concurrently with the users of SD0. Add proper locking to avoid concurrent accesses on SD MUX set rate registers. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-4-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05clk: renesas: rzg2l: Wait for status bit of SD mux before continuingClaudiu Beznea
The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf, chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL for SD clock switching status. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929053915.1530607-3-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05clk: renesas: rcar-gen3: Extend SDnH divider tableDirk Behme
The clock dividers might be used with clock stop bit enabled or not. Current tables only support recommended values from the datasheet. This might result in warnings like below because no valid clock divider is found. Resulting in a 0 divider. There are Renesas ARM Trusted Firmware version out there which e.g. configure 0x201 (shifted logical right by 2: 0x80) and with this match the added { STPnHCK | 0, 1 }: https://github.com/renesas-rcar/arm-trusted-firmware/blob/rcar_gen3_v2.3/drivers/renesas/rcar/emmc/emmc_init.c#L108 ------------[ cut here ]------------ sd1h: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:141 divider_recalc_rate+0x48/0x70 Modules linked in: CPU: 1 PID: 1 Comm: swapper/0 Not tainted 6.1.52 #1 Hardware name: Custom board based on r8a7796 (DT) pstate: 40000005 (nZcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : divider_recalc_rate+0x48/0x70 ... ------------[ cut here ]------------ Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> [wsa: extended the table to 5 entries, added comments, reword commit message a little] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230928080317.28224-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-04clk: imx: imx8qm/qxp: add more resources to whitelistPeng Fan
Add CAN_1/2 support for i.MX8QM Add M4_0, PI_0_PWM_0 and PI_0_I2C_0 for i.MX8QXP Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230912-imx8-clk-v1-v1-7-69a34bcfcae1@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: scu: ignore clks not owned by Cortex-A partitionPeng Fan
Not register clks that not owned to current partition. CPU resources are specical resources, it is assigned in ATF, not non-secure OS, but we still need to allow cpu freq, so return true for non-secure OS for cpu resources. Otherwise there will be error log if the resources are owned by current partition: [ 19.387291] cm40_i2c_div: failed to attached the power domain -2 [ 19.389305] cm40_lpuart_div: failed to attached the power domain -2 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230912-imx8-clk-v1-v1-6-69a34bcfcae1@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx8: remove MLB supportPeng Fan
MLB was de-featured, so drop MLB clk for i.MX8QM/QXP/DXL Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230912-imx8-clk-v1-v1-5-69a34bcfcae1@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx8qm-rsrc: drop VPU_UART/VPUCOREPeng Fan
IMX_SC_R_VPU_UART and IMX_SC_R_VPUCORE was used in i.MX8QM A0 which not for mass production. i.MX8QM B0 not have the two resources, so drop it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230912-imx8-clk-v1-v1-4-69a34bcfcae1@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx8qxp: correct the enet clocks for i.MX8DXLShenwei Wang
The SC_PM_CLK_MISC0 clock is not available for the resources of ENET0/1 on i.MX8DXL. Using the clock device compatible string to identify the platform and only initialize the enetX_rgmii_rx_clk clock for non i.MX8DXL platform. Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Reviewed-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Acked-by: Jason Liu <jason.hui.liu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230912-imx8-clk-v1-v1-3-69a34bcfcae1@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx8qxp: Fix elcdif_pll clockRobert Chiras
Move the elcdif_pll clock initialization before the lcd_clk, since the elcdif_clk needs to be initialized ahead of lcd_clk, being its parent. This change fixes issues with the LCD clocks during suspend/resume. Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks") Suggested-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Acked-by: Laurentiu Palcu <laurentiu.palcu@nxp.com> Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230912-imx8-clk-v1-v1-2-69a34bcfcae1@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx8dxl-rsrc: keep sorted in the ascending orderViorel Suman
Entries in imx8dxl_clk_scu_rsrc_table must be kept in the ascending order, and IMX_SC_R_M4_0_UART < IMX_SC_R_M4_0_I2C. Fixes: 036a4b4b4dfa ("clk: imx: Add imx8dxl clk driver") Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230912-imx8-clk-v1-v1-1-69a34bcfcae1@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx6sx: Allow a different LCDIF1 clock parentFabio Estevam
It is not a good idea to hardcode the LCDIF1 parent inside the clock driver because some users may want to use a different clock parent for LCDIF1. One of the reasons could be related to EMI tests. Remove the harcoded LCDIF1 parent when the LCDIF1 parent is described via devicetree. Old dtb's that do not describe the LCDIF1 parent via devicetree will use the same PLL5 clock as parent to keep the original behavior. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230815130923.775117-1-festevam@gmail.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx8mq: correct error handling pathPeng Fan
Avoid memory leak in error handling path. It does not make much sense for the SoC without clk driver, to make program behavior correct, let's fix it. Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <error27@gmail.com> Closes: https://lore.kernel.org/r/202309240551.e46NllPa-lkp@intel.com/ Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20231001122618.194498-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx8: Simplify clk_imx_acm_detach_pm_domains()Christophe JAILLET
The return value of clk_imx_acm_detach_pm_domains() is never used. Simplify the code and turn it into a void function. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx8: Add a message in case of ↵Christophe JAILLET
devm_clk_hw_register_mux_parent_data_table() error If devm_clk_hw_register_mux_parent_data_table() fails, we branch to the error handling path and imx_check_clk_hws() is never called. Actually, imx_check_clk_hws() is a no-op because values in 'hws' are either valid, either NULL. Move the call to imx_check_clk_hws() in the error handling path, so that an error is logged. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx8: Fix an error handling path in imx8_acm_clk_probe()Christophe JAILLET
If an error occurs after a successful clk_imx_acm_attach_pm_domains() call, it must be undone. Add an explicit error handling path, re-order the code and add the missing clk_imx_acm_detach_pm_domains() call. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx8: Fix an error handling path if ↵Christophe JAILLET
devm_clk_hw_register_mux_parent_data_table() fails If a devm_clk_hw_register_mux_parent_data_table() call fails, it is likely that the probe should fail with an error code. Set 'ret' before leaving the function. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: imx8: Fix an error handling path in clk_imx_acm_attach_pm_domains()Christophe JAILLET
If a dev_pm_domain_attach_by_id() call fails, previously allocated resources need to be released. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-10-04clk: imx: Select MXC_CLK for CLK_IMX8QXPAbel Vesa
If the i.MX8QXP clock provider is built-in but the MXC_CLK is built as module, build fails: aarch64-linux-ld: drivers/clk/imx/clk-imx8-acm.o: in function `imx8_acm_clk_probe': clk-imx8-acm.c:(.text+0x3d0): undefined reference to `imx_check_clk_hws' Fix that by selecting MXC_CLK in case of CLK_IMX8QXP. Fixes: c2cccb6d0b33 ("clk: imx: add imx8qxp clk driver") Closes: https://lore.kernel.org/all/8b77219e-b59e-40f1-96f1-980a0b2debcf@infradead.org/ Reported-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controllerYu Tu
Add the peripherals clock controller driver in the S4 SoC family. [jbrunet: remove extra new line at end of s4-peripherals.h] Signed-off-by: Yu Tu <yu.tu@amlogic.com> Link: https://lore.kernel.org/r/20230904075504.23263-5-yu.tu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC PLL clock driverYu Tu
Add the S4 PLL clock controller driver in the S4 SoC family. Signed-off-by: Yu Tu <yu.tu@amlogic.com> Link: https://lore.kernel.org/r/20230904075504.23263-4-yu.tu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
generated by cgit (git 2.34.1) at 2025-09-18 00:28:03 +0000