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2023-09-26clk: renesas: r8a7795: Constify r8a7795_*_clksMarek Vasut
Make r8a7795_core_clks and r8a7795_mod_clks arrays const and align them with the other clock tables in other *cpg-mssr.c . No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230917095832.39007-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-09-20clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_srcDanila Tikhonov
Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") Tested-by: Arseniy Velikanov <adomerlee@gmail.com> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230913175612.8685-1-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-20Merge branch '20230909123431.1725728-1-quic_ajipan@quicinc.com' into clk-for-6.7Bjorn Andersson
Merge the SM4450 RPMHCC and GCC through a topic branch, to allow reuse of the defines from the DeviceTree binding in the DeviceTree source.
2023-09-20clk: qcom: Add GCC driver support for SM4450Ajit Pandey
Add Global Clock Controller (GCC) support for SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230909123431.1725728-5-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-20clk: qcom: rpmh: Add RPMH clocks support for SM4450Ajit Pandey
Add support for RPMH clocks for SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230909123431.1725728-3-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-20clk: qcom: mmcc-msm8974: remove ocmemcx_ahb_clkLuca Weiss
According to a commit in the 3.4 vendor kernel sources[0] the ocmemcx_ahb_clk clock "is controlled by RPM and should not be touched by APPS.". [0] https://git.codelinaro.org/clo/la/kernel/msm/-/commit/37df5f2d91b4d5768b37fcaacaeea958dd683ebc And indeed, when using MDSS+GPU+OCMEM on MSM8226 and not using clk_ignore_unused, when Linux tries to disable the clock the device crashes and reboots. And since there's also no evidence of this clock in msm8974 vendor kernel sources, remove the clock for msm8226 and msm8974. Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230902-msm8226-ocmemcx_ahb_clk-remove-v1-1-8124dbde83b9@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-20clk: scmi: Add support for .is_enabled clk_opsCristian Marussi
Add support for .is_enabled atomic clk_ops using the related SCMI clock operation in atomic mode, if available. Note that the .is_enabled callback will be supported by this SCMI clock driver only if the configured underlying SCMI transport does support atomic operations. CC: Michael Turquette <mturquette@baylibre.com> CC: Stephen Boyd <sboyd@kernel.org> CC: linux-clk@vger.kernel.org Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230826125308.462328-6-cristian.marussi@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2023-09-20firmware: arm_scmi: Simplify enable/disable clock operationsCristian Marussi
SCMI clock enable/disable operations come in 2 different flavours which simply just differ in how the underlying SCMI transactions is carried on: atomic or not. Currently we expose such SCMI operations through 2 distinctly named wrappers, that, in turn, are wrapped into another couple of similarly and distinctly named callbacks inside SCMI clock driver user. Reduce the churn of duplicated wrappers by adding a param to SCMI clock enable/disable operations to ask for atomic operation while removing the _atomic version of such operations. No functional change. CC: Michael Turquette <mturquette@baylibre.com> CC: Stephen Boyd <sboyd@kernel.org> CC: linux-clk@vger.kernel.org Signed-off-by: Cristian Marussi <cristian.marussi@arm.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230826125308.462328-2-cristian.marussi@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2023-09-20clk: qcom: mmcc-msm8998: Fix the SMMU GDSCKonrad Dybcio
The SMMU GDSC doesn't have to be ALWAYS-ON and shouldn't feature the HW_CTRL flag (it's separate from hw_ctrl_addr). In addition to that, it should feature a cxc entry for bimc_smmu_axi_clk and be marked as votable. Fix all of these issues. Fixes: d14b15b5931c ("clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20230531-topic-8998_mmssclk-v3-5-ba1b1fd9ee75@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-20clk: qcom: mmcc-msm8998: Don't check halt bit on some branch clksKonrad Dybcio
Some branch clocks are governed externally and we're only supposed to send a request concerning their shutdown, not actually ensure it happens. Use the BRANCH_HALT_SKIP define to skip checking the halt bit. Fixes: d14b15b5931c ("clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driver") Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230531-topic-8998_mmssclk-v3-4-ba1b1fd9ee75@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19clk: qcom: clk-rcg2: Fix clock rate overflow for high parent frequenciesDevi Priya
If the parent clock rate is greater than unsigned long max/2 then integer overflow happens when calculating the clock rate on 32-bit systems. As RCG2 uses half integer dividers, the clock rate is first being multiplied by 2 which will overflow the unsigned long max value. Hence, replace the common pattern of doing 64-bit multiplication and then a do_div() call with simpler mult_frac call. Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCGs)") Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20230901073640.4973-1-quic_devipriy@quicinc.com [bjorn: Also drop unnecessary {} around single statements] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19clk: qcom: gcc-msm8996: Remove RPM bus clocksKonrad Dybcio
The GCC driver contains clocks that are owned (meaning configured and scaled) by the RPM core. Remove them from Linux to stop interjecting the RPM's logic. Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230830-topic-rpmbusclocks8996gcc-v1-1-9e99bedcdc3b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocksVaradarajan Narayanan
IPQ5332's GPLL0's nominal/turbo frequency is 800MHz. This must not be scaled based on the requirement of dependent clocks. Hence remove the CLK_SET_RATE_PARENT flag. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Kathiravan T <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/1693474133-10467-1-git-send-email-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19Merge branch '20230707035744.22245-2-quic_jkona@quicinc.com' into clk-for-6.7Bjorn Andersson
Merge the SM8550 camera clock controller patches through a topic branch, to make them available for the DeviceTree source as well.
2023-09-19clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocksJagadeesh Kona
Add support for camera qdss, sleep and xo clocks. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230707035744.22245-5-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550Jagadeesh Kona
Add support for the camera clock controller for camera clients to be able to request for camcc clocks on SM8550 platform. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230707035744.22245-4-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19clk: qcom: clk-alpha-pll: Add support for lucid ole pll configureJagadeesh Kona
Lucid ole pll has as extra RINGOSC_CAL_L field in L register in addition to the fields that are part of lucid evo pll, hence add support for lucid ole pll configure function to configure the ole plls. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230707035744.22245-3-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-18clk: renesas: r9a06g032: Name anonymous structsRalph Siemsen
Clarify the content of the r9a06g032_clkdesc structure by naming the remaining anonymous structures defined inside. Renaming each field and updating the doc then becomes necessary in order to avoid name duplications and kdoc warnings. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230913203805.465780-2-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-09-18clk: renesas: r9a06g032: Fix kerneldoc warningRalph Siemsen
Mention the 'dual' structure in the kdoc. This fixes the following W=1 warning during build: > drivers/clk/renesas/r9a06g032-clocks.c:119: warning: Function parameter or member 'dual' not described in 'r9a06g032_clkdesc' Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202309101314.kTRoxND5-lkp@intel.com/ Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230913203805.465780-1-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-09-18clk: renesas: rzg2l: Use u32 for flag and mux_flagsClaudiu Beznea
flag and mux_flags are intended to keep bit masks. Use u32 type for it. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230912045157.177966-15-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-09-18clk: renesas: rzg2l: Use FIELD_GET() for PLL register fieldsClaudiu Beznea
Use FIELD_GET() for PLL register fields. This is its purpose. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230912045157.177966-14-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-09-18clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()Claudiu Beznea
The bitmask << 16 is anyway set on both branches of if thus move it before the if and set the lower bits of registers only in case clock is enabled. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230912045157.177966-12-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-09-18clk: renesas: rzg2l: Use core->name for clock nameClaudiu Beznea
core->name already contains the clock name thus, there is no need to check the GET_SHIFT(core->conf) to decide on it. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230912045157.177966-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-09-13clk: qcom: hfpll: Add MSM8976 PLL dataAdam Skladowski
Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL. Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz. For simplicity only add second range as smaller frequencies can be obtained via apcs divider or safe parent this also saves us a hassle of reconfiguring VCO bit and config_val. A72 and CCI cluster only use single frequency range with their outputs/post_dividers/vco_bits being static. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230812112534.8610-6-a39.skl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-13clk: qcom: hfpll: Allow matching pdataAdam Skladowski
HFPLL driver can be used to drive PLLs also on different SoCs like MSM8976 On MSM8976 each PLL gets it own different configuration, add matching pdata to driver to support multiple configurations. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230812112534.8610-4-a39.skl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-13clk: qcom: clk-hfpll: Configure l_val in init when requiredAdam Skladowski
Add support for pre-configuring default frequency multiplier, this appears to be required on some platforms like MSM8976. Without configuring L_VAL device reboots when trying to bring PLL up. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230812112534.8610-3-a39.skl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-12clk: tegra: fix error return case for recalc_rateTimo Alho
tegra-bpmp clocks driver makes implicit conversion of signed error code to unsigned value in recalc_rate operation. The behavior for recalc_rate, according to it's specification, should be that "If the driver cannot figure out a rate for this clock, it must return 0." Fixes: ca6f2796eef7 ("clk: tegra: Add BPMP clock driver") Signed-off-by: Timo Alho <talho@nvidia.com> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Link: https://lore.kernel.org/r/20230912112951.2330497-1-cyndis@kapsi.fi Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-09-11clk: si521xx: Fix regmap write accessorMarek Vasut
Rework the write operation such that the Byte Count register is written with a single raw i2c write outside of regmap using transfer which does specify the number of bytes to be transfered, one in this case, and which makes the expected subsequent write transfer look like address+register+data, and then make use of this method. Without this change, the Byte Count register write in probe() would succeed as it would provide the byte count as part of its write payload, but any subsequent writes would fail due to this Byte Count register programming. Such failing writes happens e.g. during resume, when restoring the regmap content. Fixes: edc12763a3a2 ("clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators") Signed-off-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20230831181656.154750-2-marex@denx.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-09-11clk: si521xx: Use REGCACHE_FLAT instead of NONEMarek Vasut
In order to reload registers into the clock generator on resume using regcache_sync(), it is necessary to select one of the regcache types which are not NONE. Since this device has some 7 registers, use the simplest one, FLAT. The regcache code complains about REGCACHE_NONE being selected and generates a WARNING, this fixes that warning. Fixes: edc12763a3a2 ("clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators") Signed-off-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20230831181656.154750-1-marex@denx.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-09-11clk: sprd: Fix thm_parents incorrect configurationZhifeng Tang
The thm*_clk have two clock sources 32k and 250k,excluding 32m. Fixes: af3bd36573e3 ("clk: sprd: Add clocks support for UMS512") Signed-off-by: Zhifeng Tang <zhifeng.tang@unisoc.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com> Link: https://lore.kernel.org/r/20230824092624.20020-1-zhifeng.tang@unisoc.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-09-11clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum valuesBiju Das
Make vc3_clk_mux enum values depend upon vc3_clk enum values to avoid any accidental breakage in the future. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20230824104812.147775-5-biju.das.jz@bp.renesas.com Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-09-11clk: vc3: Fix output clock mappingBiju Das
According to Table 3. ("Output Source") in the 5P35023 datasheet, the output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3, 4=DIFF1, 5=DIFF2. But the code uses inverse. Fix this mapping issue. Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> Closes: https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpaejss0Y2ZpLCMNg@mail.gmail.com/ Fixes: 6e9aff555db7 ("clk: Add support for versa3 clock driver") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230824104812.147775-4-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-09-11clk: vc3: Fix 64 by 64 divisionBiju Das
Fix the below cocci warnings by replacing do_div()->div64_ul() and bound the result with a max value of U16_MAX. cocci warnings: drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. Reported-by: Julia Lawall <julia.lawall@inria.fr> Closes: https://lore.kernel.org/r/202307270841.yr5HxYIl-lkp@intel.com/ Fixes: 6e9aff555db7 ("clk: Add support for versa3 clock driver") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20230824104812.147775-3-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-09-11clk: gate: fix comment typo and grammarBaruch Siach
Change ouput -> output. While at it change also grammatically incorrect "it's" to "its". Signed-off-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/d47978a09dd0320f9929a19fa3e829608a02b224.1693485415.git.baruch@tkos.co.il Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-09-11clk: asm9620: Remove 'hw' local variable that isn't checkedStephen Boyd
The 'hw' pointer local variable in this function became unused after commit f5290d8e4f0c ("clk: asm9260: use parent index to link the reference clock"). Remove it to silence an unused but set variable warning. drivers/clk/clk-asm9260.c:258:17: warning: variable 'hw' set but not used [-Wunused-but-set-variable] struct clk_hw *hw, *pll_hw; ^ 1 warning generated. Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: f5290d8e4f0c ("clk: asm9260: use parent index to link the reference clock") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202309042014.IWERPl09-lkp@intel.com/ Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230909000703.3478902-1-sboyd@kernel.org
2023-09-11clk: renesas: r9a06g032: Use for_each_compatible_node()Yang Yingliang
Use for_each_compatible_node() instead of open-coding it. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230802091920.3270703-1-yangyingliang@huawei.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-08-30Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk subsystem updates from Stephen Boyd: "This pull request is full of clk driver changes. In fact, there aren't any changes to the clk framework this time around. That's probably because everyone was on vacation (yours truly included). We did lose a couple clk drivers this time around because nobody was using those devices. That skews the diffstat a bit, but either way, nothing looks out of the ordinary here. The usual suspects are chugging along adding support for more SoCs and fixing bugs. If I had to choose, I'd say the theme for the past few months has been "polish". There's quite a few patches that migrate to devm_platform_ioremap_resource() in here. And there's more than a handful of patches that move the NR_CLKS define from the DT binding header to the driver. There's even patches that migrate drivers to use clk_parent_data and clk_hw to describe clk tree topology. It seems that the spring (summer?) cleaning bug got some folks, or the semiconductor shortage finally hit the software side. New Drivers: - StarFive JH7110 SoC clock drivers - Qualcomm IPQ5018 Global Clock Controller driver - Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK Removed Drivers: - Remove non-OF mmp clk drivers - Remove OXNAS clk driver Updates: - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Move defines for numbers of clks (NR_CLKS) from DT headers to drivers - Introduce kstrdup_and_replace() and use it - Add PLL rates for Rockchip rk3568 - Add the display clock tree for Rockchip rv1126 - Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and RZ/G2 SoCs - Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource() - Fix function name in a comment in ccu_mmc_timing.c - Parameter name correction for ccu_nkm_round_rate() - Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e. consider alternative parent rates when determining clock rates - Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi - Support finding closest (as opposed to closest but not higher) clock rate for NM, NKM, mux and div type clocks, as use it for Allwinner A64 pll-video0 - Prefer current parent rate if able to generate ideal clock rate for Allwinner NKM clocks - Clean up Qualcomm SMD RPM driver, with interconnect bus clocks moved out to the interconnect drivers - Fix various PM runtime bugs across many Qualcomm clk drivers - Migrate Qualcomm MDM9615 is to parent_hw and parent_data - Add network related resets on Qualcomm IPQ4019 - Add a couple missing USB related clocks to Qualcomm IPQ9574 - Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock controller - In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs, and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are corrected - Add missing GDSCs to and correct GDSCs for the SC8280XP global clock controller driver - Support retention for the Qualcomm SC8280XP display clock controller GDSCs. - Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE to fix issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250, while sm8450 is corrected to use floor ops - Correct Qualcomm SM6350 GPU clock controller's clock supplies - Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver - Add missing OXILICX GDSC to Qualcomm MSM8226 GCC - Change the delay in the Qualcomm reset controller to fsleep() for correctness - Extend the Qualcomm SM83550 Video clock controller to support SC8280XP - Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3, M3-W, and M3-N SoCs - Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M - Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five - Add the PDM IPC clock for i.MX93 - Add 519.75MHz frequency support for i.MX9 PLL - Simplify the .determine_rate() implementation for i.MX GPR mux - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource() - Add the audio mux clock to i.MX8 - Fix the SPLL2 MULT range for PLLv4 - Update the SPLL2 type in i.MX8ULP - Fix the SAI4 clock on i.MX8MP - Add silicon revision print for i.MX25 on clocks init - Drop the return value from __mx25_clocks_init() - Fix the clock pauses on no-op set_rate for i.MX8M composite clock - Drop restrictions for i.MX PLL14xx and fix its max prediv value - Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to allow glitch free switching" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (207 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source ...
2023-08-30Merge branch 'clk-qcom' into clk-nextStephen Boyd
* clk-qcom: (87 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags clk: qcom: gcc-ipq5018: change some variable static clk: qcom: gcc-ipq4019: add missing networking resets dt-bindings: clock: qcom: ipq4019: add missing networking resets clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC clk: qcom: gcc-qdu1000: Update the RCGs ops clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops clk: qcom: gcc-qdu1000: Add support for GDSCs clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock clk: qcom: gcc-qdu1000: Fix clkref clocks handling clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock clk: qcom: ipq5332: drop the mem noc clocks clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks ...
2023-08-30Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and ↵Stephen Boyd
'clk-lmk' into clk-next - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Remove non-OF mmp clk drivers - Move number of clks from DT headers to drivers * clk-imx: clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz clk: imx: pll14xx: align pdiv with reference manual clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op clk: imx25: make __mx25_clocks_init return void clk: imx25: print silicon revision during init dt-bindings: clocks: imx8mp: make sai4 a dummy clock clk: imx8mp: fix sai4 clock clk: imx: imx8ulp: update SPLL2 type clk: imx: pllv4: Fix SPLL2 MULT range clk: imx: imx8: add audio clock mux driver dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource() clk: imx: clk-gpr-mux: Simplify .determine_rate() clk: imx: Add 519.75MHz frequency support for imx9 pll clk: imx93: Add PDM IPG clk dt-bindings: clock: imx93: Add PDM IPG clk * clk-samsung: dt-bindings: clock: samsung: remove define with number of clocks clk: samsung: exynoautov9: do not define number of clocks in bindings clk: samsung: exynos850: do not define number of clocks in bindings clk: samsung: exynos7885: do not define number of clocks in bindings clk: samsung: exynos5433: do not define number of clocks in bindings clk: samsung: exynos5420: do not define number of clocks in bindings clk: samsung: exynos5410: do not define number of clocks in bindings clk: samsung: exynos5260: do not define number of clocks in bindings clk: samsung: exynos5250: do not define number of clocks in bindings clk: samsung: exynos4: do not define number of clocks in bindings clk: samsung: exynos3250: do not define number of clocks in bindings * clk-annotate: clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by clk: Annotate struct clk_hw_onecell_data with __counted_by * clk-marvell: clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source clk: mmp: Remove old non-OF clock drivers * clk-lmk: clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks
2023-08-30Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ↵Stephen Boyd
'clk-rockchip' into clk-next - Add Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK - Introduce kstrdup_and_replace() and use it * clk-versa: clk: vc7: Use i2c_get_match_data() instead of device_get_match_data() clk: vc5: Use i2c_get_match_data() instead of device_get_match_data() clk: versaclock3: Switch to use i2c_driver's probe callback clk: Add support for versa3 clock driver dt-bindings: clock: Add Renesas versa3 clock generator bindings * clk-strdup: clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace() clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace() driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace() lib/string_helpers: Add kstrdup_and_replace() helper * clk-amlogic: (22 commits) dt-bindings: soc: amlogic: document System Control registers dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema clk: meson: axg-audio: move bindings include to main driver clk: meson: meson8b: move bindings include to main driver clk: meson: a1: move bindings include to main driver clk: meson: eeclk: move bindings include to main driver clk: meson: aoclk: move bindings include to main driver dt-bindings: clk: axg-audio-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids dt-bindings: clk: meson8b-clkc: expose all clock ids dt-bindings: clk: g12a-aoclkc: expose all clock ids dt-bindings: clk: g12a-clks: expose all clock ids dt-bindings: clk: axg-clkc: expose all clock ids dt-bindings: clk: gxbb-clkc: expose all clock ids clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS ... * clk-allwinner: clk: sunxi-ng: nkm: Prefer current parent rate clk: sunxi-ng: a64: select closest rate for pll-video0 clk: sunxi-ng: div: Support finding closest rate clk: sunxi-ng: mux: Support finding closest rate clk: sunxi-ng: nkm: Support finding closest rate clk: sunxi-ng: nm: Support finding closest rate clk: sunxi-ng: Add helper function to find closest rate clk: sunxi-ng: Add feature to find closest rate clk: sunxi-ng: a64: allow pll-mipi to set parent's rate clk: sunxi-ng: nkm: consider alternative parent rates when determining rate clk: sunxi-ng: nkm: Use correct parameter name for parent HW clk: sunxi-ng: Modify mismatched function name clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource() * clk-rockchip: clk: rockchip: rv1126: Add PD_VO clock tree clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz clk: rockchip: rk3568: Add PLL rate for 101MHz
2023-08-30Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and ↵Stephen Boyd
'clk-cleanup' into clk-next - Remove OXNAS clk driver * clk-bindings: dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml dt-bindings: clock: xlnx,versal-clk: drop select:false dt-bindings: clock: versal: Add versal-net compatible string dt-bindings: clock: ast2600: Add I3C and MAC reset definitions dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding * clk-starfive: reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support clk: starfive: Simplify .determine_rate() clk: starfive: Add StarFive JH7110 Video-Output clock driver clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver clk: starfive: Add StarFive JH7110 System-Top-Group clock driver clk: starfive: jh7110-sys: Add PLL clocks source from DTS clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs dt-bindings: soc: starfive: Add StarFive syscon module dt-bindings: clock: Add StarFive JH7110 PLL clock generator * clk-rm: dt-bindings: clk: oxnas: remove obsolete bindings clk: oxnas: remove obsolete clock driver * clk-renesas: clk: renesas: rcar-gen3: Add ADG clocks clk: renesas: r8a77965: Add 3DGE and ZG support clk: renesas: r8a7796: Add 3DGE and ZG support clk: renesas: r8a7795: Add 3DGE and ZG support clk: renesas: emev2: Remove obsolete clkdev registration clk: renesas: r9a07g043: Add MTU3a clock and reset entry clk: renesas: rzg2l: Simplify .determine_rate() clk: renesas: r9a09g011: Add CSI related clocks clk: renesas: r8a774b1: Add 3DGE and ZG support clk: renesas: r8a774e1: Add 3DGE and ZG support clk: renesas: r8a774a1: Add 3DGE and ZG support clk: renesas: rcar-gen3: Add support for ZG clock * clk-cleanup: clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init() clk: Explicitly include correct DT includes
2023-08-29clk: qcom: Fix SM_GPUCC_8450 dependenciesNathan Chancellor
CONFIG_SM_GCC_8450 depends on ARM64 but it is selected by CONFIG_SM_GPUCC_8450, which can be selected on ARM, resulting in a Kconfig warning. WARNING: unmet direct dependencies detected for SM_GCC_8450 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n]) Selected by [y]: - SM_GPUCC_8450 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] Add the same dependencies to CONFIG_SM_GPUCC_8450 to resolve the warning. Fixes: 728692d49edc ("clk: qcom: Add support for SM8450 GPUCC") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20230829-fix-sm_gpucc_8550-deps-v1-1-d751f6cd35b2@kernel.org Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: lmk04832: Support using PLL1_LD as SPI readback pinMike Looijmans
The PLL1_PD pin (a.k.a. STATUS_LD1) can be used as SPI readback pin. Make this possible. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Link: https://lore.kernel.org/r/20230802064100.15793-3-mike.looijmans@topic.nl Reviewed-by: Liam Beguin <liambeguin@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: lmk04832: Don't disable vco clock on probe failMike Looijmans
The probe() method never calls clk_prepare_enable(), so it should not call clk_disable_unprepare() for the vco.clk in the error path. Fixes a "lmk-vco already disabled" BUG when probe fails. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Link: https://lore.kernel.org/r/20230802064100.15793-2-mike.looijmans@topic.nl Reviewed-by: Liam Beguin <liambeguin@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-23clk: lmk04832: Set missing parent_names for output clocksMike Looijmans
lmk04832_register_clkout forgot to fill in the parent_names, resulting in the error message "Must specify parents if num_parents > 0". Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Link: https://lore.kernel.org/r/20230802064100.15793-1-mike.looijmans@topic.nl Reviewed-by: Liam Beguin <liambeguin@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22clk: Fix slab-out-of-bounds error in devm_clk_release()Andrey Skvortsov
Problem can be reproduced by unloading snd_soc_simple_card, because in devm_get_clk_from_child() devres data is allocated as `struct clk`, but devm_clk_release() expects devres data to be `struct devm_clk_state`. KASAN report: ================================================================== BUG: KASAN: slab-out-of-bounds in devm_clk_release+0x20/0x54 Read of size 8 at addr ffffff800ee09688 by task (udev-worker)/287 Call trace: dump_backtrace+0xe8/0x11c show_stack+0x1c/0x30 dump_stack_lvl+0x60/0x78 print_report+0x150/0x450 kasan_report+0xa8/0xf0 __asan_load8+0x78/0xa0 devm_clk_release+0x20/0x54 release_nodes+0x84/0x120 devres_release_all+0x144/0x210 device_unbind_cleanup+0x1c/0xac really_probe+0x2f0/0x5b0 __driver_probe_device+0xc0/0x1f0 driver_probe_device+0x68/0x120 __driver_attach+0x140/0x294 bus_for_each_dev+0xec/0x160 driver_attach+0x38/0x44 bus_add_driver+0x24c/0x300 driver_register+0xf0/0x210 __platform_driver_register+0x48/0x54 asoc_simple_card_init+0x24/0x1000 [snd_soc_simple_card] do_one_initcall+0xac/0x340 do_init_module+0xd0/0x300 load_module+0x2ba4/0x3100 __do_sys_init_module+0x2c8/0x300 __arm64_sys_init_module+0x48/0x5c invoke_syscall+0x64/0x190 el0_svc_common.constprop.0+0x124/0x154 do_el0_svc+0x44/0xdc el0_svc+0x14/0x50 el0t_64_sync_handler+0xec/0x11c el0t_64_sync+0x14c/0x150 Allocated by task 287: kasan_save_stack+0x38/0x60 kasan_set_track+0x28/0x40 kasan_save_alloc_info+0x20/0x30 __kasan_kmalloc+0xac/0xb0 __kmalloc_node_track_caller+0x6c/0x1c4 __devres_alloc_node+0x44/0xb4 devm_get_clk_from_child+0x44/0xa0 asoc_simple_parse_clk+0x1b8/0x1dc [snd_soc_simple_card_utils] simple_parse_node.isra.0+0x1ec/0x230 [snd_soc_simple_card] simple_dai_link_of+0x1bc/0x334 [snd_soc_simple_card] __simple_for_each_link+0x2ec/0x320 [snd_soc_simple_card] asoc_simple_probe+0x468/0x4dc [snd_soc_simple_card] platform_probe+0x90/0xf0 really_probe+0x118/0x5b0 __driver_probe_device+0xc0/0x1f0 driver_probe_device+0x68/0x120 __driver_attach+0x140/0x294 bus_for_each_dev+0xec/0x160 driver_attach+0x38/0x44 bus_add_driver+0x24c/0x300 driver_register+0xf0/0x210 __platform_driver_register+0x48/0x54 asoc_simple_card_init+0x24/0x1000 [snd_soc_simple_card] do_one_initcall+0xac/0x340 do_init_module+0xd0/0x300 load_module+0x2ba4/0x3100 __do_sys_init_module+0x2c8/0x300 __arm64_sys_init_module+0x48/0x5c invoke_syscall+0x64/0x190 el0_svc_common.constprop.0+0x124/0x154 do_el0_svc+0x44/0xdc el0_svc+0x14/0x50 el0t_64_sync_handler+0xec/0x11c el0t_64_sync+0x14c/0x150 The buggy address belongs to the object at ffffff800ee09600 which belongs to the cache kmalloc-256 of size 256 The buggy address is located 136 bytes inside of 256-byte region [ffffff800ee09600, ffffff800ee09700) The buggy address belongs to the physical page: page:000000002d97303b refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x4ee08 head:000000002d97303b order:1 compound_mapcount:0 compound_pincount:0 flags: 0x10200(slab|head|zone=0) raw: 0000000000010200 0000000000000000 dead000000000122 ffffff8002c02480 raw: 0000000000000000 0000000080100010 00000001ffffffff 0000000000000000 page dumped because: kasan: bad access detected Memory state around the buggy address: ffffff800ee09580: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ffffff800ee09600: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >ffffff800ee09680: 00 fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ^ ffffff800ee09700: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ffffff800ee09780: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ================================================================== Fixes: abae8e57e49a ("clk: generalize devm_clk_get() a bit") Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Link: https://lore.kernel.org/r/20230805084847.3110586-1-andrej.skvortzov@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22clk: mvebu: Convert to devm_platform_ioremap_resource()Yangtao Li
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-13-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22clk: nuvoton: Convert to devm_platform_ioremap_resource()Yangtao Li
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-12-frank.li@vivo.com Acked-by: Jacky Huang <ychuang3@nuvoton.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()Yangtao Li
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-11-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22clk: ti: Use devm_platform_get_and_ioremap_resource()Yangtao Li
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705065313.67043-10-frank.li@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-18 02:28:38 +0000