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path: root/drivers/clk
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2023-01-29clk: imx: imx93: invoke imx_register_uart_clocksPeng Fan
Invoke imx_register_uart_clocks to keep uart clk on when earlycon specified. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-5-peng.fan@oss.nxp.com
2023-01-29clk: imx: remove clk_count of imx_register_uart_clocksPeng Fan
The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com
2023-01-29clk: imx: get stdout clk count from device treePeng Fan
Currently the clk_count is specified by API users, but this parameter is wrongly used, for example, i.MX8M clk driver use 4, however the uart device tree node only use 2 clock entries. So let using of_clk_get_parent_count to get the exact clock count. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-3-peng.fan@oss.nxp.com
2023-01-29clk: imx: avoid memory leakPeng Fan
In case imx_register_uart_clocks return early, the imx_uart_clocks memory will be no freed. So execute kfree always to avoid memory leak. Fixes: 379c9a24cc23 ("clk: imx: Fix reparenting of UARTs not associated with stdout") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-2-peng.fan@oss.nxp.com
2023-01-26clk: renesas: r8a779g0: Add CAN-FD clocksGeert Uytterhoeven
Add the CANFD core clock and the CANFD0 module clock, which are used by the CAN-FD Interface on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a78f534bd80f170f3f1267f3270fdb3b7a73b5d4.1674498643.git.geert+renesas@glider.be
2023-01-26clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMACKuninori Morimoto
"sydm" is a bit name. Let's rename it to the common "sys-dmac". Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87v8l3z3y8.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-26clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMACKuninori Morimoto
"sydm" is a bit name. Let's rename it to the common "sys-dmac". Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87tu0nz3xr.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-25clk: ingenic: jz4760: Update M/N/OD calculation algorithmPaul Cercueil
The previous algorithm was pretty broken. - The inner loop had a '(m > m_max)' condition, and the value of 'm' would increase in each iteration; - Each iteration would actually multiply 'm' by two, so it is not needed to re-compute the whole equation at each iteration; - It would loop until (m & 1) == 0, which means it would loop at most once. - The outer loop would divide the 'n' value by two at the end of each iteration. This meant that for a 12 MHz parent clock and a 1.2 GHz requested clock, it would first try n=12, then n=6, then n=3, then n=1, none of which would work; the only valid value is n=2 in this case. Simplify this algorithm with a single for loop, which decrements 'n' after each iteration, addressing all of the above problems. Fixes: bdbfc029374f ("clk: ingenic: Add support for the JZ4760") Cc: <stable@vger.kernel.org> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20221214123704.7305-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-24clk: renesas: r8a779g0: Add custom clock for PLL2Geert Uytterhoeven
Currently the PLLs are modeled as fixed factor clocks, based on initial settings. However, enabling CPU boost clock rates requires increasing the PLL clock rates. Add a custom clock driver to model the PLL clocks on R-Car Gen4, and use it for PLL2 on R-Car V4H. This allows the Z clock (Cortex-A76 core clock) to request PLL rate changes, and enable boost mode for the High Performance mode. For now this is limited to integer multiplication modes. Note that the definition for CPG_PLLxCR0_NI uses the value for R-Car V4H. On R-Car S4-8, the integer and fractional multiplication fields are one bit larger resp. smaller, but R-Car S4-8 does not support High Performance mode. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/76a5952900a6e15604c640bc8a27762e0e936677.1670492384.git.geert+renesas@glider.be
2023-01-23clk: renesas: cpg-mssr: Remove superfluous check in resume codeGeert Uytterhoeven
When the code flow arrives at printing the error message in cpg_mssr_resume_noirq(), we know for sure that we are not running on an RZ/A Soc, as the code checked for that before. Fixes: ace342097768e35f ("clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/144a3e66d748c0c17f3524ac8fa6ece5bf5b6f1e.1673425314.git.geert+renesas@glider.be
2023-01-23clk: renesas: r9a06g032: Handle h2mode setting based on USBF presenceHerve Codina
The CFG_USB[H2MODE] allows to switch the USB configuration. The configuration supported are: - One host and one device or - Two hosts Set CFG_USB[H2MODE] based on the USBF controller (USB device) availability. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230105152257.310642-3-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-19clk: microchip: mpfs-ccc: Use devm_kasprintf() for allocating formatted stringsGeert Uytterhoeven
In various places, string buffers of a fixed size are allocated, and filled using snprintf() with the same fixed size, which is error-prone. Replace this by calling devm_kasprintf() instead, which always uses the appropriate size. While at it, remove an unneeded intermediate variable, which allows us to drop a cast as a bonus. With the initial behavior it would have been possible to have a device tree with a node address that would make "ccc<node_address>_pll<N>" exceed 18 characters. If that happened, the <N> would be cut off & both pll 0 & 1 would be named identically. If that happens, pll1 would fail to register. Thus, the fixes tag has been added to this commit. Fixes: d39fb172760e ("clk: microchip: add PolarFire SoC fabric clock support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> [claudiu.beznea: added the rationale behind fixes tag] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/f904fd28b2087d1463ea65f059924e3b1acc193c.1672764239.git.geert+renesas@glider.be
2023-01-18clk: qcom: cpu-8996: change setup sequence to follow vendor kernelDmitry Baryshkov
Add missing register writes to CPU clocks setup procedure. This makes it follow the setup procedure used in msm-3.18 kernel. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-14-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: fix PLL clock opsDmitry Baryshkov
Switch CPU PLLs to use clk_alpha_pll_hwfsm_ops, it seems to suit better. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-13-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: fix ACD initializationDmitry Baryshkov
The vendor kernel applies different order while programming SSSCTL and L2ACDCR registers on power and performance clusters. However it was demonstrated that doing this upstream results in the board reset. Make both clusters use the same sequence, which fixes the reset. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-12-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: fix PLL configuration sequenceDmitry Baryshkov
Switch both power and performance clocks to the GPLL0/2 (sys_apcs_aux) before PLL configuration. Switch them to the ACD afterwards. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-11-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: move qcom_cpu_clk_msm8996_acd_init callDmitry Baryshkov
Initialize ACD configuration from qcom_cpu_clk_msm8996_register_clks(), before registering all clocks. This way we can be sure that the clock is fully configured before letting CCF touch it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-10-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: setup PLLs before registering clocksDmitry Baryshkov
Setup all PLLs before registering clocks in the common clock framework. This ensures that the clocks are not accessed before being setup in the known way and that the CCF is in sync with the actual HW programming. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-9-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cbDmitry Baryshkov
- Do not use the Alt PLL completely. Switch to smux when necessary to prevent overvolting - Restore the parent in case the rate change aborts for some reason - Do not duplicate resetting the parent in set_parent operation. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-8-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: skip ACD init if the setup is validDmitry Baryshkov
Check whether L2 registers contain correct values and skip programming if they are valid. This follows the code present downstream. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-7-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: support using GPLL0 as SMUX inputDmitry Baryshkov
In some cases the driver might need using GPLL0 to drive CPU clocks. Bring it in through the sys_apcs_aux clock. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-6-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: fix the init clock rateDmitry Baryshkov
Current multiplier (60) results in CPU getting the rate which is unlisted in the CPU frequency tables (60 * 19.2 = 1152 MHz). This results in warnings from the cpufreq during startup. Change PLL programming (l = 54) to init CPU clocks to start with the frequency of 54 * 19.2 = 1036.8 MHz which is supported by both power and performance clusters from all speed bins. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-5-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: cpu-8996: correct PLL programmingDmitry Baryshkov
Change PLL programming to follow the downstream setup. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-4-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: clk-alpha-pll: program PLL_TEST/PLL_TEST_U if requiredDmitry Baryshkov
Program PLL_TEST and PLL_TEST_U registers if required by the pll configuration. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113120544.59320-3-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: Add QDU1000 and QRU1000 GCC supportTaniya Das
Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Made gcc_pcie_0_pipe_clk_src use clk_regmap_phy_mux_ops] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230112204446.30236-3-quic_molvera@quicinc.com
2023-01-18clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_namesDmitry Baryshkov
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "xo_board" clock instead of manually registered "xo" clock and allows us to drop qcom_cc_register_board_clk() call from the driver at some point. In the same way change the looked up system "sleep_clk_src" clock to "sleep_clk", which is registered from DT. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-12-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: mmcc-apq8084: remove spdm clocksDmitry Baryshkov
SPDM is used for debug/profiling and does not have any other functionality. These clocks can safely be removed. Suggested-by: Stephen Boyd <sboyd@kernel.org> Suggested-by: Georgi Djakov <djakov@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: mmcc-apq8084: move clock parent tables downDmitry Baryshkov
Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-10-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-9-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRCDmitry Baryshkov
Add the GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for the multimedia subsystem. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-8-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_namesDmitry Baryshkov
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "xo_board" clock instead of manually registered "xo" clock and allows us to drop qcom_cc_register_board_clk() call from the driver at some point. In the same way change the looked up system "sleep_clk_src" clock to "sleep_clk", which is registered from DT. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-7-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: gcc-apq8084: move PLL clocks upDmitry Baryshkov
Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-6-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-5-dmitry.baryshkov@linaro.org
2023-01-18clk: qcom: ipq8074: populate fw_name for usb3phy-sRobert Marko
Having only .name populated in parent_data for clocks which are only globally searchable currently will not work as the clk core won't copy that name if there is no .fw_name present as well. So, populate .fw_name for usb3phy clocks in parent_data as they were missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents"). Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data") Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230108130440.670181-1-robimarko@gmail.com
2023-01-18clk: qcom: add the GCC driver for sa8775pShazad Hussain
Add support for the Global Clock Controller found in the QTI SA8775P platforms. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> [Bartosz: made the driver ready for upstream] Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Moved to core_initcall(), per request of Konrad] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117180429.305266-3-brgl@bgdev.pl
2023-01-18clk: vc5: Add support for 5P49V60Lars-Peter Clausen
The 5P49V60 is very similar to the existing supported clock chips of the versaclock5 driver and uses the same register map layout. But its maximum VCO frequency is 2.7 GHz instead of 3 GHz for the other supported devices. Add a vco_max field to the chip info field to allow to specify a per device variant maximum VCO frequency. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230114233500.3294789-2-lars@metafoo.de Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-18clk: vc5: Use `clamp()` to restrict PLL rangeLars-Peter Clausen
The VCO frequency needs to be within a certain range and the driver enforces this. Make use of the clamp macro to implement this instead of open-coding it. This makes the code a bit shorter and also semanticly stronger. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230114233500.3294789-1-lars@metafoo.de Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-17clk: qcom: smd-rpm: msm8936: Add PMIC gated RPM_SMD_XO_*Bryan O'Donoghue
The XO crystal input is buffered through the PMIC and controlled by RPM. Create the relevant clock gate representation in the RPM clock definitions. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117024846.1367794-5-bryan.odonoghue@linaro.org
2023-01-17clk: qcom: rpmh: remove duplicate IPA clock referenceArnd Bergmann
One of the ones that were recently added was already there: drivers/clk/qcom/clk-rpmh.c:578:35: error: initialized field overwritten [-Werror=override-init] 578 | [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, Fixes: aa055bf158cd ("clk: qcom: rpmh: define IPA clocks where required") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117170217.2462320-1-arnd@kernel.org
2023-01-17soc: renesas: r9a06g032-sysctrl: Handle h2mode setting based on USBF presenceHerve Codina
The CFG_USB[H2MODE] allows to switch the USB configuration. The configuration supported are: - One host and one device or - Two hosts Set CFG_USB[H2MODE] based on the USBF controller (USB device) availability. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230105152257.310642-3-herve.codina@bootlin.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-01-16clk: qcom: Remove need for clk_ignore_unused on sc8280xpBjorn Andersson
With the transition of disabling unused clocks at sync_state, rather than late_initcall() it's now possible to drop clk_ignore_unused and unused clock disabled once client drivers have probed. Do this on SC8280XP. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # sc8280xp-lenovo-thinkpad-x13s Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113041038.4188995-1-quic_bjorande@quicinc.com
2023-01-16clk: samsung: remove s3c24xx specific pll bitsArnd Bergmann
With the s3c24xx clk driver gone, the portions of the pll driver for it can also be removed. Suggested-by: Chanwoo Choi <cwchoi00@gmail.com> Link: https://lore.kernel.org/linux-arm-kernel/0e0eff12-d8ea-72e9-d135-4259dda9a750@gmail.com/ Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-01-16clk: remove s3c24xx driverArnd Bergmann
The s3c24xx platform is gone, so the clk driver can be removed as well. Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-01-13clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rateMartin Blumenstingl
clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-cpu-dyndiv over to use .determine_rate. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20221225212632.2760126-5-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-01-13clk: meson: sclk-div: switch from .round_rate to .determine_rateMartin Blumenstingl
clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch sclk-div over to use .determine_rate. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20221225212632.2760126-4-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-01-13clk: meson: dualdiv: switch from .round_rate to .determine_rateMartin Blumenstingl
clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-dualdiv over to use .determine_rate. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20221225212632.2760126-3-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-01-13clk: meson: mpll: Switch from .round_rate to .determine_rateMartin Blumenstingl
clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-mpll over to use .determine_rate. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20221225212632.2760126-2-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-01-13cpuidle, clk: Remove trace_.*_rcuidle()Peter Zijlstra
OMAP was the one and only user. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Frederic Weisbecker <frederic@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230112195541.844982902@infradead.org
2023-01-12clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failedAlexey Khoroshilov
If cpg_mssr_common_init() fails after assigning priv to global variable cpg_mssr_priv, it deallocates priv, but cpg_mssr_priv keeps dangling pointer that potentially can be used later. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 1f7db7bbf031 ("clk: renesas: cpg-mssr: Add early clock support") Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1671806417-32623-1-git-send-email-khoroshilov@ispras.ru Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-12clk: renesas: r9a07g044: Add clock and reset entries for CRULad Prabhakar
Add CRU clock and reset entries to CPG driver. CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular sequence for the CRU block hence add these clocks to r9a07g044_no_pm_mod_clks[] array and pass it as part of CPG data for both RZ/G2L and RZ/V2L SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221221212703.348278-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2025-09-23 03:19:25 +0000