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2022-05-25Merge branch 'clk-qcom' into clk-nextStephen Boyd
* clk-qcom: Revert "clk: qcom: regmap-mux: add pipe clk implementation" Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks" Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks" clk: qcom: rcg2: Cache CFG register updates for parked RCGs clk: qcom: add sc8280xp GCC driver dt-bindings: clock: Add Qualcomm SC8280XP GCC bindings clk: qcom: gcc-msm8976: Add modem reset dt-bindings: clk: qcom: gcc-msm8976: Add modem reset clk: qcom: gcc-msm8976: Set floor ops for SDCC dt-bindings: clock: qcom,gcc-apq8064: Fix typo in compatible and split apq8084 clk: qcom: smd: Update MSM8976 RPM clocks. clk: qcom: gcc-msm8998: add SSC-related clocks dt-bindings: clock: gcc-msm8998: Add definitions of SSC-related clocks dt-bindings: clock: qcom,rpmcc: add clocks property dt-bindings: clock: qcom,rpmcc: convert to dtschema clk: qcom: lpass: Add support for LPASS clock controller for SC7280 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks clk: qcom: regmap-mux: add pipe clk implementation
2022-05-25Merge branches 'clk-rockchip', 'clk-ingenic', 'clk-bindings', 'clk-samsung' ↵Stephen Boyd
and 'clk-stm' into clk-next - Mark some clks critical on Ingenic X1000 - Add STM32MP13 RCC driver (Reset Clock Controller) * clk-rockchip: dt-bindings: clock: convert rockchip,rk3368-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3228-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3036-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3308-cru.txt to YAML dt-bindings: clock: convert rockchip,px30-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3188-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3288-cru.txt to YAML dt-bindings: clock: convert rockchip,rv1108-cru.txt to YAML dt-binding: clock: Add missing rk3568 cru bindings clk: rockchip: Mark hclk_vo as critical on rk3568 dt-bindings: clock: fix rk3399 cru clock issues dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml dt-bindings: clock: replace a maintainer for rockchip,rk3399-cru.yaml dt-bindings: clock: fix some conversion style issues for rockchip,rk3399-cru.yaml * clk-ingenic: clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCs mips: ingenic: Do not manually reference the CPU clock clk: ingenic: Mark critical clocks in Ingenic SoCs clk: ingenic: Allow specifying common clock flags * clk-bindings: dt-bindings: clock: Replace common binding with link to schema * clk-samsung: dt-bindings: clock: exynosautov9: correct count of NR_CLK clk: samsung: exynosautov9: add cmu_peric1 clock support clk: samsung: exynosautov9: add cmu_peric0 clock support clk: samsung: exynosautov9: add cmu_fsys2 clock support clk: samsung: exynosautov9: add cmu_busmc clock support clk: samsung: exynosautov9: add cmu_peris clock support clk: samsung: exynosautov9: add cmu_core clock support clk: samsung: add top clock support for Exynos Auto v9 SoC dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings dt-bindings: clock: add clock binding definitions for Exynos Auto v9 * clk-stm: clk: stm32mp13: add safe mux management clk: stm32mp13: add multi mux function clk: stm32mp13: add all STM32MP13 kernel clocks clk: stm32mp13: add all STM32MP13 peripheral clocks clk: stm32mp13: manage secured clocks clk: stm32mp13: add composite clock clk: stm32mp13: add stm32 divider clock clk: stm32mp13: add stm32_gate management clk: stm32mp13: add stm32_mux clock management clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller) dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
2022-05-25Merge branches 'clk-ux500', 'clk-mtk', 'clk-tegra', 'clk-allwinner' and ↵Stephen Boyd
'clk-imx' into clk-next - Convert ux500 to clk_hw - Add the two missing CLKOUT clocks for U8500/DB8500 SoC - MediaTek MT8186 SoC clk support - Move MediaTek driver to clk_hw provider APIs * clk-ux500: clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base() clk: ux500: Implement the missing CLKOUT clocks clk: ux500: Rewrite PRCMU clocks to use clk_hw_* clk: ux500: Drop .is_prepared state from PRCMU clocks clk: ux500: Drop .is_enabled state from PRCMU clocks dt-bindings: clock: u8500: Add clkout clock bindings * clk-mtk: (22 commits) clk: mediatek: mt8173: Switch to clk_hw provider APIs clk: mediatek: Switch to clk_hw provider APIs clk: mediatek: Replace 'struct clk' with 'struct clk_hw' clk: mediatek: apmixed: Drop error message from clk_register() failure clk: mediatek: Make mtk_clk_register_composite() static clk: mediatek: use en_mask as a pure div_en_mask clk: mediatek: update compatible string for MT7986 ethsys clk: mediatek: Add MT8186 ipesys clock support clk: mediatek: Add MT8186 mdpsys clock support clk: mediatek: Add MT8186 camsys clock support clk: mediatek: Add MT8186 vencsys clock support clk: mediatek: Add MT8186 vdecsys clock support clk: mediatek: Add MT8186 imgsys clock support clk: mediatek: Add MT8186 wpesys clock support clk: mediatek: Add MT8186 mmsys clock support clk: mediatek: Add MT8186 mfgsys clock support clk: mediatek: Add MT8186 imp i2c wrapper clock support clk: mediatek: Add MT8186 apmixedsys clock support clk: mediatek: Add MT8186 infrastructure clock support clk: mediatek: Add MT8186 topckgen clock support ... * clk-tegra: clk: tegra: Update kerneldoc to match prototypes clk: tegra: Replace .round_rate() with .determine_rate() clk: tegra: Register clocks from root to leaf clk: tegra: Add missing reset deassertion * clk-allwinner: clk: sunxi-ng: h616: Add PLL derived 32KHz clock clk: sunxi-ng: h6-r: Add RTC gate clock * clk-imx: clk: imx8mp: fix usb_root_clk parent clk: imx8mp: add clkout1/2 support clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage clk: imx8mp: Add DISP2 pixel clock clk: imx: scu: fix a potential memory leak in __imx_clk_gpr_scu() clk: imx: Add check for kcalloc clk: imx8mn: add GPT support dt-bindings: imx: add clock bindings for i.MX8MN GPT clk: imx: Remove the snvs clock clk: imx8m: check mcore_booted before register clk clk: imx: add mcore_booted module paratemter clk: imx8mq: add 27m phy pll ref clock
2022-05-25Merge branches 'clk-ti', 'clk-cleanup', 'clk-airoha', 'clk-i2c-simple' and ↵Stephen Boyd
'clk-renesas' into clk-next - Airoha EN7523 SoC system clocks - Use i2c driver probe_new to avoid id scans * clk-ti: clk: ti: clkctrl: replace usage of found with dedicated list iterator variable clk: ti: composite: Prefer kcalloc over open coded arithmetic clk: keystone: syscon-clk: Add support for AM62 epwm-tbclk dt-bindings: clock: ehrpwm: Add AM62 specific compatible * clk-cleanup: clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc() clk: fixed-rate: Remove redundant if statement clk: mux: remove redundant initialization of variable width clk: using pm_runtime_resume_and_get instead of pm_runtime_get_sync clk: actions: remove redundant assignment after a mask operation * clk-airoha: clk: en7523: fix wrong pointer check in en7523_clk_probe() clk: en7523: Add clock driver for Airoha EN7523 SoC dt-bindings: Add en7523-scu device tree binding documentation * clk-i2c-simple: clk: renesas-pcie: use simple i2c probe function clk: si570: use i2c_match_id and simple i2c probe clk: si544: use i2c_match_id and simple i2c probe clk: si5351: use i2c_match_id and simple i2c probe clk: si5341: use simple i2c probe function clk: si514: use simple i2c probe function clk: max9485: use simple i2c probe function clk: cs2000-cp: use simple i2c probe function clk: cdce925: use i2c_match_id and simple i2c probe clk: cdce706: use simple i2c probe function * clk-renesas: (48 commits) clk: renesas: r9a09g011: Add eth clock and reset entries clk: renesas: Add RZ/V2M support using the rzg2l driver clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg clk: renesas: rzg2l: Make use of CLK_MON registers optional clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers clk: renesas: rzg2l: Add read only versions of the clk macros clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC clk: renesas: r9a07g044: Fix OSTM1 module clock name clk: renesas: r9a07g043: Add clock and reset entries for ADC clk: renesas: r9a07g043: Add TSU clock and reset entry clk: renesas: r9a07g043: Add RSPI clock and reset entries clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller clk: renesas: r9a07g044: Add DSI clock and reset entries clk: renesas: r9a07g044: Add LCDC clock and reset entries clk: renesas: r9a07g044: Add M4 Clock support clk: renesas: r9a07g044: Add M3 Clock support clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support clk: renesas: r9a07g044: Add M1 clock support clk: renesas: rzg2l: Add DSI divider clk support ...
2022-05-23Revert "clk: qcom: regmap-mux: add pipe clk implementation"Dmitry Baryshkov
Johan Hovold has pointed out that there are several deficiencies and a race condition in the regmap_mux_safe ops that were merged. Pipe clocks has been updated to use newer and simpler clk_regmap_phy_mux_ops. Drop the regmap-mux-safe clock ops now. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220521005343.1429642-4-dmitry.baryshkov@linaro.org
2022-05-23Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe ↵Dmitry Baryshkov
clocks" Johan Hovold has pointed out that there are several deficiencies and a race condition in the regmap_mux_safe ops that were merged. Revert the commit that switches gcc-sc7280 driver to use regmap_mux_safe. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220521005343.1429642-3-dmitry.baryshkov@linaro.org
2022-05-23Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe ↵Dmitry Baryshkov
clocks" Johan Hovold has pointed out that there are several deficiencies and a race condition in the regmap_mux_safe ops that were merged. Revert the commit that switches gcc-sm8450 driver to use regmap_mux_safe. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220521005343.1429642-2-dmitry.baryshkov@linaro.org
2022-05-20clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc()Christophe JAILLET
We should have 'n', then 'size', not the opposite. This is harmless because the 2 values are just multiplied, but having the correct order silence a (unpublished yet) smatch warning. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/49d726d11964ca0e3757bdb5659e3b3eaa1572b5.1653081643.git.christophe.jaillet@wanadoo.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: stm32mp13: add safe mux managementGabriel Fernandez
Some muxes need to set a the safe position when clock is off. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-12-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: stm32mp13: add multi mux functionGabriel Fernandez
Some RCC muxes can manages two output clocks with same register. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-11-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: stm32mp13: add all STM32MP13 kernel clocksGabriel Fernandez
Complete all kernel clocks of stm32mp13. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-10-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: stm32mp13: add all STM32MP13 peripheral clocksGabriel Fernandez
All peripheral clocks are mainly based on stm32_gate clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-9-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: stm32mp13: manage secured clocksGabriel Fernandez
Don't register a clock if this clock is secured. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-8-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: stm32mp13: add composite clockGabriel Fernandez
Just to introduce management of stm32 composite clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-7-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: stm32mp13: add stm32 divider clockGabriel Fernandez
Just to introduce management of a stm32 divider clock Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-6-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: stm32mp13: add stm32_gate managementGabriel Fernandez
Just to introduce management of a stm32 gate clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-5-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: stm32mp13: add stm32_mux clock managementGabriel Fernandez
Just to introduce management of a stm32 mux clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-4-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)Gabriel Fernandez
This driver manages Reset and Clock of STM32MP13 soc. It uses a clk-stm32-core module to manage stm32 gate, mux and divider for STM32MP13 and for new future soc. All gates, muxes, dividers are identify by an index and information are stored in array (register address, shift, with, flags...) This is useful when we have two clocks with the same gate or when one mux manages two output clocks. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-3-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: ti: clkctrl: replace usage of found with dedicated list iterator variableJakob Koschel
To move the list iterator variable into the list_for_each_entry_*() macro in the future it should be avoided to use the list iterator variable after the loop body. To *never* use the list iterator variable after the loop it was concluded to use a separate iterator variable instead of a found boolean [1]. This removes the need to use a found variable and simply checking if the variable was set, can determine if the break/goto was hit. Link: https://lore.kernel.org/all/CAHk-=wgRr_D8CB-D9Kg-c=EHreAsk5SqXPwr9Y7k9sA6cWXJ6w@mail.gmail.com/ Signed-off-by: Jakob Koschel <jakobkoschel@gmail.com> Link: https://lore.kernel.org/r/20220324071019.59483-1-jakobkoschel@gmail.com Tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-20clk: ti: composite: Prefer kcalloc over open coded arithmeticLen Baker
As noted in the "Deprecated Interfaces, Language Features, Attributes, and Conventions" documentation [1], size calculations (especially multiplication) should not be performed in memory allocator (or similar) function arguments due to the risk of them overflowing. This could lead to values wrapping around and a smaller allocation being made than the caller was expecting. Using those allocations could lead to linear overflows of heap memory and other misbehaviors. So, use the purpose specific kcalloc() function instead of the argument size * count in the kzalloc() function. [1] https://www.kernel.org/doc/html/v5.14/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments Signed-off-by: Len Baker <len.baker@gmx.com> Link: https://lore.kernel.org/r/20210904131714.2312-1-len.baker@gmx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-19clk: mediatek: mt8173: Switch to clk_hw provider APIsChen-Yu Tsai
As part of the effort to improve the MediaTek clk drivers, the next step is to switch from the old 'struct clk' clk prodivder APIs to the new 'struct clk_hw' ones. The MT8173 clk driver has one clk that is registered directly with the clk provider APIs, instead of going through the MediaTek clk library. Switch this instance to use the clk_hw provider API. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-6-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-19clk: mediatek: Switch to clk_hw provider APIsChen-Yu Tsai
As part of the effort to improve the MediaTek clk drivers, the next step is to switch from the old 'struct clk' clk prodivder APIs to the new 'struct clk_hw' ones. In a previous patch, 'struct clk_onecell_data' was replaced with 'struct clk_hw_onecell_data', with (struct clk_hw *)->clk and __clk_get_hw() bridging the new data structures and old code. Now switch from the old 'clk_(un)?register*()' APIs to the new 'clk_hw_(un)?register*()' ones. This is done with the coccinelle script below. Unfortunately this also leaves clk-mt8173.c with a compile error that would need a coccinelle script longer than the actual diff to fix. This last part is fixed up by hand. // Fix prototypes @@ identifier F =~ "^mtk_clk_register_"; @@ - struct clk * + struct clk_hw * F(...); // Fix calls to mtk_clk_register_<singular> @ reg @ identifier F =~ "^mtk_clk_register_"; identifier FS =~ "^mtk_clk_register_[a-z_]*s"; identifier I; expression clk_data; expression E; @@ FS(...) { ... - struct clk *I; + struct clk_hw *hw; ... for (...;...;...) { ... ( - I + hw = - clk_register_fixed_rate( + clk_hw_register_fixed_rate( ... ); | - I + hw = - clk_register_fixed_factor( + clk_hw_register_fixed_factor( ... ); | - I + hw = - clk_register_divider( + clk_hw_register_divider( ... ); | - I + hw = F(...); ) ... if ( - IS_ERR(I) + IS_ERR(hw) ) { pr_err(..., - I + hw ,...); ... } - clk_data->hws[E] = __clk_get_hw(I); + clk_data->hws[E] = hw; } ... } @ depends on reg @ identifier reg.I; @@ return PTR_ERR( - I + hw ); // Fix mtk_clk_register_composite to return clk_hw instead of clk @@ identifier I, R; expression E; @@ - struct clk * + struct clk_hw * mtk_clk_register_composite(...) { ... - struct clk *I; + struct clk_hw *hw; ... - I = clk_register_composite( + hw = clk_hw_register_composite( ...); if (IS_ERR( - I + hw )) { ... R = PTR_ERR( - I + hw ); ... } return - I + hw ; ... } // Fix other mtk_clk_register_<singular> to return clk_hw instead of clk @@ identifier F =~ "^mtk_clk_register_"; identifier I, D, C; expression E; @@ - struct clk * + struct clk_hw * F(...) { ... - struct clk *I; + int ret; ... - I = clk_register(D, E); + ret = clk_hw_register(D, E); ... ( - if (IS_ERR(I)) + if (ret) { kfree(C); + return ERR_PTR(ret); + } | - if (IS_ERR(I)) + if (ret) { kfree(C); - return I; + return ERR_PTR(ret); } ) - return I; + return E; } // Fix mtk_clk_unregister_<singular> to take clk_hw instead of clk @@ identifier F =~ "^mtk_clk_unregister_"; identifier I, I2; @@ static void F( - struct clk *I + struct clk_hw *I2 ) { ... - struct clk_hw *I2; ... - I2 = __clk_get_hw(I); ... ( - clk_unregister(I); + clk_hw_unregister(I2); | - clk_unregister_composite(I); + clk_hw_unregister_composite(I2); ) ... } // Fix calls to mtk_clk_unregister_*() @@ identifier F =~ "^mtk_clk_unregister_"; expression I; expression E; @@ - F(I->hws[E]->clk); + F(I->hws[E]); Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-5-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-19clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai
As part of the effort to improve the MediaTek clk drivers, the next step is to switch from the old 'struct clk' clk prodivder APIs to the new 'struct clk_hw' ones. Instead of adding new APIs to the MediaTek clk driver library mirroring the existing ones, moving all drivers to the new APIs, and then removing the old ones, just migrate everything at the same time. This involves replacing 'struct clk' with 'struct clk_hw', and 'struct clk_onecell_data' with 'struct clk_hw_onecell_data', and fixing up all usages. For now, the clk_register() and co. usage is retained, with __clk_get_hw() and (struct clk_hw *)->clk used to bridge the difference between the APIs. These will be replaced in subsequent patches. Fix up mtk_{alloc,free}_clk_data to use 'struct clk_hw' by hand. Fix up all other affected call sites with the following coccinelle script. // Replace type @@ @@ - struct clk_onecell_data + struct clk_hw_onecell_data // Replace of_clk_add_provider() & of_clk_src_simple_get() @@ expression NP, DATA; symbol of_clk_src_onecell_get; @@ - of_clk_add_provider( + of_clk_add_hw_provider( NP, - of_clk_src_onecell_get, + of_clk_hw_onecell_get, DATA ) // Fix register/unregister @@ identifier CD; expression E; identifier fn =~ "unregister"; @@ fn(..., - CD->clks[E] + CD->hws[E]->clk ,... ); // Fix calls to clk_prepare_enable() @@ identifier CD; expression E; @@ clk_prepare_enable( - CD->clks[E] + CD->hws[E]->clk ); // Fix pointer assignment @@ identifier CD; identifier CLK; expression E; @@ - CD->clks[E] + CD->hws[E] = ( - CLK + __clk_get_hw(CLK) | ERR_PTR(...) ) ; // Fix pointer usage @@ identifier CD; expression E; @@ - CD->clks[E] + CD->hws[E] // Fix mtk_clk_pll_get_base() @@ symbol clk, hw, data; @@ mtk_clk_pll_get_base( - struct clk *clk, + struct clk_hw *hw, const struct mtk_pll_data *data ) { - struct clk_hw *hw = __clk_get_hw(clk); ... } // Fix mtk_clk_pll_get_base() usage @@ identifier CD; expression E; @@ mtk_clk_pll_get_base( - CD->clks[E] + CD->hws[E]->clk ,... ); Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-4-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-19clk: mediatek: apmixed: Drop error message from clk_register() failureChen-Yu Tsai
mtk_clk_register_ref2usb_tx() prints an error message if clk_register() fails. It doesn't if kzalloc() fails though. The caller would then tack on its own error message to handle this. Also, All other clk registration functions in the MediaTek clk library leave the error message printing to the bulk registration functions, while the helpers that register individual clks just return error codes. Drop the error message that is printed when clk_register() fails in mtk_clk_register_ref2usb_tx() to make its behavior consistent both across its failure modes, and with the rest of the driver library. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-3-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-19clk: mediatek: Make mtk_clk_register_composite() staticChen-Yu Tsai
mtk_clk_register_composite() is not used anywhere outside of the file it is defined. Make it static. Fixes: 9741b1a68035 ("clk: mediatek: Add initial common clock support for Mediatek SoCs.") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-2-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-19clk: qcom: rcg2: Cache CFG register updates for parked RCGsBjorn Andersson
As GDSCs are turned on and off some associated clocks are momentarily enabled for house keeping purposes. For this, and similar, purposes the "shared RCGs" will park the RCG on a source clock which is known to be available. When the RCG is parked, a safe clock source will be selected and committed, then the original source would be written back and upon enable the change back to the unparked source would be committed. But starting with SM8350 this fails, as the value in CFG is committed by the GDSC handshake and without a ticking parent the GDSC enablement will time out. This becomes a concrete problem if the runtime supended state of a device includes disabling such rcg's parent clock. As the device attempts to power up the domain again the rcg will fail to enable and hence the GDSC enablement will fail, preventing the device from returning from the suspended state. This can be seen in e.g. the display stack during probe on SM8350. To avoid this problem, the software needs to ensure that the RCG is configured to a active parent clock while it is disabled. This is done by caching the CFG register content while the shared RCG is parked on this safe source. Writes to M, N and D registers are committed as they are requested. New helpers for get_parent() and recalc_rate() are extracted from their previous implementations and __clk_rcg2_configure() is modified to allow it to operate on the cached value. Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220426212136.1543984-1-bjorn.andersson@linaro.org
2022-05-19clk: qcom: add sc8280xp GCC driverBjorn Andersson
Add support for the Global Clock Controller found in the Qualcomm SC8280XP platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220505025457.1693716-3-bjorn.andersson@linaro.org
2022-05-19clk: renesas: r9a06g032: Probe possible childrenMiquel Raynal
The clock controller device on r9a06g032 takes all the memory range that is described as being a system controller. This range contains many different (unrelated?) registers besides the ones belonging to the clock controller, that can necessitate to be accessed from other peripherals. For instance, the dmamux registers are there. The dmamux "device" will be described as a child node of the clock/system controller node, which means we need the top device driver (the clock controller driver in this case) to populate its children manually. In case of error when populating the children, we do not fail the probe on purpose to keep the clk driver up and running. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220427095653.91804-7-miquel.raynal@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-05-19clk: renesas: r9a06g032: Export function to set dmamuxMiquel Raynal
The dmamux register is located within the system controller. Without syscon, we need an extra helper in order to give write access to this register to a dmamux driver. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220427095653.91804-5-miquel.raynal@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-05-18clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen
We no longer allow en_mask to be a combination of pll_en_bit and div_en_mask, so remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask that only used for pll dividers. This commit continues the work done in commit 7cc4e1bbe300 ("clk: mediatek: Fix asymmetrical PLL enable and disable control") and commit f384c44754b7 ("clk: mediatek: Add configurable enable control to mtk_pll_data") to clean up en_mask(bit0) default setting. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com> Link: https://lore.kernel.org/r/20220513073621.12923-1-mandyjh.liu@mediatek.com Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-18clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCsAidan MacDonald
The TCU clock gate on X1000 wasn't requested by the driver and could be gated automatically later on in boot, which prevents timers from running and breaks PWM. Add a workaround to support old device trees that don't specify the "tcu" clock gate. In this case the kernel will print a warning and attempt to continue without the clock, which is wrong, but it could work if "clk_ignore_unused" is in the kernel arguments. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220412122750.279058-3-aidanmacdonald.0x0@gmail.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-18clk: mediatek: update compatible string for MT7986 ethsysSam Shih
Update compatible string of mt7986 ethsys clock driver to fit the devicetree bindings document. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Link: https://lore.kernel.org/r/20220509090939.845-2-sam.shih@mediatek.com Fixes: ec97d23c8e22 ("clk: mediatek: add mt7986 clock support") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-18clk: ingenic: Mark critical clocks in Ingenic SoCsAidan MacDonald
Consider CPU, L2 cache, and memory clocks as critical to prevent them -- and the parent clocks -- from being automatically gated, since nothing calls clk_get() on these clocks. Gating the CPU clock hangs the processor, and gating memory makes external DRAM inaccessible. Normal kernel code can't hope to deal with either situation so those clocks have to be critical. The L2 cache is required only if caches are running, and could be gated if the kernel takes care to flush and disable caches before gating the clock. There's no mechanism to do this, and probably no reason to do it, so it's simpler to mark the L2 cache as critical. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220428164454.17908-3-aidanmacdonald.0x0@gmail.com Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-18clk: ingenic: Allow specifying common clock flagsAidan MacDonald
Provide a flags field for clocks under the ingenic-cgu driver, which can be used to set generic common clock framework flags on the created clocks. For example, the CLK_IS_CRITICAL flag is needed for some clocks (such as CPU or memory) to stop them being automatically disabled. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220428164454.17908-2-aidanmacdonald.0x0@gmail.com Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-18clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base()Hangyu Hua
Off-by-one will happen when index == ARRAY_SIZE(ur->base). Fixes: b14cbdfd467d ("clk: ux500: Add driver for the reset portions of PRCC") Signed-off-by: Hangyu Hua <hbh25y@gmail.com> Link: https://lore.kernel.org/r/20220518062537.17933-1-hbh25y@gmail.com Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-17clk: at91: generated: consider range when calculating best rateCodrin Ciubotariu
clk_generated_best_diff() helps in finding the parent and the divisor to compute a rate closest to the required one. However, it doesn't take into account the request's range for the new rate. Make sure the new rate is within the required range. Fixes: 8a8f4bf0c480 ("clk: at91: clk-generated: create function to find best_diff") Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20220413071318.244912-1-codrin.ciubotariu@microchip.com Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-17clk: imx8mp: fix usb_root_clk parentPeng Fan
According to reference mannual CCGR77(usb) sources from hsio_axi, fix it. Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220507125430.793287-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-05-17Revert "clk: sunxi-ng: sun6i-rtc: Add support for H6"Jernej Skrabec
This reverts commit 1738890a3165ccd0da98ebd3e2d5f9b230d5afa8. Commit 1738890a3165 ("clk: sunxi-ng: sun6i-rtc: Add support for H6") breaks HDMI output on Tanix TX6 mini board. Exact reason isn't known, but because that commit doesn't actually improve anything, let's just revert it. Cc: stable@vger.kernel.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220511200206.2458274-1-jernej.skrabec@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-17clk: bcm2835: fix bcm2835_clock_choose_divStefan Wahren
The commit 09e3b18ca5de ("clk: bcm2835: Remove unused variable") accidentially breaks the behavior of bcm2835_clock_choose_div() and booting of Raspberry Pi. The removed do_div macro call had side effects, so we need to restore it. Fixes: 09e3b18ca5de ("clk: bcm2835: Remove unused variable") Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Link: https://lore.kernel.org/r/20220428183010.1635248-1-stefan.wahren@i2se.com Tested-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-16clk: fixed-rate: Remove redundant if statementLi Zhengyu
(np) is always true when (dev || !np) is false, so just remove the check. Signed-off-by: Li Zhengyu <lizhengyu3@huawei.com> Link: https://lore.kernel.org/r/20220509092102.140520-1-lizhengyu3@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-10clk: samsung: exynosautov9: add cmu_peric1 clock supportChanho Park
Like CMU_PERIC0, this provides clocks for USI06 ~ USI11 and USI_I2C. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-10-chanho61.park@samsung.com
2022-05-10clk: samsung: exynosautov9: add cmu_peric0 clock supportChanho Park
CMU_PERIC0 provides clocks for USI0 ~ USI5 and USIx_I2C. USI0/1/2/3/4/5 have its own divider but USI_I2Cs share "dout_peric0_usi_i2c" divider. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220504075154.58819-9-chanho61.park@samsung.com
2022-05-10clk: samsung: exynosautov9: add cmu_fsys2 clock supportChanho Park
CMU_FSYS2 is responsible to control clocks of BLK_FSYS2 which includes ufs and ethernet IPs. This patch adds some essential clocks to be controlled by ethernet/ufs drivers instead of listing full clocks. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-8-chanho61.park@samsung.com
2022-05-10clk: samsung: exynosautov9: add cmu_busmc clock supportChanho Park
CMU_BUSMC is responsible to control clocks of BLK_BUSMC which represents Data/Peri buses. Most clocks except PDMA/SPDMA are not necessary to be controlled by HLOS. So, this adds PDMA/SPDMA gate clocks. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-7-chanho61.park@samsung.com
2022-05-10clk: samsung: exynosautov9: add cmu_peris clock supportChanho Park
CMU_PERIS is responsible to control clocks of BLK_PERIS which has OPT/MCT/WDT and TMU. This patch only supports WDT gate clocks and all other clocks except WDT will be supported later. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-6-chanho61.park@samsung.com
2022-05-10clk: samsung: exynosautov9: add cmu_core clock supportChanho Park
Add CMU_CORE clock which represents Core BUS clocks. The source clocks of this CMU block are oscclk or dout_clkcmu_core_bus. Thus, two source clocks should be provided via device tree. All the gate clocks are defined as CLK_IS_CRITICAL because they control(gate/ungate) core bus clocks but not been assigned to any drivers. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-5-chanho61.park@samsung.com
2022-05-10clk: samsung: add top clock support for Exynos Auto v9 SoCChanho Park
This adds support for CMU_TOP which generates clocks for all the function blocks such as CORE, FSYS0/1/2, PERIC0/1 and so on. For CMU_TOP, PLL_SHARED0,1,2,3 and 4 will be the sources of this block and they will generate bus clocks. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-4-chanho61.park@samsung.com
2022-05-07ARM: pxa: move clk register definitions to driverArnd Bergmann
The clock register definitions are now used (almost) exclusively in the clk driver, and that relies on no other mach/*.h header files any more. Remove the dependency on mach/pxa*-regs.h by addressing the registers as offsets from a void __iomem * pointer, which is either passed from a board file, or (for the moment) ioremapped at boot time from a hardcoded address in case of DT (this should be moved into the DT of course). Cc: linux-clk@vger.kernel.org Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-07ARM: pxa: move smemc register access from clk to platformArnd Bergmann
The get_sdram_rows() and get_memclkdiv() helpers need smemc register that are separate from the clk registers, move them out of the clk driver, and use an extern declaration instead. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/lkml/87pnielzo4.fsf@belgarion.home/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-07cpufreq: pxa3: move clk register access to clk driverArnd Bergmann
The driver needs some low-level register access for setting the core and bus frequencies. These registers are owned by the clk driver, so move the low-level access into that driver with a slightly higher-level interface and avoid any machine header file dependencies. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: linux-clk@vger.kernel.org Cc: linux-pm@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit (git 2.34.1) at 2025-09-18 00:15:55 +0000