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path: root/drivers/clk
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2019-11-11clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko
A proper External Memory Controller clock rounding and parent selection functionality is required by the EMC drivers, it is not available using the generic clock implementation because only the Memory Controller driver is aware of what clock rates are actually available for a particular device. EMC drivers will have to register a Tegra-specific CLK-API callback which will perform rounding of a requested rate. EMC clock users won't be able to request EMC clock by getting -EPROBE_DEFER until EMC driver is probed and the callback is set up. The functionality is somewhat similar to the clk-emc.c which serves Tegra124+ SoCs. The later HW generations support more parent clock sources and the HW configuration / integration with the EMC drivers differs a tad from the older gens, hence it's not really worth to try to squash everything into a single source file. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: Add API to get index of the clock parentSowjanya Komatineni
This patch adds a new clk_hw_get_parent_index() function that can be used to retrieve the index of a given clock's parent. This can be useful for restoring a clock on system resume. Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-08clk: clk-gpio: propagate rate change to parentMichael Hennerich
For an external clock source, which is gated via a GPIO, the rate change should typically be propagated to the parent clock. The situation where we are requiring this propagation, is when an external clock is connected to override an internal clock (which typically has a fixed rate). The external clock can have a different rate than the internal one, and may also be variable, thus requiring the rate propagation. This rate change wasn't propagated until now, and it's unclear about cases where this shouldn't be propagated. Thus, it's unclear whether this is fixing a bug, or extending the current driver behavior. Also, it's unsure about whether this may break any existing setups; in the case that it does, a device-tree property may be added to disable this flag. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lkml.kernel.org/r/20191108071718.17985-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-08clk: qcom: rpmh: Reuse sdm845 clks for sm8150Stephen Boyd
The SM8150 list of clks is almost the same as the list for SDM845, except there isn't an IPA clk. Just point to the SDM845 clks from the SM8150 list for now so we can reduce the amount of struct bloat in this driver. Suggested-by: Vinod Koul <vkoul@kernel.org> Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20191107214018.184105-1-sboyd@kernel.org Reviewed-by: Vinod Koul <vkoul@kernel.org>
2019-11-08clk/ti/adpll: allocate room for terminating nullStephen Kitt
The buffer allocated in ti_adpll_clk_get_name doesn't account for the terminating null. This patch switches to devm_kasprintf to avoid overflowing. Signed-off-by: Stephen Kitt <steve@sk2.org> Link: https://lkml.kernel.org/r/20191019140634.15596-1-steve@sk2.org Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-08clk: ast2600: Add RMII RCLK gates for all four MACsAndrew Jeffery
RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a single gate for each MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lkml.kernel.org/r/20191010020725.3990-3-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-08drivers/clk: convert VL struct to struct_sizeStephen Kitt
There are a few manually-calculated variable-length struct allocations left, this converts them to use struct_size. Found with the following git grep command git grep -A1 'kzalloc.*sizeof[^_].*+' Signed-off-by: Stephen Kitt <steve@sk2.org> Link: https://lkml.kernel.org/r/20190927185110.29897-1-steve@sk2.org Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com> [sboyd@kernel.org: Add grep command] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-08Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "Fixes for various clk driver issues that happened because of code we merged this merge window. The Amlogic driver was missing some flags causing rates to be rounded improperly or clk_set_rate() to fail. The Samsung driver wasn't freeing everything on error paths and improperly saving/restoring PLL state across suspend/resume. The at91 driver was calling msleep() too early when scheduling hadn't started, so we put in place a quick solution until we can handle this sort of problem in the core framework. There were also problems with the Allwinner driver and operator precedence being incorrect causing subtle bugs. Finally, the TI driver was duplicating aliases and not delaying long enough leading to some unexpected timeouts" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: ti: clkctrl: Fix failed to enable error with double udelay timeout clk: ti: dra7-atl-clock: Remove ti_clk_add_alias call clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18 clk: sunxi: Fix operator precedence in sunxi_divs_clk_setup clk: ast2600: Fix enabling of clocks clk: at91: avoid sleeping early clk: imx8m: Use SYS_PLL1_800M as intermediate parent of CLK_ARM clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU clk: samsung: exynos5433: Fix error paths clk: at91: sam9x60: fix programmable clock clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes clk: meson: g12a: fix cpu clock rate setting clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
2019-11-07clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driverJeffrey Hugo
The GPUCC manages the clocks for the Adreno GPU found on MSM8998. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191031185733.15553-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Allow constant ratio freq tables for rcgJeffrey Hugo
Some RCGs (the gfx_3d_src_clk in msm8998 for example) are basically just some constant ratio from the input across the entire frequency range. It would be great if we could specify the frequency table as a single entry constant ratio instead of a long list, ie: { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }, { } So, lets support that. We need to fix a corner case in qcom_find_freq() where if the freq table is non-null, but has no frequencies, we end up returning an "entry" before the table array, which is bad. Then, we need ignore the freq from the table, and instead base everything on the requested freq. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191031185715.15504-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: smd: Add missing pnoc clockJeffrey Hugo
When MSM8998 support was added, and analysis was done to determine what clocks would be consumed. That analysis had a flaw, which caused the pnoc to be skipped. The pnoc clock needs to be on to access the uart for the console. The clock is on from boot, but has no consumer votes in the RPM. When we attempt to boot the modem, it causes the RPM to turn off pnoc, which kills our access to the console and causes CPU hangs. We need pnoc to be defined, so that clk_smd_rpm_handoff() will put in an implicit vote for linux and prevent issues when booting modem. Hopefully pnoc can be consumed by the interconnect framework in future so that Linux can rely on explicit votes. Fixes: 6131dc81211c ("clk: qcom: smd: Add support for MSM8998 rpm clocks") Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191107190615.5656-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Enumerate clocks and reset needed to boot the 8998 modemJeffrey Hugo
We need to control five additional clocks and a reset inorder to boot the modem on msm8998. If we can boot the modem, we have a place to run the wlan firmware and get wifi up and running. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191107192136.5880-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: clk-rpmh: Add support for RPMHCC for SC7180Taniya Das
Add support for clock RPMh driver to vote for ARC and VRM managed clock resources. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1572371299-16774-4-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Add Global Clock controller (GCC) driver for SC7180Taniya Das
Add support for the global clock controller found on SC7180 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20191014102308.27441-6-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: common: Return NULL from clk_hw OF providerTaniya Das
Return NULL in the cases where the clk_hw is not registered with the clock provider, but the clock consumer still requests for a clock id. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20191014102308.27441-3-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: rcg: update the DFS macro for RCGTaniya Das
Update the init data name for each of the dynamic frequency switch controlled clock associated with the RCG clock name, so that it can be generated as per the hardware plan. Thus update the macro accordingly. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20191014102308.27441-2-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: remove unneeded semicolonYueHaibing
remove unneeded semicolon. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191025093332.27592-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Add Q6SSTOP clock controller for QCS404Govind Singh
Add support for the Q6SSTOP clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required WCSS Q6SSTOP clock/reset controls to bring the subsystem out of reset and shutdown the WCSS Q6DSP. Signed-off-by: Govind Singh <govinds@codeaurora.org> Link: https://lkml.kernel.org/r/20191011132928.9388-3-govinds@codeaurora.org [sboyd@kernel.org: Sort makefile] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Initialize clock drivers earlierAmit Kucheria
Initialize the clock drivers on sdm845 and qcs404 in core_initcall so we can have earlier access to cpufreq during booting. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/75ae9c3a1c0e69b95818c6ffe7181fdeaaf2d70e.1571656015.git.amit.kucheria@linaro.org
2019-11-05clk: rockchip: protect the pclk_usb_grf as critical on px30Heiko Stuebner
Make this clock a real critical clock, so that writes to the usbphy grf always succeed. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20190917081903.25139-5-heiko@sntech.de
2019-11-05clk: rockchip: add video-related niu clocks as critical on px30Heiko Stuebner
Video-In and -Out interconnect clocks need to stay on all the time for the peripheral to work and we do not model the actual interconnect at this point. So mark them as critical for now. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20190917081903.25139-4-heiko@sntech.de
2019-11-05clk: rockchip: move px30 critical clocks to correct clock controllerHeiko Stuebner
The clocks in the px30 critical clock section are from the regular cru not the pmucru, so move them to the correct place. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20190917081903.25139-3-heiko@sntech.de
2019-11-05clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandcFinley Xiao
Some IPs, such as NAND, EMMC, SDIO and SDMMC need clock of 50% duty cycle, divfree50 can generate clock of 50% duty cycle even in odd value divisor. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20190917081903.25139-2-heiko@sntech.de
2019-11-05clk: sunxi-ng: h3: Export MBUS clockJernej Skrabec
MBUS clock will be referenced in MBUS controller node. Export it. Acked-by: Maxime Ripard <mripard@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-11-04Merge tag 'clk-v5.4-samsung-fixes' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-fixes Pull Samsung clk driver fixes from Sylwester Nawrocki: - system suspend related fixes for the exynos542x clocks driver - probe() error paths fixes in the exynos5433 CMU driver adding proper release of memory and clk resources * tag 'clk-v5.4-samsung-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU clk: samsung: exynos5433: Fix error paths
2019-11-04Merge tag 'sunxi-clk-fixes-for-5.4-1' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Two patches that fix some operator precedence and zeroing of bits * tag 'sunxi-clk-fixes-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18 clk: sunxi: Fix operator precedence in sunxi_divs_clk_setup
2019-11-04clk: ti: clkctrl: Fix failed to enable error with double udelay timeoutTony Lindgren
Commit 3d8598fb9c5a ("clk: ti: clkctrl: use fallback udelay approach if timekeeping is suspended") added handling for cases when timekeeping is suspended. But looks like we can still get occasional "failed to enable" errors on the PM runtime resume path with udelay() returning faster than expected. With ti-sysc interconnect target module driver this leads into device failure with PM runtime failing with "failed to enable" clkctrl error. Let's fix the issue with a delay of two times the desired delay as in often done for udelay() to account for the inaccuracy. Fixes: 3d8598fb9c5a ("clk: ti: clkctrl: use fallback udelay approach if timekeeping is suspended") Cc: Keerthy <j-keerthy@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lkml.kernel.org/r/20190930154001.46581-1-tony@atomide.com Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-04clk: ti: dra7-atl-clock: Remove ti_clk_add_alias callPeter Ujfalusi
ti_clk_register() calls it already so the driver should not create duplicated alias. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lkml.kernel.org/r/20191002083436.10194-1-peter.ujfalusi@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-04clk: imx: imx8mq: fix sys3_pll_out_selsPeng Fan
It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent. According to the current imx_clk_sccg_pll design, it uses both bypass1/2, however set bypass2 as 1 is not correct, because it will make sys[x]_pll_out use wrong parent and might access wrong registers. So correct bypass2 to 0 and fix sys3_pll_out_sels. Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk") Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-11-01clk: renesas: r8a7796: Add R8A77961 CPG/MSSR supportGeert Uytterhoeven
Add support for the R-Car M3-W+ (R8A77961) SoC to the Renesas Clock Pulse Generator / Module Standby and Software Reset driver. R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for both SoCs to share a driver. R-Car M3-W+ lacks a few modules, so their clocks must be nullified. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023122941.12342-5-geert+renesas@glider.be
2019-11-01clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960Geert Uytterhoeven
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_CLK_R8A77961. Extend the dependency of CONFIG_CLK_R8A77960 from CONFIG_ARCH_R8A7796 to CONFIG_ARCH_R8A77960, to relax dependencies for a future rename of the SoC configuration symbol. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023122941.12342-4-geert+renesas@glider.be
2019-11-01clk: renesas: r8a77965: Remove superfluous semicolonGeert Uytterhoeven
There is no need to terminate a function with a semicolon. Remove it. Reported-by: Biju Das <biju.das@bp.renesas.com> Fixes: 7ce36da900c0a2ff ("clk: renesas: cpg-mssr: Add support for R-Car M3-N") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191016150711.30305-1-geert+renesas@glider.be
2019-10-31clk: ti: divider: convert to use min,max,mask instead of widthTero Kristo
The existing width field used to check divider validity does not provide enough protection against bad values. For example, if max divider value is 4, the smallest all-1 bitmask that can hold this value is 7, which allows values higher than 4 to be used. This typically causes unpredictable results with hardware. So far this issue hasn't been noticed as most of the dividers actually have maximum values which fit the whole bitfield, but there are certain clocks for which this is a problem, like dpll4_m4 divider on omap3 devices. Thus, convert the whole validity logic to use min,max and mask values for determining if a specific divider is valid or not. This prevents the odd cases where bad value would otherwise be written to a divider config register. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Adam Ford <aford173@gmail.com>
2019-10-31clk: ti: divider: cleanup ti_clk_parse_divider_data APITero Kristo
Cleanup the ti_clk_parse_divider_data to pass the divider data struct directly instead of individual values of it. This makes it easier to modify the implementation later on. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Adam Ford <aford173@gmail.com>
2019-10-31clk: ti: divider: cleanup _register_divider and ti_clk_get_div_tableTero Kristo
Cleanup couple of TI divider clock internal APIs. These currently pass huge amount of parameters, which makes it difficult to track what is going on. Abstract most of these under struct clk_omap_div which gets passed over the APIs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Adam Ford <aford173@gmail.com>
2019-10-31clk: ti: am43xx: drop idlest polling from gfx clockTero Kristo
Due to the way ti sysc and hardreset line control is now implemented, it is not possible to poll the clock status for gfx clock independent of hardreset line control. Thus, add a flag to prevent handling this status bit from clock driver. Correct sequencing of events is guaranteed by ti-sysc bus driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: ti: am33xx: drop idlest polling from gfx clockTero Kristo
Due to the way ti sysc and hardreset line control is now implemented, it is not possible to poll the clock status for gfx clock independent of hardreset line control. Thus, add a flag to prevent handling this status bit from clock driver. Correct sequencing of events is guaranteed by ti-sysc bus driver. Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: ti: am33xx: drop idlest polling from pruss clkctrl clockTero Kristo
The PRUSS module on AM33xx SoCs has a hardreset line and is controlled by a PRCM reset line. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for the PRUSS clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to the PRUSS clkctrl clock so that these module status checks are skipped. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: ti: am43xx: drop idlest polling from pruss clkctrl clockTero Kristo
The PRUSS modules on AM43xx SoCs have a hardreset line and are controlled by a PRCM reset line. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for the PRUSS clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to the PRUSS clkctrl clock so that these module status checks are skipped. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: ti: omap5: Drop idlest polling from IPU & DSP clkctrl clocksSuman Anna
The IPU and DSP remote processor cores and their corresponding MMUs on OMAP5 SoCs have hardreset lines associated with them and are controlled by a PRCM reset line each. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for these clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to both the IPU and DSP clkctrl clocks so that these module status checks are skipped. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: ti: omap4: Drop idlest polling from IPU & DSP clkctrl clocksSuman Anna
The IPU and DSP remote processor cores and their corresponding MMUs on OMAP4 SoCs have hardreset lines associated with them and are controlled by a PRCM reset line each. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for these clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to both the IPU and DSP clkctrl clocks so that these module status checks are skipped. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: ti: dra7xx: Drop idlest polling from IPU & DSP clkctrl clocksTero Kristo
The IPU and DSP remote processor cores and their corresponding MMUs on DRA7 SoCs have hardreset lines associated with them and are controlled by a PRCM reset line each. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for these clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to both the IPU and DSP clkctrl clocks so that these module status checks are skipped. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: ti: omap5: add IVA subsystem clkctrl dataTero Kristo
Add clkctrl data for the IVA subsystem (Image and Video Accelerator.) Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: ti: clkctrl: add new exported API for checking standby infoTero Kristo
Standby status is provided for certain clkctrl clocks to see if the given module has entered standby or not. This is mostly needed by remoteproc code to see if the remoteproc has entered standby and the clock can be turned off safely. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: ti: clkctrl: convert to use bit helper macros instead of bitopsTero Kristo
This improves the readibility of the code slightly, and makes modifying the flags bit simpler. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: ti: clkctrl: fix setting up clkctrl clocksTero Kristo
Apply the proper register function for clkctrl clocks, so they get registered under the clk_hw_omap list also. This allows checking their type runtime. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-31clk: rockchip: make clk_half_divider_ops staticBen Dooks (Codethink)
The clk_half_divider_ops is not used outside or declared outside of drivers/clk/rockchip/clk-half-divider.c so make it static to avoid the following warning: drivers/clk/rockchip/clk-half-divider.c:142:22: warning: symbol 'clk_half_divider_ops' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20191017105348.8061-1-ben.dooks@codethink.co.uk Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-29clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D pathMarek Szyprowski
Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D, so the G3D MALI driver can simply adjust the rate of its clock by doing a single clk_set_rate() call, without the need to know the whole clock topology in Exynos542x SoCs. Suggested-by: Marian Mihailescu <mihailescu2m@gmail.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-10-29clk: samsung: exynos5420: Preserve CPU clocks configuration during ↵Marian Mihailescu
suspend/resume Save and restore top PLL related configuration registers for big (APLL) and LITTLE (KPLL) cores during suspend/resume cycle. So far, CPU clocks were reset to default values after suspend/resume cycle and performance after system resume was affected when performance governor has been selected. Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list") Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-10-29clk: samsung: exynos5420: Add VPLL rate tableMarian Mihailescu
Add new table rate for VPLL for Exynos 542x SoC required to support Mali GPU clock frequencies. Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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