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path: root/drivers/clk
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2019-10-29clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18Colin Ian King
The zero'ing of bits 16 and 18 is incorrect. Currently the code is masking with the bitwise-and of BIT(16) & BIT(18) which is 0, so the updated value for val is always zero. Fix this by bitwise and-ing value with the correct mask that will zero bits 16 and 18. Addresses-Coverity: (" Suspicious &= or |= constant expression") Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-29clk: sunxi: Fix operator precedence in sunxi_divs_clk_setupNathan Chancellor
r375326 in Clang exposes an issue with operator precedence in sunxi_div_clk_setup: drivers/clk/sunxi/clk-sunxi.c:1083:30: warning: operator '?:' has lower precedence than '|'; '|' will be evaluated first [-Wbitwise-conditional-parentheses] data->div[i].critical ? ~~~~~~~~~~~~~~~~~~~~~ ^ drivers/clk/sunxi/clk-sunxi.c:1083:30: note: place parentheses around the '|' expression to silence this warning data->div[i].critical ? ^ ) drivers/clk/sunxi/clk-sunxi.c:1083:30: note: place parentheses around the '?:' expression to evaluate it first data->div[i].critical ? ^ ( 1 warning generated. It appears that the intention was for ?: to be evaluated first so that CLK_IS_CRITICAL could be added to clkflags if the critical boolean was set; right now, | is being evaluated first. Add parentheses around the ?: block to have it be evaluated first. Fixes: 9919d44ff297 ("clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks") Link: https://github.com/ClangBuiltLinux/linux/issues/745 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-28clk: ast2600: Fix enabling of clocksJoel Stanley
The struct clk_ops enable callback for the aspeed gates mixes up the set to clear and write to set registers. Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lkml.kernel.org/r/20191016131319.31318-1-joel@jms.id.au Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-28clk: hi6220: use CLK_OF_DECLARE_DRIVERPeter Griffin
As now we also need to probe in the reset driver as well. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Allison Randal <allison@lohutok.net> Cc: Peter Griffin <peter.griffin@linaro.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Link: https://lkml.kernel.org/r/20191001182546.70090-1-john.stultz@linaro.org [sboyd@kernel.org: Add comment about reset driver] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-28clk: at91: avoid sleeping earlyAlexandre Belloni
It is not allowed to sleep to early in the boot process and this may lead to kernel issues if the bootloader didn't prepare the slow clock and main clock. This results in the following error and dump stack on the AriettaG25: bad: scheduling from the idle thread! Ensure it is possible to sleep, else simply have a delay. Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/20190920153906.20887-1-alexandre.belloni@bootlin.com Fixes: 80eded6ce8bb ("clk: at91: add slow clks driver") Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-28clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clockFancy Fang
The mipi pll clock comes from the MIPI PHY PLL output, so it should not be a fixed clock. MIPI PHY PLL is in the MIPI DSI space, and it is used as the bit clock for transferring the pixel data out and its output clock is configured according to the display mode. So it should be used only for MIPI DSI and not be exported out for other usages. Signed-off-by: Fancy Fang <chen.fang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28clk: imx8m: Use SYS_PLL1_800M as intermediate parent of CLK_ARMLeonard Crestez
During cpu frequency switching the main "CLK_ARM" is reparented to an intermediate "step" clock. On imx8mm and imx8mn the 24M oscillator is used for this purpose but it is extremely slow, increasing wakeup latencies to the point that i2c transactions can timeout and system becomes unresponsive. Fix by switching the "step" clk to SYS_PLL1_800M, matching the behavior of imx8m cpufreq drivers in imx vendor tree. This bug was not immediately apparent because upstream arm64 defconfig uses the "performance" governor by default so no cpufreq transitions happen. Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Cc: stable@vger.kernel.org Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Link: https://lkml.kernel.org/r/f5d2b9c53f1ed5ccb1dd3c6624f56759d92e1689.1571771777.git.leonard.crestez@nxp.com Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-28clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify codePeng Fan
imx_obtain_fixed_clk_hw could be used to simplify code to replace __clk_get_hw(of_clk_get_by_name(node, "name")) Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify codePeng Fan
imx_obtain_fixed_clk_hw could be used to simplify code to replace __clk_get_hw(of_clk_get_by_name(node, "name")) Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify codePeng Fan
imx_obtain_fixed_clk_hw could be used to simplify code to replace __clk_get_hw(of_clk_get_by_name(node, "name")) Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify codePeng Fan
imx_obtain_fixed_clk_hw could be used to simplify code to replace __clk_get_hw(of_clk_get_by_name(node, "name")) Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-26clk: imx7ulp: Correct DDR clock mux optionsAnson Huang
In the latest reference manual Rev.0,06/2019, the DDR clock mux is extended to 2 bits, and the clock options are also changed, correct them accordingly. Fixes: b1260067ac3d ("clk: imx: add imx7ulp clk driver") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-26clk: imx7ulp: Correct system clock source option #7Anson Huang
In the latest reference manual Rev.0,06/2019, the SCS's option #7 is no longer from upll, it is reserved, update clock driver accordingly. Fixes: b1260067ac3d ("clk: imx: add imx7ulp clk driver") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25clk: samsung: exynos5420: Preserve PLL configuration during suspend/resumeMarek Szyprowski
Properly save and restore all top PLL related configuration registers during suspend/resume cycle. So far driver only handled EPLL and RPLL clocks, all other were reset to default values after suspend/resume cycle. This caused for example lower G3D (MALI Panfrost) performance after system resume, even if performance governor has been selected. Reported-by: Reported-by: Marian Mihailescu <mihailescu2m@gmail.com> Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-10-25clk: imx: imx8mq: mark sys1/2_pll as fixed clockPeng Fan
According Architecture definition guide, SYS1_PLL is fixed at 800MHz, SYS2_PLL is fixed at 1000MHz, so let's use imx_clk_fixed to register the clocks and drop code that could change the rate. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25clk: imx: imx8mn: mark sys_pll1/2 as fixed clockPeng Fan
According Architecture definition guide, SYS_PLL1 is fixed at 800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed to register the clocks and drop code that could change the rate. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25clk: imx: imx8mm: mark sys_pll1/2 as fixed clockPeng Fan
According Architecture definition guide, SYS_PLL1 is fixed at 800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed to register the clocks and drop code that could change the rate. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25clk: imx8mn: Define gates for pll1/2 fixed dividersLeonard Crestez
On imx8mn there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25clk: imx8mm: Define gates for pll1/2 fixed dividersLeonard Crestez
On imx8mm there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25clk: imx8mq: Define gates for pll1/2 fixed dividersLeonard Crestez
On imx8mq there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate but these gates are not currently defined in the clock tree. Add them between sys1/2_pll_out and the fixed dividers. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-23clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMUMarek Szyprowski
G3D clocks require special handling of their parent bus clock during power domain on/off sequences. Those clocks were not initially added to the sub-CMU handler, because that time there was no open-source driver for the G3D (MALI Panfrost) hardware module and it was not possible to test it. This patch fixes this issue. Parent clock for G3D hardware block is now properly preserved during G3D power domain on/off sequence. This restores proper MALI Panfrost performance broken by commit 8686764fc071 ("ARM: dts: exynos: Add G3D power domain to Exynos542x"). Reported-by: Marian Mihailescu <mihailescu2m@gmail.com> Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Marian Mihailescu <mihailescu2m@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-10-23clk: samsung: exynos5433: Fix error pathsMarek Szyprowski
Add checking the value returned by samsung_clk_alloc_reg_dump() and devm_kcalloc(). While fixing this, also release all gathered clocks. Fixes: 523d3de41f02 ("clk: samsung: exynos5433: Add support for runtime PM") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> [s.nawrocki: squashed patch from K. Kozlowski adding missing slab.h header] Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-10-21Merge tag 'mmp-soc-for-v5.5-2' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp into arm/soc ARM: Marvell MMP SoC patches for v5.5 This tag includes initial support for the Marvell MMP3 processor. MMP3 is used in OLPC XO-4 laptops, Panasonic Toughpad FZ-A1 tablet and Dell Wyse 3020/Tx0D thin clients. * tag 'mmp-soc-for-v5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp: MAINTAINERS: mmp: add Git repository ARM: mmp: remove MMP3 USB PHY registers from regs-usb.h ARM: mmp: move cputype.h to include/linux/soc/ ARM: mmp: add SMP support ARM: mmp: add support for MMP3 SoC ARM: mmp: define MMP_CHIPID by the means of CIU_REG() ARM: mmp: DT: convert timer driver to use TIMER_OF_DECLARE ARM: mmp: map the PGU as well ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP ARM: l2c: add definition for FWA in PL310 aux register Link: https://lore.kernel.org/r/3a035bed90f9d8acc49b2d11d20089b546062aea.camel@v3.sk Signed-off-by: Olof Johansson <olof@lixom.net>
2019-10-21clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()Geert Uytterhoeven
As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the SD clocks on R-Car Gen3 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. This includes implementing range checking. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190830134515.11925-9-geert+renesas@glider.be
2019-10-21clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()Geert Uytterhoeven
As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the Z clocks on R-Car Gen3 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. This includes implementing range checking. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190830134515.11925-8-geert+renesas@glider.be
2019-10-21clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()Geert Uytterhoeven
As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the Z clock on R-Car Gen2 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. This includes implementing range checking. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190830134515.11925-7-geert+renesas@glider.be
2019-10-17ARM: mmp: add support for MMP3 SoCLubomir Rintel
Similar to MMP2, which this patch is based on. Known differencies from MMP2 are: * Two PJ4B cores instead of one PJ4 * Tauros 3 L2 cache controller instead of Tauros 2 * A GIC interrupt controller optionally used instead of the MMP one * A TWD local timer * Different USB2 PHY * A USB3 SS controller * More interrupt muxes Hard to tell what else is different, because documentation is not available. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
2019-10-16clk: sprd: Change to use devm_platform_ioremap_resource()Baolin Wang
Use the new helper that wraps the calls to platform_get_resource() and devm_ioremap_resource() together, which can simpify the code. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Link: https://lkml.kernel.org/r/841d26a2adb4bf3b4423f82a41dd3f1346413db6.1570520268.git.baolin.wang@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: s3c2410: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191015142424.25944-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: axs10x: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191015142259.17216-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: mediatek: mt6797: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191015124728.25072-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: mediatek: mt7629: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191015124226.25792-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: mediatek: mt7622: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191015121735.26228-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: mediatek: mt8183: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191015121421.26144-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: mediatek: mt6779: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191015121035.24736-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: mediatek: mt2712: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191015112644.19816-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: davinci: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191014144407.23264-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: hisilicon: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191014144014.20644-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: bcm2835: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191014143642.24552-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16Merge tag 'clk-meson-fixes-v5.4-1' of https://github.com/BayLibre/clk-meson ↵Stephen Boyd
into clk-fixes Pull first round of amlogic clock fixes from Jerome Brunet: - This fixes the clock rate propagation for the g12a cpu and gxbb adc clocks. * tag 'clk-meson-fixes-v5.4-1' of https://github.com/BayLibre/clk-meson: clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes clk: meson: g12a: fix cpu clock rate setting clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
2019-10-16clk: imx: imx8mn: drop unused pll enumPeng Fan
The PLL enum definition is not used, so drop it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lkml.kernel.org/r/1571122989-29361-1-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: ast2600: remove unused variable 'eclk_parent_names'YueHaibing
drivers/clk/clk-ast2600.c:119:27: warning: eclk_parent_names defined but not used [-Wunused-const-variable=] It is never used, so can be removed. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191015115117.23504-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-14clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-14clk: imx: clk-pll14xx: Make two variables staticYueHaibing
Fix sparse warnings: drivers/clk/imx/clk-pll14xx.c:44:37: warning: symbol 'imx_pll1416x_tbl' was not declared. Should it be static? drivers/clk/imx/clk-pll14xx.c:57:37: warning: symbol 'imx_pll1443x_tbl' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-14clk: imx8mq: Add VIDEO2_PLL clockLaurentiu Palcu
This clock is needed by DCSS when high resolutions are used. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com> CC: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-08clk: meson: axg_audio: add sm1 supportJerome Brunet
Add sm1 support the axg audio clock controllers. This new version is indeed derived from the previous generation, as always, adding a few new clocks to the mix. The number of gates now exceeds 32 and do not fit in a single register. Unfortunately, designers chose to introduce the new gate register immediately after the original one, at the beginning of the register space, shifting all the master clock register offsets. The sm1 also introduce a few mux and divider on the top clock path, possibly to lower the peripheral clocks of the audio blocks if necessary. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-08clk: meson: axg-audio: provide clk top signal nameJerome Brunet
The peripheral clock on the sm1 goes through some muxes and dividers before reaching the audio gates. To model that, without repeating our self too much, the "top" clock signal is introduced and will serve as a the parent of the gates. On the axg and g12a, the top clock is just a pass-through to the audio peripheral clock provided by the main controller. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-08clk: meson: axg-audio: prepare sm1 additionJerome Brunet
Rearrange the macro definition of the clocks of the axg-audio controller. Also, the sm1 variant will feature tiny modification of different blocks in this controller. Because of that, we need to fallback to the old way of defining parent for some of the clocks, using signal name. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-08clk: meson: axg-audio: fix regmap last registerJerome Brunet
Since the addition of the g12a, the last register is AUDIO_CLK_SPDIFOUT_B_CTRL. Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support") Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-08clk: meson: axg-audio: remove useless definesJerome Brunet
Defining the number of each input type is no longer necessary since we are not using the clk-input hack anymore Fixes: 282420eed23f ("clk: meson: axg-audio: migrate to the new parent description method") Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
generated by cgit (git 2.34.1) at 2025-09-12 03:25:39 +0000