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into clk-fixes
Pull Meson clk driver fixes from Jerome Brunet:
- MPLL50M DT bindings typo fix
- Meson9 VPU typo fixes
* tag 'clk-meson-5.2-1-fixes' of https://github.com/BayLibre/clk-meson:
clk: meson: meson8b: fix a typo in the VPU parent names array variable
clk: meson: fix MPLL 50M binding id typo
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Building COMMON_CLK_XGENE is pointless, unless we're building for
an XGENE system.
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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On Amlogic Meson G12b platform, the fclk_div3 seems to be necessary for
the system to operate correctly.
Disabling it cause the entire system to freeze, including peripherals.
Let's mark this clock as critical, fixing boot on G12b platforms.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Update the Meson G12A Clock driver to support the Amlogic G12B SoC.
G12B clock driver is very close, the main differences are :
- the clock tree is duplicated for the both clusters, and the
SYS_PLL are swapped between the clusters
- G12B has additional clocks like for CSI an other components
Here only the cpu clock tree is handled.
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Add the TS clocks used by two temperature sensors
Reviewed-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [fixed commit description]
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Add the cts_i958 clock to control the clock source of the spdif output
block. It is used to select whether the clock source of the spdif output
is cts_amclk (when data are taken from i2s buffer) or the cts_mclk_i958
(when data are taken from the spdif buffer). The setup for this clock is
identical to GXBB, so this ports commit 7eaa44f6207fb6 ("clk: meson:
gxbb: add cts_i958 clock") to the Meson8/Meson8b/Meson8m2 clock driver.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Add the SPDIF master clock also referred as cts_mclk_i958. The setup for
this clock is identical to GXBB, so this ports commit 3c277c247eabeb
("clk: meson: gxbb: add cts_mclk_i958") to the Meson8/Meson8b/Meson8m2
clock driver.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Add the I2S master clock also referred as cts_amclk. The setup for this
clock is identical to GXBB, so this ports commit 4087bd4b21702d ("clk:
meson: gxbb: add cts_amclk") to the Meson8/Meson8b/Meson8m2 clock
driver.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Failing to toggle a GDSC as the driver core is attaching the
power-domain to a device will cause a silent probe deferral. Provide an
explicit warning to the developer, in order to reduce the amount of time
it takes to debug this.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Tested-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Fixes gcc '-Wunused-but-set-variable' warning:
drivers/clk/mmp/clk-frac.c: In function clk_factor_set_rate:
drivers/clk/mmp/clk-frac.c:81:16: warning: variable prev_rate set but not used [-Wunused-but-set-variable]
It's never used and can be removed.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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They are not used any more since
commit 7558562a70fb ("clk: ti: Drop legacy clk-3xxx-legacy code")
Reported-by: Hulk Robot <hulkci@huawei.com>
Suggested-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Variable 'ddrphycfg_parents' is defined static and initialized, but not
used in the file.
../drivers/clk/mediatek/clk-mt8516.c:234:27: warning: ‘ddrphycfg_parents’ defined but not used [-Wunused-const-variable=]
static const char * const ddrphycfg_parents[] __initconst = {
^~~~~~~~~~~~~~~~~
Signed-off-by: Philippe Mazenauer <philippe.mazenauer@outlook.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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The code was setting the bit 21 of the CPCCR register to use a divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.
This is the opposite of how this register field works: a cleared bit
means that the /2 divider is used, and a set bit means that the divider
is 1.
Restore the correct behaviour using the newly introduced .div_table
field.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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The main clocks (cclk, hclk, pclk, mclk, ipu) were using
incorrect dividers, and thus reported an incorrect rate.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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The main clocks (cclk, h0clk, h1clk, h2clk, c1clk, pclk) were using
incorrect dividers, and thus reported an incorrect rate.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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The main clocks (cclk, hclk, pclk, mclk, lcd) were using
incorrect dividers, and thus reported an incorrect rate.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Some clocks provided on Ingenic SoCs have dividers, whose hardware value
as written in the register cannot be expressed as an affine function
to the actual divider value.
For instance, for the CPU clock on the JZ4770, the dividers are coded as
follows:
------------------
| Bits | Div |
------------------
| 0 0 0 | 1 |
| 0 0 1 | 2 |
| 0 1 0 | 3 |
| 0 1 1 | 4 |
| 1 0 0 | 6 |
| 1 0 1 | 8 |
| 1 1 0 | 12 |
------------------
To support this setup, we introduce a new field in the
ingenic_cgu_div_info structure that allows to specify the divider table.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Currently, the clock identifiers are limited to 255. To support future
SoCs, this muse be extended to 32 bits, which should provide way more
than enough space. Basic support for extending the clock API is going
to be implemented in the firmware driver, but there are some minor
changes that need to be done on the clock driver side first.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Probing all the available clocks from the PM firmware takes quite a lot
of time, increasing boot time. Instead, implement functionality that
parses only the used clocks from DT, and registers these to clock core.
This way, the boot time is greatly improved.
Additionally, provide a Kconfig option for parsing all the clocks from
firmware, if someone requires this. It is mostly useful as a debugging
functionality if we want to inspect the whole clock tree.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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This makes it both easier to see what the probe does, and also makes it
possible to add alternative implementations for the clock data source.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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There is no need to store the full node name to the individual clocks,
as this will just consome memory and make the clock debug entries
unnecessary long. Just shorten this to "clk" for now.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Switch the entire clk-imx6sll driver to clk_hw based API.
This allows us to move closer to a clear split between
consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the entire clk-imx7d driver to clk_hw based API. This allows us
to move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the entire clk-imx6ul driver to clk_hw based API. This allows us
to move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the entire clk-imx6sx driver to clk_hw based API. This allows us
to move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the entire clk-imx6q driver to clk_hw based API.
Add imx6q_obtain_fixed_clk_hw helper to clean up the registration
of the clocks that are either found in device tree or are assigned
a fixed zero rate. This switch allows us to move closer to a clear
split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the entire clk-imx6sl driver to clk_hw based API.
This allows us to move closer to a clear split between
consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch all the wrappers to clk_hw based API and rename them to indicate
that. Add macros for clk based legacy users. This allows us to move
closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the imx_clk_fixup_mux function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. a macro for clk
based legacy. This allows us to move closer to a clear split between
consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the imx_clk_fixup_divider function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to
move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the imx_clk_gate_exclusive function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to move
closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the imx_clk_pfd function to clk_hw based API, rename accordingly
and add a macro for clk based legacy. This allows us to move closer to
a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the imx_clk_hw_pllv3 function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us
to move closer to a clear split between consumer and provider clk
APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the clk_register_gate2 function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to
move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch the clk_cpu clock registering function to clk_hw based API and add
a macro for clk based legacy. This allows us to move closer to a clear
split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Switch all the clk_busy clock registering functions to clk_hw based API.
Keep around some clk based wrappers to be used by older imx platforms.
This allows us to move closer to a clear split of consumer and provider
clk APIs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The clock is registered later than these two re-parentings.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The clock IMX6SX_CLK_AXI is not registered at all.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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In order to move to clk_hw based API, imx_obtain_fixed_clock_hw
is added. The end goal here is to have all the clk providers use
the clk_hw based API.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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There is no audio_pll2_clk registered, it should be audio_pll2_out.
Cc: <stable@vger.kernel.org>
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Remove MT8183 sspm clock
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add audsys clock driver for MediaTek MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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ARCH_BRCMSTB needs to use the BCM2835 clock driver for chips like
BCM7211 which adopted that clock controller, make that possible and the
driver default to be enabled for ARCH_BRCMSTB.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Make the BCM2835 clock driver selectable by other
architectures/platforms. ARCH_BRCMSTB will be selecting that driver in
the next commit since new chips like 7211 use the same CPRMAN clock
controller that this driver supports.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Commit 9fba738a53dda2 ("clk: add duty cycle support") added support for
getting and setting the duty cycle of a clock. This implements the
get_duty_cycle callback for PWM based clocks so the duty cycle is shown
in the debugfs output (/sys/kernel/debug/clk/clk_summary).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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If we do a clk_get() for a clock that does not exists, we have
_ti_omap4_clkctrl_xlate() return uninitialized data if no match
is found. This can be seen in some cases with SLAB_DEBUG enabled:
Unable to handle kernel paging request at virtual address 5a5a5a5a
...
clk_hw_create_clk.part.33
sysc_notifier_call
notifier_call_chain
blocking_notifier_call_chain
device_add
Let's fix this by setting a found flag only when we find a match.
Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Fixes: 88a172526c32 ("clk: ti: add support for clkctrl clocks")
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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This patch provides support for clocks needed for Dynamic Memory Controller
in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
GATE entries.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
Controller frequencies for driver's DRAM timings.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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The 48 MHz PLL rate is not present in the downstream chromeos-3.14
tree. Looking at history, it was originally removed in
<https://crrev.com/c/265810> ("CHROMIUM: clk: rockchip: expand more
clocks support") with no explanation. Much of that patch was later
reverted in <https://crrev.com/c/284595> ("CHROMIUM: clk: rockchip:
Revert more questionable PLL rates"), but that patch left in the
removal of 48 MHz. What I wrote in that patch:
> Note that the original change also removed the rate (48000000, 1,
> 64, 32) from the table. I have no idea why that was squashed in
> there, but that rate was invalid anyway (it appears to have an out
> of bounds NO). I'm not putting that rate in.
Reading the TRM I see that NO is defined as
- NO: 1, 2-16 (even only)
...and furthermore only 4 bits are assigned for NO-1, which means that
the highest NO we could even represent is 16.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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