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2025-06-17drm/i915/dsb: Move the DSB_PMCTRL* reset out of intel_dsb_finish()Ville Syrjälä
When using the flip queue, due to the DMC vs. DSB register corruption problem, we must not issue any register writes from the DSB after unhalting the DMC. Currently we are doing just that by trying to restore DSB_PMCTRL* back to a sane state from intel_dsb_finish(). Since the only place left that pokes at DSB_PMCTRL* is intel_dsb_chain() we can just do DSB_PMCTRL_2/DSB_FORCE_DEWAKE reset in the same place. The DSB_PMCTRL reset is trickier since we'd have to do it from the chained DSB itself. But based on my earlier testing DSB_PMCTRL/DSB_ENABLE_DEWAKE doesn't actually do anything if the DSB isn't actually enabled, so we can omit the reset to keep things a bit simpler. We do need to reset DSB_PMCTRL/DSB_ENABLE_DEWAKE before tarting the DSB however, in case it was left enabled from a previous use. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250612145018.8735-6-ville.syrjala@linux.intel.com
2025-06-17drm/i915/dsb: Garbage collect the MMIO DEwake stuffVille Syrjälä
Since the introduction of DSB chaining we no longer need the DEwake tricks in intel_dsb_commit(). I also need to relocate the DSB_PMCTRL* writes out of intel_dsb_finish() (due to the flip queue DMC vs. DSB register corruption issues), and it'll be a bit more straightforward if I don't have to worry about the non-chained DSB path anymore. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250612145018.8735-5-ville.syrjala@linux.intel.com
2025-06-17drm/i915/dsb: Introduce intel_dsb_exec_time_us()Ville Syrjälä
Pull the magic 20 usec DSB execution deadline into intel_dsb_arm_exec_time_us(), and also add its counterpart for the non-arming register write section. For the non-arming part we'll just throw in a random 80 usec for now so the total is 100usec. The total exec time will be needed by the upcoming flip queue code. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250612145018.8735-4-ville.syrjala@linux.intel.com
2025-06-17drm/i915/dsb: Provide intel_dsb_head() and intel_dsb_size()Ville Syrjälä
The upcoming flip queue implementation will need to know the DSB buffer head and size. Expose those outside intel_dsb.c. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250612145018.8735-3-ville.syrjala@linux.intel.com
2025-06-17drm/i915/dsb: Use intel_dsb_ins_align() in intel_dsb_align_tail()Ville Syrjälä
If the free_post is not QW aligned we don't have to memset the extra DW needed to make it so, as the only way that can happen is via intel_dsb_reg_write_indexed() which already makes sure the next DW is zeroed. Not a big deal, but this is more consistent how all the other stuff operates that puts instructions into the DSB buffer, and we'll get a few more of those soon. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250612145018.8735-2-ville.syrjala@linux.intel.com
2025-06-16drm/i915/dsi: Fix off by one in BXT_MIPI_TRANS_VTOTALVille Syrjälä
BXT_MIPI_TRANS_VTOTAL must be programmed with vtotal-1 instead of vtotal. Make it so. Cc: stable@vger.kernel.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250314150136.22564-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit 7b3685c9b38c3097f465efec8b24dbed63258cf6) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2025-06-14drm/i915/dsi: Assert that vfp+vsync+vbp == vtotal on BXT/GLKVille Syrjälä
Windows code seems to do some dodgy looking +/-1 adjustments to some of the vertical timings. Not sure if that's correct or not, but let's at least cross check some of the values we got from the hardware to double check whether the GOP did the same or not. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250314150136.22564-3-ville.syrjala@linux.intel.com Acked-by: Jani Nikula <jani.nikula@intel.com>
2025-06-14drm/i915/dsi: Fix off by one in BXT_MIPI_TRANS_VTOTALVille Syrjälä
BXT_MIPI_TRANS_VTOTAL must be programmed with vtotal-1 instead of vtotal. Make it so. Cc: stable@vger.kernel.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250314150136.22564-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-06-12drm/i915/dp: Disable the AUX DPCD probe quirk if it's not requiredImre Deak
Reading DPCD registers has side-effects and some of these can cause a problem for instance during link training. Based on this it's better to avoid the probing quirk done before each DPCD register read, limiting this to the monitor which requires it. The only known problematic monitor is an external SST sink, so keep the quirk disabled always for eDP and MST sinks. Reenable the quirk after a hotplug event and after resuming from a power state without hotplug support, until the subsequent EDID based detection. v2: Add a helper for determining the need/setting the probing. (Jani) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250609125556.109538-2-imre.deak@intel.com
2025-06-11drm/i915/display: drop i915_reg.h include where possibleJani Nikula
A number of files have unnecessary i915_reg.h includes. Drop them. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://lore.kernel.org/r/7c4002322f4d8132fd2eaa1a4d688539cdd043c3.1749469962.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-11drm/i915/display: include intel_display_reg_defs.h from display regs filesJani Nikula
Some display register files include i915_reg_defs.h, some don't include anything. Prefer intel_display_reg_defs.h in display. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://lore.kernel.org/r/06c24e1f6a7a2f6b4801b0a079eec3cc924402a7.1749469962.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-11drm/i915/panel: sync panel prepared state at registerJani Nikula
If the panel is enabled at probe, and we take over the hardware state, the drm_panel prepared state will be out of sync. We'll need to notify drm_panel framework about the state at probe, so it can in turn notify the panel followers. Cc: Lee Shawn C <shawn.c.lee@intel.com> Tested-by: Lee Shawn C <shawn.c.lee@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/a33e4fe5e9970aed9c4aef8c426c00a189149c32.1749199013.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-11drm/i915/panel: register drm_panel and call prepare/unprepare for ICL+ DSIJani Nikula
Allocate and register a drm_panel so that drm_panel_followers can find the panel. Pass the drm_connector::kdev device to drm_panel allocation for matching. That's only available after drm_sysfs_connector_add(), so we need to postpone the drm_panel allocation until .late_register() hook. The drm_panel framework is moving towards devm_drm_panel_alloc(). It requires a wrapper struct, and struct intel_panel would be the natural candidate. However, we can't postpone its allocation until .late_register(), so we have to use __devm_drm_panel_alloc() directly for now. Call the drm_panel_prepare() and drm_panel_unprepare() functions for ICL+ DSI, so that followers get notified of the panel power state changes. This can later be expanded to VLV+ DSI and eDP. Cc: Maxime Ripard <mripard@kernel.org> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Cc: Lee Shawn C <shawn.c.lee@intel.com> Tested-by: Lee Shawn C <shawn.c.lee@intel.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/13d15c1414e65ffb21944d66e2820befdab54e98.1749199013.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-11drm/i915/panel: add panel register/unregisterJani Nikula
Add panel register/unregister functions, and handle backlight register/unregister from there. This is in preparation for adding more panel specific register/unregister functionality. Cc: Lee Shawn C <shawn.c.lee@intel.com> Tested-by: Lee Shawn C <shawn.c.lee@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@gmail.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/b737d4bc8b91df630cd4db4648f3a3571989cfd8.1749199013.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-09drm/i915: split out display register macros to a separate fileJani Nikula
This is a scripted split of the display related register macros from i915_reg.h to display/intel_display_regs.h. As a starting point, move all the macros that are only used in display code (or GVT). If there are users in core i915 code or soc/, or no users anywhere, keep the macros in i915_reg.h. This is done in groups of macros separated by blank lines, moving the comments along with the groups. Some manually picked macro groups are kept/moved regardless of the heuristics above. This is obviously a very crude approach. It's not perfect. But there are 4.2k lines in i915_reg.h, and its refactoring has ground to a halt. This is the big hammer that splits the file to two, and enables further cleanup. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> # v2 Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20250606102256.2080073-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-06Merge tag 'drm-next-2025-06-06' of https://gitlab.freedesktop.org/drm/kernelLinus Torvalds
Pull drm fixes from Dave Airlie: "This is pretty much two weeks worth of fixes, plus one thing that might be considered next: amdkfd is now able to be enabled on risc-v platforms. Otherwise, amdgpu and xe with the majority of fixes, and then a smattering all over. panel: - nt37801: fix IS_ERR - nt37801: fix KConfig connector: - Fix null deref in HDMI audio helper. bridge: - analogix_dp: fixup clk-disable removal nouveau: - minor typo fix (',' vs ';') msm: - mailmap updates i915: - Fix the enabling/disabling of DP audio SDP splitting - Fix PSR register definitions for ALPM - Fix u32 overflow in SNPS PHY HDMI PLL setup - Fix GuC pending message underflow when submit fails - Fix GuC wakeref underflow race during reset xe: - Two documentation fixes - A couple of vm init fixes - Hwmon fixes - Drop reduntant conversion to bool - Fix CONFIG_INTEL_VSEC dependency - Rework eviction rejection of bound external bos - Stop re-submitting signalled jobs - A couple of pxp fixes - Add back a fix that got lost in a merge - Create LRC bo without VM - Fix for the above fix amdgpu: - UserQ fixes - SMU 13.x fixes - VCN fixes - JPEG fixes - Misc cleanups - runtime pm fix - DCN 4.0.1 fixes - Misc display fixes - ISP fix - VRAM manager fix - RAS fixes - IP discovery fix - Cleaner shader fix for GC 10.1.x - OD fix - Non-OLED panel fix - Misc display fixes - Brightness fixes amdkfd: - Enable CONFIG_HSA_AMD on RISCV - SVM fix - Misc cleanups - Ref leak fix - WPTR BO fix radeon: - Misc cleanups" * tag 'drm-next-2025-06-06' of https://gitlab.freedesktop.org/drm/kernel: (105 commits) drm/nouveau/vfn/r535: Convert comma to semicolon drm/xe: remove unmatched xe_vm_unlock() from __xe_exec_queue_init() drm/xe: Create LRC BO without VM drm/xe/guc_submit: add back fix drm/xe/pxp: Clarify PXP queue creation behavior if PXP is not ready drm/xe/pxp: Use the correct define in the set_property_funcs array drm/xe/sched: stop re-submitting signalled jobs drm/xe: Rework eviction rejection of bound external bos drm/xe/vsec: fix CONFIG_INTEL_VSEC dependency drm/xe: drop redundant conversion to bool drm/xe/hwmon: Move card reactive critical power under channel card drm/xe/hwmon: Add support to manage power limits though mailbox drm/xe/vm: move xe_svm_init() earlier drm/xe/vm: move rebind_work init earlier MAINTAINERS: .mailmap: update Rob Clark's email address mailmap: Update entry for Akhil P Oommen MAINTAINERS: update my email address MAINTAINERS: drop myself as maintainer drm/i915/display: Fix u32 overflow in SNPS PHY HDMI PLL setup drm/amd/display: Fix default DC and AC levels ...
2025-06-05drm/i915: use drm_modeset_lock_assert_held() in intel_connector_get_pipe()Luca Coelho
In the intel_connector_get_pipe() function, we check if connection_mutex is held and generate our own WARN_ON if that's the case. Instead of generating a non-standard warning for a mutex issue, we should use the standard lockdep framework. Change the function to use drm_modeset_lock_assert_held() instead. Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250520095408.1310440-1-luciano.coelho@intel.com
2025-06-05drm/i915: remove unused arg in skl_scaler_get_filter_select()Luca Coelho
We always pass 0 in the set argument of skl_scaler_get_filter_select() calls, so the argument is unnecessary. Remove it. Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250520082917.1302665-3-luciano.coelho@intel.com
2025-06-05drm/i915/dkl: return if tc_port is invalid in dkl_phy_set_hip_idx()Luca Coelho
In dkl_phy_set_hip_idx(), we may try to shift a value negatively, whose behavior is undefined. This can happen because we define TC_PORT_NONE to -1, so theoretically tc_port could be -1. We will then use tc_port to shift to the correct address of the specified port, but if it's negative, anything can happen. If this happens or tc_port exceeds I915_MAX_TC_PORTS, it's safer to return with a warning than risk an invalid write. Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250520082917.1302665-2-luciano.coelho@intel.com
2025-06-04drm/i915/wm: DG2 doesn't have dram info to look up wm_lv_0_adjust_neededJani Nikula
There's no dram info on DG2 that we could use. The struct dram_info is all zero on it, but be explicit about this. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://lore.kernel.org/r/a866641bff364dcfcaaabaa1d53c4a8cfa94ff3f.1748337870.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-04drm/i915/dram: add accessor for struct dram_info and use itJani Nikula
Add a function to get the (const) pointer to struct dram_info, and use that to obtain the pointer instead of poking at i915->dram_info directly. Clean up a couple of local variables while at it. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://lore.kernel.org/r/4174edf649e2f6805dab6fd6ce2ec10f4e5f2498.1748337870.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-04drm/i915/bw: pass struct dram_info pointer aroundJani Nikula
Have just one place to figure out the pointer to struct dram_info, and pass that around. This simplifies future changes. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://lore.kernel.org/r/1752b4987ff39a685c28cebae1be4ce326b67c7b.1748337870.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-04drm/i915/display: Fix u32 overflow in SNPS PHY HDMI PLL setupDibin Moolakadan Subrahmanian
When configuring the HDMI PLL, calculations use DIV_ROUND_UP_ULL and DIV_ROUND_DOWN_ULL macros, which internally rely on do_div. However, do_div expects a 32-bit (u32) divisor, and at higher data rates, the divisor can exceed this limit. This leads to incorrect division results and ultimately misconfigured PLL values. This fix replaces do_div calls with div64_base64 calls where diviser can exceed u32 limit. Fixes: 5947642004bf ("drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250528064557.4172149-1-dibin.moolakadan.subrahmanian@intel.com (cherry picked from commit ce924116e43ffbfa544d82976c4b9d11bcde9334) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2025-06-04drm/i915/sbi: clean up SBI register macro definitions and usageJani Nikula
Use REG_BIT() and friends for defining the register macros. Switch GVT to use the same macros, and drop its own copies. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/e148e8621c6055d0441fdf6d651d4ad24be53d09.1748343520.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-04drm/i915/sbi: split out intel_sbi_regs.hJani Nikula
Split out display/intel_sbi_regs.h from i915_reg.h. Include both the SBI interface MMIO as well as the known sideband offsets. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/c96197159e05ebcb63fcc05f0f0801624cd4fdeb.1748343520.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-04drm/i915/sbi: convert to intel_de_*()Jani Nikula
Convert SBI to use the intel_de_*() interface. This allows us to drop the dependency in i915_drv.h while at it. The fast timeout for the status wait drops from 100 us to 2 us on i915, but that should be of no consequence. The slow timeout remains the same. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/146f9027f565feb827861f06c1ae218b378edd95.1748343520.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-04drm/i915: add out_value to intel_wait_for_register_fw() and intel_de_wait_fw()Jani Nikula
Future users of intel_de_wait_fw() need the final value. Just return it for everyone using intel_wait_for_register_fw() and intel_de_wait_fw() to avoid adding or using another set of specialized functions. There aren't that many users for these anyway. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/f804b2fe85ad63389e74d82e4c97220e9275f170.1748343520.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-04drm/i915/de: rename timeout parameters timeout_ms to highlight unitJani Nikula
The timeout parameters are in ms. Rename the parameters to highlight the unit. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/cd4c775ad323a577f612e6a942f83b22641fb798.1748343520.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-04drm/i915/sbi: move sbi_lock under struct intel_displayJani Nikula
With SBI under display, also move sbi_lock to display->sbi.lock. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/838fa712fc8a691a3f9427e5f4ed551bd1c62c49.1748343520.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-04drm/i915/sbi: convert intel_sbi.[ch] to struct intel_displayJani Nikula
Convert intel_sbi.[ch] to struct intel_display, as much as possible anyway, and as a consequence drop the dependency on i915_drv.h from intel_pch_refclk.c. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/9fa9f9a828a7e0e93208111566478b16838abe0d.1748343520.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-04drm/i915/sbi: move intel_sbi.[ch] under display/Jani Nikula
The LPT/WPT SBI is arguably part of south display, and it's only used by intel_pch_refclk.c anyway. Move it under display/. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/341268d633e9705bc582f1cc985dc4554e39d87d.1748343520.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-06-03drm/i915/display: Fix u32 overflow in SNPS PHY HDMI PLL setupDibin Moolakadan Subrahmanian
When configuring the HDMI PLL, calculations use DIV_ROUND_UP_ULL and DIV_ROUND_DOWN_ULL macros, which internally rely on do_div. However, do_div expects a 32-bit (u32) divisor, and at higher data rates, the divisor can exceed this limit. This leads to incorrect division results and ultimately misconfigured PLL values. This fix replaces do_div calls with div64_base64 calls where diviser can exceed u32 limit. Fixes: 5947642004bf ("drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250528064557.4172149-1-dibin.moolakadan.subrahmanian@intel.com
2025-06-02drm/i915/psr: Fix using wrong mask in REG_FIELD_PREPJouni Högander
Wrong mask is used in PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION. Fixes: 295099580f04 ("drm/i915/psr: Add missing ALPM AUX-Less register definitions") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-12-jouni.hogander@intel.com (cherry picked from commit 8097128a40ff378761034ec72cdbf6f46e466dc0) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2025-05-29drm/i915/psr: Do not disable Panel Replay in case VRR is enabledJouni Högander
Allow Panel Replay with VRR. All VRR modes are supposed to work with Panel Replay. Bspec: 68920, 68925 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-13-jouni.hogander@intel.com
2025-05-29drm/i915/psr: Fix using wrong mask in REG_FIELD_PREPJouni Högander
Wrong mask is used in PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION. Fixes: 295099580f04 ("drm/i915/psr: Add missing ALPM AUX-Less register definitions") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-12-jouni.hogander@intel.com
2025-05-29drm/i915/display: Add function to configure LFPS sendingJouni Högander
Add function to configre LFPS sending for Panel Replay according to link training sequence in HAS document. This assumes we are using AUX Less always if it's supported by the sink and the source. v2: - drop HAS reference - replay kerneldoc comment with a generic comment - check display version in intel_lnl_mac_transmit_lfps Bspec: 68849 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-11-jouni.hogander@intel.com
2025-05-29drm/i915/display: Add PHY_CMN1_CONTROL register definitionsJouni Högander
Add PHY_CMN1_CONTROL register and its definitions to configure port LFPS sending. Bspec: 68962 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-10-jouni.hogander@intel.com
2025-05-29drm/i915/alpm: Move port alpm configurationJouni Högander
It is specified in Bspec where port alpm configuration is supposed to be performed. Change accordingly. v2: - drop HAS reference - ensure PORT_ALPM registers are not writen on older platform Bspec: 68849 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-9-jouni.hogander@intel.com
2025-05-29drm/i915/alpm: Add new interface to check if AUXLess ALPM is usedJouni Högander
we need to know if AUXLess ALPM is used when preparing for link training. Add new interface for this and use it in existing code where possible. v2: remove kerneldoc comment Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-8-jouni.hogander@intel.com
2025-05-29drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSRJouni Högander
Currently we spread ugly PSR details into ALPM code to check if AUXLess ALPM is needed. Prepare to hide these details to PSR code by adding new interface for checking if AUXLess ALPM is needed. v2: remove kerneldoc comment Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-7-jouni.hogander@intel.com
2025-05-29drm/i915/alpm: Write PR_ALPM_CTL registerJouni Högander
PR_ALPM_CTL register contains configurations related to Adaptive sync sdp. Configure these if Adaptive Sync SDP is supported. v2: avoid using hardcoded indices Bspec: 71014 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-6-jouni.hogander@intel.com
2025-05-29drm/i915/alpm: Add PR_ALPM_CTL register definitionsJouni Högander
Add PR_ALPM_CTL register definition and bits for it. Bspec: 71014 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-5-jouni.hogander@intel.com
2025-05-29drm/i915/psr: Read all Panel Replay capability registers from DPCDJouni Högander
There are several Panel Replay capability register in DPCD. Read them all for later use. v2: - avoid using hardcoded indices - read all Panel Replay capability registers Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-4-jouni.hogander@intel.com
2025-05-29drm/panelreplay: Panel Replay capability DPCD register definitionsJouni Högander
Add new definition for size of Panel Replay DPCD capability registers area. Rename existing definitions to group capability registers together. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://lore.kernel.org/r/20250526120512.1702815-2-jouni.hogander@intel.com
2025-05-28Merge tag 'drm-next-2025-05-28' of https://gitlab.freedesktop.org/drm/kernelLinus Torvalds
Pull drm updates from Dave Airlie: "As part of building up nova-core/nova-drm pieces we've brought in some rust abstractions through this tree, aux bus being the main one, with devres changes also in the driver-core tree. Along with the drm core abstractions and enough nova-core/nova-drm to use them. This is still all stub work under construction, to build the nova driver upstream. The other big NVIDIA related one is nouveau adds support for Hopper/Blackwell GPUs, this required a new GSP firmware update to 570.144, and a bunch of rework in order to support multiple fw interfaces. There is also the introduction of an asahi uapi header file as a precursor to getting the real driver in later, but to unblock userspace mesa packages while the driver is trapped behind rust enablement. Otherwise it's the usual mixture of stuff all over, amdgpu, i915/xe, and msm being the main ones, and some changes to vsprintf. new drivers: - bring in the asahi uapi header standalone - nova-drm: stub driver rust dependencies (for nova-core): - auxiliary - bus abstractions - driver registration - sample driver - devres changes from driver-core - revocable changes core: - add Apple fourcc modifiers - add virtio capset definitions - extend EXPORT_SYNC_FILE for timeline syncobjs - convert to devm_platform_ioremap_resource - refactor shmem helper page pinning - DP powerup/down link helpers - extended %p4cc in vsprintf.c to support fourcc prints - change vsprintf %p4cn to %p4chR, remove %p4cn - Add drm_file_err function - IN_FORMATS_ASYNC property - move sitronix from tiny to their own subdir rust: - add drm core infrastructure rust abstractions (device/driver, ioctl, file, gem) dma-buf: - adjust sg handling to not cache map on attach - allow setting dma-device for import - Add a helper to sort and deduplicate dma_fence arrays docs: - updated drm scheduler docs - fbdev todo update - fb rendering - actual brightness ttm: - fix delayed destroy resv object bridge: - add kunit tests - convert tc358775 to atomic - convert drivers to devm_drm_bridge_alloc - convert rk3066_hdmi to bridge driver scheduler: - add kunit tests panel: - refcount panels to improve lifetime handling - Powertip PH128800T004-ZZA01 - NLT NL13676BC25-03F, Tianma TM070JDHG34-00 - Himax HX8279/HX8279-D DDIC - Visionox G2647FB105 - Sitronix ST7571 - ZOTAC rotation quirk vkms: - allow attaching more displays i915: - xe3lpd display updates - vrr refactor - intel_display struct conversions - xe2hpd memory type identification - add link rate/count to i915_display_info - cleanup VGA plane handling - refactor HDCP GSC - fix SLPC wait boosting reference counting - add 20ms delay to engine reset - fix fence release on early probe errors xe: - SRIOV updates - BMG PCI ID update - support separate firmware for each GT - SVM fix, prelim SVM multi-device work - export fan speed - temp disable d3cold on BMG - backup VRAM in PM notifier instead of suspend/freeze - update xe_ttm_access_memory to use GPU for non-visible access - fix guc_info debugfs for VFs - use copy_from_user instead of __copy_from_user - append PCIe gen5 limitations to xe_firmware document amdgpu: - DSC cleanup - DC Scaling updates - Fused I2C-over-AUX updates - DMUB updates - Use drm_file_err in amdgpu - Enforce isolation updates - Use new dma_fence helpers - USERQ fixes - Documentation updates - SR-IOV updates - RAS updates - PSP 12 cleanups - GC 9.5 updates - SMU 13.x updates - VCN / JPEG SR-IOV updates amdkfd: - Update error messages for SDMA - Userptr updates - XNACK fixes radeon: - CIK doorbell cleanup nouveau: - add support for NVIDIA r570 GSP firmware - enable Hopper/Blackwell support nova-core: - fix task list - register definition infrastructure - move firmware into own rust module - register auxiliary device for nova-drm nova-drm: - initial driver skeleton msm: - GPU: - ACD (adaptive clock distribution) for X1-85 - drop fictional address_space_size - improve GMU HFI response time out robustness - fix crash when throttling during boot - DPU: - use single CTL path for flushing on DPU 5.x+ - improve SSPP allocation code for better sharing - Enabled SmartDMA on SM8150, SC8180X, SC8280XP, SM8550 - Added SAR2130P support - Disabled DSC support on MSM8937, MSM8917, MSM8953, SDM660 - DP: - switch to new audio helpers - better LTTPR handling - DSI: - Added support for SA8775P - Added SAR2130P support - HDMI: - Switched to use new helpers for ACR data - Fixed old standing issue of HPD not working in some cases amdxdna: - add dma-buf support - allow empty command submits renesas: - add dma-buf support - add zpos, alpha, blend support panthor: - fail properly for NO_MMAP bos - add SET_LABEL ioctl - debugfs BO dumping support imagination: - update DT bindings - support TI AM68 GPU hibmc: - improve interrupt handling and HPD support virtio: - add panic handler support rockchip: - add RK3588 support - add DP AUX bus panel support ivpu: - add heartbeat based hangcheck mediatek: - prepares support for MT8195/99 HDMIv2/DDCv2 anx7625: - improve HPD tegra: - speed up firmware loading * tag 'drm-next-2025-05-28' of https://gitlab.freedesktop.org/drm/kernel: (1627 commits) drm/nouveau/tegra: Fix error pointer vs NULL return in nvkm_device_tegra_resource_addr() drm/xe: Default auto_link_downgrade status to false drm/xe/guc: Make creation of SLPC debugfs files conditional drm/i915/display: Add check for alloc_ordered_workqueue() and alloc_workqueue() drm/i915/dp_mst: Work around Thunderbolt sink disconnect after SINK_COUNT_ESI read drm/i915/ptl: Use everywhere the correct DDI port clock select mask drm/nouveau/kms: add support for GB20x drm/dp: add option to disable zero sized address only transactions. drm/nouveau: add support for GB20x drm/nouveau/gsp: add hal for fifo.chan.doorbell_handle drm/nouveau: add support for GB10x drm/nouveau/gf100-: track chan progress with non-WFI semaphore release drm/nouveau/nv50-: separate CHANNEL_GPFIFO handling out from CHANNEL_DMA drm/nouveau: add helper functions for allocating pinned/cpu-mapped bos drm/nouveau: add support for GH100 drm/nouveau: improve handling of 64-bit BARs drm/nouveau/gv100-: switch to volta semaphore methods drm/nouveau/gsp: support deeper page tables in COPY_SERVER_RESERVED_PDES drm/nouveau/gsp: init client VMMs with NV0080_CTRL_DMA_SET_PAGE_DIRECTORY drm/nouveau/gsp: fetch level shift and PDE from BAR2 VMM ...
2025-05-28drm/i915: Indicate which pipe lied about its interruptsVille Syrjälä
Indicate which pipe signalled the spurious DE PIPE interrupt. Might help with debugging a bit if we know where the interrupt is supposedly coming from. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250513092820.18715-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-05-27drm/i915: stop including display/intel_display_{core, limits}.h from i915_drv.hJani Nikula
Make i915->display pointer opaque to most of core i915 driver. Lots of places now need explicit include of intel_display_core.h, or a more specific header. With this dependency broken, changes in display should cause radically less recompilation of i915. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://lore.kernel.org/r/b381b59acb7e4f600e0282935a68aedf77768109.1747907216.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-27drm/i915/display: allocate struct intel_display dynamicallyJani Nikula
Allocate struct intel_display dynamically in intel_display_device_probe() and free in intel_display_device_remove(). v2: Remove duplicate intel_display_device_remove() on error path (Lucas) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/8cd526a177061cddf71db59bd0901bd1a24e77be.1747907216.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-26drm/i915/dp: Fix the enabling/disabling of audio SDP splittingImre Deak
Adjust the enabling/disabling steps of the DP audio SDP splitting according to a recent Bspec update. This moves the enabling to the audio codec enable sequence after the transcoder is enabled and disables SDP splitting explicitly during the audio disable sequence. Bspec requires waiting for a vblank event after the transcoder is enabled and before SDP splitting is enabled. There is no need for an explicit wait for this, since after the transcoder is enabled this vblank event is guaranteed to have happened via a flip done wait (see intel_atomic_commit_tail() -> drm_atomic_helper_wait_for_flip_done()). The bspec update is for LNL+ only, but the HW team clarified that this has been always the intended sequence on all platforms and bspec will be updated everywhere accordingly. The way SDP splitting was originally enabled matched the version of bspec at that time. Adding here the Fixes: line still, since this change fixes a FIFO underrun on PTL during output enabling when DSC is enabled. Bspec: 49283, 68943 Fixes: 8853750dbad8 ("drm/i915: Enable SDP split for DP2.0") Cc: Vinod Govindapillai <vinod.govindapillai@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250520142219.1688401-1-imre.deak@intel.com (cherry picked from commit 56764c845aa5be14cd53702fc9f2da23e25857de) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2025-05-26drm/i915: Disable updating of LUT values during vblankChaitanya Kumar Borah
Do not schedule vblank worker for LUT update if the registers are double buffered v2: Do not schedule the worker at all (Ville) Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-12-chaitanya.kumar.borah@intel.com
generated by cgit (git 2.34.1) at 2025-08-01 18:17:39 +0000