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path: root/drivers/gpu/drm
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2019-02-01drm/msm/dpu: Correct initialization of modifiersFritz Koenig
allow_fb_modifiers needs to be set before drm_universal_plane_init is called. Signed-off-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2019-02-01drm/msm/dpu: Initialize supported modifiersFritz Koenig
Pass list of supported modifiers to plane init. Signed-off-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2019-02-01drm/msm/dpu: Plane helper for modifiersFritz Koenig
Filter planes based on the supported modifiers Signed-off-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2019-02-01drm/msm/dpu: Use simple list for plane format initFritz Koenig
Simplify the initilization of a list of formats by passing the list in directly instead of copying it from one structure to another. Signed-off-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2019-02-01drm/msm/dpu: Remove unused format tables.Fritz Koenig
Signed-off-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2019-02-01drm/sun4i: tcon: Prepare and enable TCON channel 0 clock at initPaul Kocialkowski
When initializing clocks, a reference to the TCON channel 0 clock is obtained. However, the clock is never prepared and enabled later. Switching from simplefb to DRM actually disables the clock (that was usually configured by U-Boot) because of that. On the V3s, this results in a hang when writing to some mixer registers when switching over to DRM from simplefb. Fix this by preparing and enabling the clock when initializing other clocks. Waiting for sun4i_tcon_channel_enable to enable the clock is apparently too late and results in the same mixer register access hang. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190131132550.26355-1-paul.kocialkowski@bootlin.com
2019-02-01drm/bridge: dw-hdmi: add support for YUV420 outputNeil Armstrong
In order to support the HDMI2.0 YUV420 display modes, this patch adds support for the YUV420 TMDS Clock divided by 2 and the controller passthrough mode. YUV420 Synopsys PHY support will need some specific configuration table to support theses modes. This patch is based on work from Zheng Yang <zhengyang@rock-chips.com> in the Rockchip Linux 4.4 BSP at [1] [1] https://github.com/rockchip-linux/kernel/tree/release-4.4 Cc: Zheng Yang <zhengyang@rock-chips.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1549022873-40549-5-git-send-email-narmstrong@baylibre.com
2019-02-01drm/meson: add support for HDMI2.0 2160p modesNeil Armstrong
Now we support the TMDS Clock > 3.4GHz and support the SCDC Control operation in the DW-HDMI Controller, we can enable support for the HDMI2.0 3840x2160@60/50 RGB444 display modes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1549022873-40549-4-git-send-email-narmstrong@baylibre.com
2019-02-01drm/meson: add HDMI div40 TMDS modeNeil Armstrong
Add support for TMDS Clock > 3.4GHz for HDMI2.0 display modes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1549022873-40549-3-git-send-email-narmstrong@baylibre.com
2019-02-01drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling supportNeil Armstrong
Add support for SCDC Setup for TMDS Clock > 3.4GHz and enable TMDS Scrambling when supported or mandatory. This patch also adds an helper to setup the control bit to support the high TMDS Bit Period/TMDS Clock-Period Ratio as required with TMDS Clock > 3.4GHz for HDMI2.0 3840x2160@60/50 modes. These changes were based on work done by Huicong Xu <xhc@rock-chips.com> and Nickey Yang <nickey.yang@rock-chips.com> to support HDMI2.0 modes on the Rockchip 4.4 BSP kernel at [1] [1] https://github.com/rockchip-linux/kernel/tree/release-4.4 Cc: Nickey Yang <nickey.yang@rock-chips.com> Cc: Huicong Xu <xhc@rock-chips.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1549022873-40549-2-git-send-email-narmstrong@baylibre.com
2019-02-01Merge back earlier PM core material for v5.1.Rafael J. Wysocki
2019-02-01drm/amdgpu: clean up memory/GDS/GWS/OA alignment codeMarek Olšák
- move all adjustments into one place - specify GDS/GWS/OA alignment in basic units of the heaps - it looks like GDS alignment was 1 instead of 4 Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-01drm/amdgpu: fix the incorrect external id for raven seriesHuang Rui
This patch fixes the incorrect external id that kernel reports to user mode driver. Raven2's rev_id is starts from 0x8, so its external id (0x81) should start from rev_id + 0x79 (0x81 - 0x8). And Raven's rev_id should be 0x21 while rev_id == 1. Reported-by: Crystal Jin <Crystal.Jin@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-01drm/amdgpu: Implement doorbell self-ring for NBIO 7.4Jay Cornwall
Fixes doorbell reflection on Vega20. Change-Id: I0495139d160a9032dff5977289b1eec11c16f781 Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-01drm/amd/display: Fix fclk idle stateRoman Li
[Why] The earlier change 'Fix 6x4K displays' led to fclk value idling at higher DPM level. [How] Apply the fix only to respective multi-display configuration. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-01Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into ↵Dave Airlie
drm-next This pull includes the new Arm "komeda" DRM driver. It is currently hosted in the same repo as the other "mali-dp" driver because it is the next iteration of the IP. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Liviu Dudau <Liviu.Dudau@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190131173600.GN25147@e110455-lin.cambridge.arm.com
2019-02-01Merge tag 'drm-intel-next-2019-01-24' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next - Track all runtime-PM wakerefs and other rpm improvements (Chris) - Fix ILK-IVB primary plane enable delays (Juha-Pekka) - Differentiate between gtt->mutex and ppgtt->mutex (Chris) - Prevent concurrent GGTT update and use on Braswell (Chris) - Fix CNL macros for DDI vswing (Aditya) - Fix static code analysis warning (RK) - Only dump GPU state on set-wedged if interesting (Chris) - Port F detection improvements (Imre) - userptr mutex lock fixes (Chris) - Fix on MST allocation by propagating error value at compute_config (Lyude) - Serialise concurrent calls to set_wedge (Chris) - Unify reset functionality into i915_reset.c (Chris) - Switch to kernel fixed size types (Jani) - Limit the for_each_set_bit to the valid range (Chris) - Fix wakeref cooie handling (Tvrtko) - IRQs handling improvements (Chris) - Selftests improvements (Chris) - Remove superfluous PANEL_POWER_OFF macro (Jani) - Global seqno fix (Chris) - DSI fixes (Hans) - Refactor out intel_context_init() (Chris) - Show all active engines on hangcheck (Chris) - PSR2 fixes and improvements (Jose) - Do a posting read after irq install on Ice Lake (Daniele) - Add few more device IDs for Ice Lake (Rodrigo) - Mark up priority boost on preemption (Chris) - Add color management LUT validation helper (Matt) - Split out intel_crt_present to platform specific setup (Jani) - LVDS and TV clean up and improvements (Jani) - Simplify CRT VBT check for per-VLV/DDI (Jani) - De-inline intel_context_init() (Chris) - Backlight fixes (Maarten) - Enable fastset for non-boot modesets (Maarten) - Make HW readout mark CRTC scaler as in use (Maarten) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190128181000.GA5284@intel.com
2019-02-01Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie
into drm-next New stuff for 5.1. amdgpu: - DC bandwidth formula updates - Support for DCC on scanout surfaces - Support for multiple IH rings on soc15 asics - Fix xgmi locking - Add sysfs interface to get pcie usage stats - Simplify DC i2c/aux code - Initial support for BACO on vega10/20 - New runtime SMU feature debug interface - Expand existing sysfs power interfaces to new clock domains - Handle kexec properly - Simplify IH programming - Rework doorbell handling across asics - Drop old CI DPM implementation - DC page flipping fixes - Misc SR-IOV fixes amdkfd: - Simplify the interfaces between amdkfd and amdgpu ttm: - Add a callback to notify the driver when the lru changes sched: - Refactor mirror list handling - Rework hw fence processing Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190125231517.26268-1-alexander.deucher@amd.com
2019-01-31drm/i915/cfl: Adding another PCI Device ID.Rodrigo Vivi
While cross checking PCI IDs from Intel Media SDK and kernel Dmitry noticed this gap. So we checked the spec and this new ID had been recently added. v2: Adding new H_GT1 entry to i915_pci.c (Jose) Reported-by: Dmitry Rogozhkin<dmitry.v.rogozhkin@intel.com> Cc: Dmitry Rogozhkin<dmitry.v.rogozhkin@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190201235049.27206-1-rodrigo.vivi@intel.com
2019-02-01Merge tag 'gvt-next-2019-02-01' of https://github.com/intel/gvt-linux into ↵Rodrigo Vivi
drm-intel-next-queued gvt-next-2019-02-01 - new VFIO EDID region support (Henry) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190201061523.GE5588@zhen-hp.sh.intel.com
2019-02-01drm/i915: Enable fastboot by default on VLV and CHVHans de Goede
We really want to have fastboot enabled by default to avoid an ugly modeset during boot. Currently we are enabling fastboot by default on gen9+ (Skylake and newer). The intention is to enable it on older generations after it has seen more testing on gen9+. VLV and CHV devices are still being sold in stores today, as such it is desirable to also enable fastboot by default on these now. I've extensively tested fastboot=1 support on over 50 different Bay- and Cherry-Trail devices. Testing DSI and eDP panels as well as HDMI output (and even DP over Type-C on one device). All 50 devices work fine with fastboot=1. On 2 devices their DSI panel turns black as soon as the i915 driver loads when fastboot=0, so having fastboot enabled is required for these 2 to work properly (for lack of a better fix). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190129142237.8684-1-hdegoede@redhat.com
2019-02-01drm/i915/icl: restore WaEnableFloatBlendOptimizationTalha Nassar
Enables blend optimization for floating point RTs This restores the workaround that was reverted in c358514ba8da ("Revert "drm/i915/icl: WaEnableFloatBlendOptimization""). The revert was due to the register write seemingly not sticking, but the HW team has confirmed that this is because the register is WO and that the workaround is indeed required. Here the wa is added with a mask of 0 since the register is WO. References: https://hsdes.intel.com/resource/1408134172 References: https://bugs.freedesktop.org/show_bug.cgi?id=107338 Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Talha Nassar <talha.nassar@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/1548983324-15344-4-git-send-email-talha.nassar@intel.com
2019-02-01drm/i915: Save some lines of source code in workaroundsTvrtko Ursulin
No functional or code size change - just notice we can compact the source by re-using a single helper for adding workarounds. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/1548983324-15344-3-git-send-email-talha.nassar@intel.com
2019-02-01drm/i915: Move workaround infrastructure code upTvrtko Ursulin
Top comment in intel_workarounds.c says common code should come first so lets respect that. Also, by moving the common code together opportunities to reduce duplication will become more obvious. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/1548983324-15344-2-git-send-email-talha.nassar@intel.com
2019-01-31drm/i915/icl: Work around broken VBTs for port F detectionImre Deak
VBT may include incorrect information about the presence of port F. Work around this on SKUs where we know the port is not present. v2: - Fix IS_ICL_WITH_PORT_F, so it's useable from any context. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108915 Cc: Mika Kahola <mika.kahola@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181220155211.31456-1-imre.deak@intel.com
2019-01-31drm/i915/icl: Add TypeC ports only if VBT is presentImre Deak
We can't safely probe Type C ports, whether they are a legacy or a USB/Thunderbolt DP Alternate Type C port. This would require performing the TypeC connect sequence - as described by the specification - but that may have unwanted side-effects. These side-effects include at least - without completeness - timeouts during AUX power well enabling and subsequent PLL enabling errors. To safely identify these ports we really need VBT, which has the proper flag for this (ddi_vbt_port_info::supports_typec_usb, supports_tbt). Based on the above disable Type C ports if we can't load VBT for some reason. v2: - Notice that we disable TypeC ports completely and simplify accordingly (Jose). - Add code comment explaining why we disabled the ports. (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Jose Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190128114242.28666-1-imre.deak@intel.com
2019-01-31drm/i915: Pick the first unused PLL once againVille Syrjälä
commit 5b0bd14dcc6b ("drm/i915/icl: keep track of unused pll while looping") inadvertently (I presume) changed the code to pick the last unused dpll rather than the first unused one like we did before. While there should most likely be no harm in changing the order let's change back just to avoid a change in the behaviour. At least it might reduce the confusion when staring at logs (took me a while to figure out why DPLL1 being picked over DPLL0 when the latter was most definitely available). Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190130181359.20693-1-ville.syrjala@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-01-31drm/i915: Don't use the second dbuf slice on iclVille Syrjälä
The code managing the dbuf slices is borked and needs some real work to fix. In the meantime let's just stop using the second slice. v2: Drop the change to intel_enabled_dbuf_slices_num() (Mahesh) Cc: Mahesh Kumar <mahesh1.sh.kumar@gmail.com> Reviewed-by: Imre Deak <imre.deak@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190130155110.12918-1-ville.syrjala@linux.intel.com Reviewed-by: Mahesh Kumar <mahesh1.sh.kumar@gmail.com>
2019-01-31drm/i915/gvt: add VFIO EDID regionHang Yuan
Implement VFIO EDID region for vgpu. Support EDID blob update and notify guest on link state change via hotplug event. v3: move struct edid_region to kvmgt.c <zhenyu> v2: add EDID sanity check and size update <zhenyu> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Hang Yuan <hang.yuan@linux.intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2019-01-31drm/i915/gvt: add hotplug emulationHang Yuan
Add function to emulate hotplug interrupt for SKL/KBL platforms Signed-off-by: Hang Yuan <hang.yuan@linux.intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2019-01-31drm/i915/gvt: add functions to get default resolutionHang Yuan
These functions will get default resolution according to vgpu type. Signed-off-by: Hang Yuan <hang.yuan@linux.intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2019-01-30drm/i915: Apply LUT validation checks to platforms more accurately (v3)Matt Roper
Use of the new DRM_COLOR_LUT_NON_DECREASING test was a bit over-zealous; it doesn't actually need to be applied to the degamma on "bdw-style" platforms. Likewise, we overlooked the fact that CHV should have that test applied to the gamma LUT as well as the degamma LUT. Rather than adding more complicated platform checking to intel_color_check(), let's just store the appropriate set of LUT validation flags for each platform in the intel_device_info structure. v2: - Shuffle around LUT size tests so that the hardware-specific tests won't be applied to legacy gamma tables. (Ville) - Add a debug message so that it will be easier to understand why an atomic transaction involving incorrectly-sized LUT's got rejected by the driver. v3: - Switch size_t's to int's. (Ville) Fixes: 85e2d61e4976 ("drm/i915: Validate userspace-provided color management LUT's (v4)") References: https://lists.freedesktop.org/archives/intel-gfx/2019-January/187634.html Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190130181022.4291-1-matthew.d.roper@intel.com
2019-01-30drm/i915: Force background color to black for gen9+ (v2)Matt Roper
We don't yet allow userspace to control the CRTC background color, but we should manually program the color to black to ensure the BIOS didn't leave us with some other color. We should also set the pipe gamma and pipe CSC bits so that the background color goes through the same color management transformations that a plane with black pixels would. v2: Rename register to SKL_BOTTOM_COLOR to more closely follow bspec naming. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190130185122.10322-2-matthew.d.roper@intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2019-01-30drm/dp/mst: Provide better debugs for NAK repliesVille Syrjälä
Decode the NAK reply fields to make it easier to parse the logs. v2: s/STR/DP_STR/ to avoid conflict with some header stuff (0day) Use drm_dp_mst_req_type_str() more (DK) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190122200301.18633-2-ville.syrjala@linux.intel.com
2019-01-30drm/dp/mst: Provide defines for ACK vs. NAK reply typeVille Syrjälä
Make the code a bit easier to read by providing symbolic names for the reply_type (ACK vs. NAK). Also clean up some brace stuff while at it. v2: s/DP_REPLY/DP_SIDEBAND_REPLY/ (DK) Fix some checkpatch issues Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190122200301.18633-1-ville.syrjala@linux.intel.com
2019-01-30drm/amdgpu: Transfer fences to dmabuf importerChris Wilson
amdgpu only uses shared-fences internally, but dmabuf importers rely on implicit write hazard tracking via the reservation_object.fence_excl. For example, the importer use the write hazard for timing a page flip to only occur after the exporter has finished flushing its write into the surface. As such, on exporting a dmabuf, we must either flush all outstanding fences (for we do not know which are writes and should have been exclusive) or alternatively create a new exclusive fence that is the composite of all the existing shared fences, and so will only be signaled when all earlier fences are signaled (ensuring that we can not be signaled before the completion of any earlier write). v2: reservation_object is already locked by amdgpu_bo_reserve() v3: Replace looping with get_fences_rcu and special case the promotion of a single shared fence directly to an exclusive fence, bypassing the fence array. v4: Drop the fence array ref after assigning to reservation_object Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107341 Testcase: igt/amd_prime/amd-to-i915 References: 8e94a46c1770 ("drm/amdgpu: Attach exclusive fence to prime exported bo's. (v5)") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Reviewed-by: "Christian König" <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-30drm/doc: fix VRR_ENABLED casingDaniel Vetter
Yes it's inconsitent with vrr_capable, but this is the actual uapi as exercise by igt. Fixes: ab7a664f7a2d ("drm: Document variable refresh properties") Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Pekka Paalanen <pekka.paalanen@collabora.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190130163006.28945-3-daniel.vetter@ffwll.ch
2019-01-30drm/savage: mark expected switch fall-throughsGustavo A. R. Silva
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/gpu/drm/savage/savage_state.c:301:8: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/gpu/drm/savage/savage_state.c:438:8: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/gpu/drm/savage/savage_state.c:559:8: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/gpu/drm/savage/savage_state.c:697:8: warning: this statement may fall through [-Wimplicit-fallthrough=] Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enabling -Wimplicit-fallthrough. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190129202005.GA25789@embeddedor
2019-01-30drm/via: mark expected switch fall-throughsGustavo A. R. Silva
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/gpu/drm/via/via_dmablit.c:179:3: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/gpu/drm/via/via_dmablit.c:185:3: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/gpu/drm/via/via_dmablit.c:187:3: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/gpu/drm/via/via_dmablit.c:195:3: warning: this statement may fall through [-Wimplicit-fallthrough=] Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enabling -Wimplicit-fallthrough. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190129201742.GA25660@embeddedor
2019-01-30drm/komeda: Off by one in komeda_fb_get_pixel_addr()Dan Carpenter
The > should be >= to avoid an off by one bug. Fixes: c46c24bb6b11 ("drm/komeda: Add komeda_framebuffer") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
2019-01-30drm/qxl: use ttm_ttGerd Hoffmann
qxl device will not dma, so we don't need ttm_dma_tt. Go use ttm_tt instead, to avoid wasting resources (swiotlb bounce buffers for example). Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190129082541.1392-1-kraxel@redhat.com
2019-01-29drm/i915: Update DRIVER_DATE to 20190129Rodrigo Vivi
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2019-01-30drm/i915: Use IS_GEN9_LP() for the linetime w/a checkVille Syrjälä
IS_GLK||IS_BXT == IS_GEN9_LP Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181221171436.8218-10-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
2019-01-30drm/i915: Drop the pointless linetime==0 checkVille Syrjälä
0*whatever==0 so this check is pointless. Remove it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181221171436.8218-9-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
2019-01-30drm/i915: Drop the definite article in front of SAGVVille Syrjälä
The spec doesn't use a definite article in front of SAGV. The rules regarding articles and initialisms are super fuzzy, but at least to my ears it sounds much more natural to not have the article. Perhaps because I tend to pronounce it as "sag-vee" instead of spelling out the letters one at a time. Actually I might still prefer to leave out the article if I did spell them out. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181221171436.8218-8-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2019-01-30drm/i915: Pass dev_priv to skl_needs_memory_bw_wa()Ville Syrjälä
skl_needs_memory_bw_wa() doesn't look at the passed in state at all. Possibly it should, but for now let's make life simpler by just passing in dev_priv. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181221171436.8218-7-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
2019-01-30drm/i915: Account for minimum ddb allocation restrictionsVille Syrjälä
On icl+ bspec tells us to calculate a separate minimum ddb allocation from the blocks watermark. Both have to be checked against the actual ddb allocation, but since we do things the other way around we'll just calculat the minimum acceptable ddb allocation by taking the maximum of the two values. We'll also replace the memcmp() with a full trawl over the the watermarks so that it'll ignore the min_ddb_alloc because we can't directly read that out from the hw. I suppose we could reconstruct it from the other values, but I was too lazy to do that now. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181221171436.8218-6-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
2019-01-30drm/i915: Fix > vs >= mismatch in watermark/ddb calculationsVille Syrjälä
Bspec says we have to reject the watermark if it's >= the ddb allocation. Fix the code to reject the == case as it should. For transition watermarks we can just use >=, for the rest we'll do +1 when calculating the minimum ddb allocation size. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181221171436.8218-5-ville.syrjala@linux.intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
2019-01-30drm/i915: Fix bits vs. bytes mixup in dbuf block size computationVille Syrjälä
The spec used to say "8bpp" which someone took to mean 8 bytes per pixel when in fact it was supposed to be 8 bits per pixel. The spec has been updated to make it more clear now. Fix the code to match. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181221171436.8218-4-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
2019-01-30drm/i915: Reinstate an early latency==0 check for skl+Ville Syrjälä
I thought we could remove all the early latency==0 checks and rely on skl_wm_method{1,2}() checking for it. But skl_compute_plane_wm() applies a bunch of workarounds to bump up the latency before calling those guys so clearly it won't end up doing the right thing. Also not sure if the calculations based on the method1/2 results are safe agaisnt overflows so it might not work all that well in any case. Let's put the early check back. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181221171436.8218-3-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
generated by cgit (git 2.34.1) at 2025-09-18 21:34:38 +0000