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path: root/drivers/gpu/drm
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2017-10-21drm/amd/display: option to maximize lb usageTony Cheng
experimental change for testing if max line buffer result in better stutter efficiency for 1080p, LB can hold up to 9 line at 10bpcc, potentially add 10 line time of latency hiding. Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: add option to disable DCC for DCC 128b requestTony Cheng
1. reverts commit e67f51012740 ("dc: temp disable DCC on high res.") - default still DCC enabled 2. add debug options to decide how DCC is disabled - disable DCC - disable DCC if DCC requires 128b (aka. half) request -- observed compressed data corruption result in screen corruption in full (256b) request while half (128b) would cause DCN to hang, result in DF hang Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: enable optional pipe split for single displayTony Cheng
also refactor debug option. now pipe_split_policy are dynamic = no hack around dcn_calcs. will split based on HW recommendation avoid = avoid split if we can support the config with higher voltage avoid_multi_display = allow split with single display output. force_single_disp_pipe_split force single display to pipe split to improve stutter efficiency by using DET buffers using 2 HUBP. Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: temp disable DCC on high res.Charlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Fix MST daisy chain SST not light upJerry Zuo
In SST daisy chain scenario, edid is getting read in mst hotplug routine. It is getting conflict with drm send_enum_path_resources kernel thread in terms of i2c bus which is getting locked up in such case. Have edid being read in get_mode hook, instead of in hotplug routine. Signed-off-by: Jerry Zuo <Jerry.Zuo@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Only reset top pipe back end.Yongqiang Sun
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Early return when turn off a plane.Yongqiang Sun
In case of two monitor connected and turn off one of the monitors, OTG0 is locked after graphic plane off due to redundant programming front end regs. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Program stream's csc matrix instead of using defaultSivapiriyanKumarasamy
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: update link type to mst before topology discoveryWenjing Liu
[Description] link type is not updated before mst topology discovery. This causes issue when branch device response to link address after before the start topology discovery event finishes. [Solution] update link type to mst before topology discovery Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Use active + border for bw validationEric Yang
When doing SLS, KMD gives us clipped v_addressable with border. This results in bw validation failure. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Fixed incorrect return value for validatonYongqiang Sun
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: screen flickers when connected to ext monitor in cloneHersen Wu
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: version 3.1.02Tony Cheng
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Fixed validation return wrong result.Yongqiang Sun
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: add hubp/dpp pg debug keyCharlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: make sure BL off to mainlink off has enough timeCharlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: fix ASSERT() caused by missing registers.Ken Chalmers
Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: edp backlight regression fixYue Hin Lau
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: moving backlight registers to hwsequencerYue Hin Lau
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: update blending mode and set output denormEric Bernstein
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: add back removed hack for mpcc addEric Yang
A previous changed removed the hack to match mpcc_idd with mi instance. This causes pstate hang on resume from hibernate for yet unknown reason. Add the hack back for now to work around the issue. More debugging required in init_hw to root cause the hang. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: set cp25201 to use TPS4Wenjing Liu
[Description] hbr2 compliance eye output is unstable (toggling on and off) with debugger break. This caueses intermittent PHY automation failure. Need to look into the root cause later Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: removing remaining register definitions work aroundYue Hin Lau
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: power_down_Hw need signal type to turnoff backlightAndrew Jiang
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: make tile changing run at ISRShihChen Chen
Signed-off-by: ShihChen Chen <ShihChen.Chen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Refactor dc_update_planes_and_stream.Bhawanpreet Lakha
Split update_planes_and_stream_state (split Software and Hardware programming) as the state is already build, so we only need to program the hardware Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Fix NULL pointer on MST chained modeJerry Zuo
Prevent NULL pointer on new_stream being added to ctx when added MST connectors cannot be found in existing crtc_state in the chained mode Signed-off-by: Jerry Zuo <Jerry.Zuo@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Exclude MST from fake sinkJerry Zuo
Needs effort to take care of the fake sink scenario in downstream daisy chain device. Exclude MST from fake sink feature for now. Signed-off-by: Jerry Zuo <Jerry.Zuo@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: fixing register includesYue Hin Lau
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Match actual state during S3 resume.Leo (Sunpeng) Li
During system suspend, we: 1. Cache a duplicate of the current DRM atomic state, which calls hooks to duplicate our internal states. 2. Call hooks to disable all functionalities. 3. System suspended. During resume, we attempt to restore the cached state. However, our interal states are now stale, since step 1 was done before step 2. i.e. our cached state does not reflect the disabled nature of things. This change resolves that by destroying all relevant states to reflect the actual state during resume. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: update mpc add/remove functionsEric Bernstein
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: fix multi-display on CZRoman Li
- fixed wrong index in dce110_validate_surface_sets() - formatted for better readability Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> igned-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Refactor dcn10_dpp_cm_helper to dcn10_cm_commonYue Hin Lau
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Don't report fake sink as connectedHarry Wentland
This was missed in the previous fake sink change. The fake sink allows us to enable a pipe with a disconnected display. We shouldn't report it as connected. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: To prevent detecting new sink from spurious HPDMartin Tsai
Signed-off-by: Martin Tsai <martin.tsai@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Add FBC on/off to front-end programmingRoman Li
- Fixing text mode for cases when VT-switch doesn't result in timing change Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: fix usb-c dongle regressionEric Yang
A previous change moved link_disconnect_sink after dpcd read, this causes the sink count to be overwritten which in turn causes another detection to be triggered in the short pulse handler, which brings down the display. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Force always scale chroma, set always_scaled to falseAndrew Jiang
This allows us to not always have scaling on, which causes issues with validation and causes the text to blur slightly. Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Driver message to SMU to indicate display offHersen Wu
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-20drm/i915/cnl: Map VBT DDC Pin to BSpec DDC Pin.Rodrigo Vivi
Starting on CNL we now need to map VBT DDC Pin to BSPec DDC Pin values. Not a direct translation anymore. According to VBT Block 2 (General Bytes Definition) DDC Bus +----------+-----------+--------------------+ | DDI Type | VBT Value | Bspec Mapped Value | +----------+-----------+--------------------+ | DDI-B | 0x1 | 0x1 | | DDI-C | 0x2 | 0x2 | | DDI-D | 0x3 | 0x4 | | DDI-F | 0x4 | 0x3 | +----------+-----------+--------------------+ v2: Move defines to a better place. This is actually CNL_PCH not CNL only. v3: Accepting Ville's suggestions: enums and array to to make this future proof. v4: Protect the array access as Ville suggested. Also accepting all Jani's suggestions: - use already defined gmbus pin definitions. - use map_ddc_pin for disambiguation. - Add /* sic */ comment on inverted values so people can easily see it it nos a mistake we have the map 3 -> 4 and 4 -> 3 :/ Cc: Jani Nikula <jani.nikula@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171020172641.16029-1-rodrigo.vivi@intel.com
2017-10-20drm/i915: Let's use more enum intel_dpll_id pll_id.Rodrigo Vivi
No functional change expected. Just let's use this enum when possible and also same standard pll_id name so we can rework gen9+ port clock later. Cc: Mika Kahola <mika.kahola@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171018195407.8618-1-rodrigo.vivi@intel.com
2017-10-21drm: Reorganize drm_pending_event to support future event types [v2]Keith Packard
Place drm_event_vblank in a new union that includes that and a bare drm_event structure. This will allow new members of that union to be added in the future without changing code related to the existing vbl event type. Assignments to the crtc_id field are now done when the event is allocated, rather than when delievered. This way, delivery doesn't need to have the crtc ID available. v2: * Remove 'dev' argument from create_vblank_event It wasn't being used anyways, and if we need it in the future, we can always get it from crtc->dev. * Check for MODESETTING before looking for crtc in queue_vblank_event UMS drivers will oops if we try to get a crtc, so make sure we're modesetting before we try to find a crtc_id to fill into the event. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit dc695b85fde88eca3ef3b03fcd82f15b6bc6e462)
2017-10-21drm: Widen vblank count to 64-bits [v3]Keith Packard
This modifies the datatypes used by the vblank code to provide 64 bits of vblank count. The driver interfaces have been left using 32 bits of vblank count; all of the code necessary to widen that value for the user API was already included to handle devices returning fewer than 32-bits. This will provide the necessary datatypes for the Vulkan API. v2: * Re-write wait_vblank ioctl to ABSOLUTE sequence When an application uses the WAIT_VBLANK ioctl with RELATIVE or NEXTONMISS bits set, the target vblank interval is updated within the kernel. We need to write that target back to the ioctl buffer and update the flags bits so that if the wait is interrupted by a signal, when it is re-started, it will target precisely the same vblank count as before. * Leave driver API with 32-bit vblank count v3: * Rebase on top of Arnd Bergmann's patch which had the switch to ktime_t parts. [airlied: fix conflict with Ville vblank change]. Suggested-by: Michel Dänzer <michel@daenzer.net> Suggested-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit 2affbc16983e4fc90960bc7f70e7615f4228199b)
2017-10-20drm/amdgpu:fix wb_clearMonk Liu
Properly shift the index when clearing so we clear the right bit Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-20drm/amdgpu:fix vf_error_putMonk Liu
1,it should not work on non-SR-IOV case 2,the NO_VBIOS error is incorrect, should handle it under detect_sriov_bios. 3,wrap the whole detect_sriov_bios with sriov check Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-20drm/amdgpu/sriov:now must reinit pspMonk Liu
otherwise after VF FLR the KIQ cannot work Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-20drm/amdgpu: merge bios post checking functionspding
Merge the post checking functions to avoid confusion and take virtualization into account in all cases. Signed-off-by: pding <Pixel.Ding@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-20drm/tegra: hdmi: Add cec-notifier supportHans Verkuil
In order to support CEC the HDMI driver has to inform the CEC driver whenever the physical address changes. So when the EDID is read the CEC driver has to be informed and whenever the hotplug detect goes away. This is done through the cec-notifier framework. The link between the HDMI driver and the CEC driver is done through the hdmi-phandle property in the tegra-cec node in the device tree. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-20drm/tegra: dc: Perform a complete reset sequenceThierry Reding
In order for the reset to be applied properly, the module clock must be enabled during the assertion. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-20drm/tegra: dc: Make sure to set the module clock rateThierry Reding
When applying the PLL changes from the computed state object, make sure to set the rate of the display controller module clock. Failing to do so can yield to a situation where the parent will be set to the proper pixel clock, but the module clock will be divided down to the rate that is happened to be set to before the parent rate change. Signed-off-by: Thierry Reding <treding@nvidia.com>
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