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path: root/drivers/gpu/drm
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2021-12-07drm/msm/dp: displayPort driver need algorithm rationalJackie Liu
Let's select RATIONAL with dp driver. avoid like: [...] x86_64-linux-gnu-ld: drivers/gpu/drm/msm/dp/dp_catalog.o: in function `dp_catalog_ctrl_config_msa': dp_catalog.c:(.text+0x57e): undefined reference to `rational_best_approximation' Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support") Reported-by: kernelbot <kernel-bot@kylinos.cn> Signed-off-by: Jackie Liu <liuyun01@kylinos.cn> Link: https://lore.kernel.org/r/20211110070950.3355597-2-liu.yun@linux.dev Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-12-07drm/msm/dpu: remove node from list before freeing the nodeYang Li
fix the following smatch warning: drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:1675 dpu_plane_init() warn: '&pdpu->mplane_list' not removed from list Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1638502612-113708-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-12-07drm/msm/dp: Re-order dp_audio_put in deinit_sub_modulesSean Paul
Audio is initialized last, it should be de-initialized first to match the order in dp_init_sub_modules(). Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-12-sean@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-12-sean@poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-12-sean@poorly.run #v3 Changes in v2: -None Changes in v3: -None Changes in v4: -None Link: https://lore.kernel.org/r/20211105030434.2828845-12-sean@poorly.run Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-12-07drm/msm/dpu: Remove encoder->enable() hackSean Paul
encoder->commit() was being misused because there were some global resources which needed to be tweaked in encoder->enable() which were not accessible in dpu_encoder.c. That is no longer true and the redirect serves no purpose any longer. So remove the indirection. Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-11-sean@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-11-sean@poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-11-sean@poorly.run #v3 Changes in v2: -None Changes in v3: -None Changes in v4: -None Link: https://lore.kernel.org/r/20211105030434.2828845-11-sean@poorly.run Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-12-07drm/msm/dpu: Remove useless checks in dpu_encoderSean Paul
A couple more useless checks to remove in dpu_encoder. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-10-sean@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-10-sean@poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-10-sean@poorly.run #v3 Changes in v2: -None Changes in v3: -None Changes in v4: -None Link: https://lore.kernel.org/r/20211105030434.2828845-10-sean@poorly.run Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-12-07drm/msm/dpu_kms: Re-order dpu includesSean Paul
Make includes alphabetical in dpu_kms.c Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-9-sean@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-9-sean@poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-9-sean@poorly.run #v3 Changes in v2: -None Changes in v3: -None Changes in v4: -None Link: https://lore.kernel.org/r/20211105030434.2828845-9-sean@poorly.run Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-12-07drm/msm/gpu: Don't allow zero fence_idRob Clark
Elsewhere we treat zero as "no fence" and __msm_gem_submit_destroy() skips removal from fence_idr. We could alternately change this to use negative values for "no fence" but I think it is more clear to not allow zero as a valid fence_id. Signed-off-by: Rob Clark <robdclark@chromium.org> Fixes: a61acbbe9cf8 ("drm/msm: Track "seqno" fences by idr") Link: https://lore.kernel.org/r/20211129182344.292609-1-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-12-07drm/msm/dp: Add "qcom, sc7280-dp" to support display port.Kuogee Hsieh
Changes in v2: -- move "qcom,sc7280-dp" before "qcom,sc7280-edp" Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1638809846-31950-1-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-12-07drm/amdgpu: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmiClaudio Suarez
Once EDID is parsed, the monitor HDMI support information is available through drm_display_info.is_hdmi. The amdgpu driver still calls drm_detect_hdmi_monitor() to retrieve the same information, which is less efficient. Change to drm_display_info.is_hdmi This is a TODO task in Documentation/gpu/todo.rst Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Claudio Suarez <cssk@net-c.es> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amdgpu: use drm_edid_get_monitor_name() instead of duplicating the codeClaudio Suarez
Use drm_edid_get_monitor_name() instead of duplicating the code that parses the EDID in dm_helpers_parse_edid_caps() Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Claudio Suarez <cssk@net-c.es> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amdgpu: update drm_display_info correctly when the edid is readClaudio Suarez
drm_display_info is updated by drm_get_edid() or drm_connector_update_edid_property(). In the amdgpu driver it is almost always updated when the edid is read in amdgpu_connector_get_edid(), but not always. Change amdgpu_connector_get_edid() and amdgpu_connector_free_edid() to keep drm_display_info updated. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Claudio Suarez <cssk@net-c.es> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Fix out of bounds access on DNC31 stream encoder regsNicholas Kazlauskas
[Why] During dcn31_stream_encoder_create, if PHYC/D get remapped to F/G on B0 then we'll index 5 or 6 into a array of length 5 - leading to an access violation on some configs during device creation. [How] Software won't be touching PHYF/PHYG directly, so just extend the array to cover all possible engine IDs. Even if it does by try to access one of these registers by accident the offset will be 0 and we'll get a warning during the access. Fixes: 2fe9a0e1173f ("drm/amd/display: Fix DCN3 B0 DP Alt Mapping") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amdgpu: skip umc ras error count harvestStanley.Yang
remove in recovery stat check, skip umc ras err cnt harvest in amdgpu_ras_log_on_err_counter Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amdgpu: free vkms_output after useFlora Cui
Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Leslie Shi <Yuliang.Shi@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amdgpu: drop the critial WARN_ON in amdgpu_vkmsFlora Cui
Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Leslie Shi <Yuliang.Shi@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Reduce stack usageAric Cyr
Reduce stack usage by moving an unnecessary structure copy to a pointer. Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Query DMCUB for dp alt statusNicholas Kazlauskas
[Why] To avoid hanging RDPCSPIPE when INTERCEPTB isn't set. DMCUB owns control of that bit so DMCUB should manage returning the information driver needs for link encoder control. [How] Add a new DMCUB command to return dp alt disable and dp4 information. Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: [FW Promotion] Release 0.0.96Anthony Koo
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: add a debug option to force dp2 lt fallback methodWenjing Liu
[why] A debug option is needed to temporarily force dp2 new link training fallback method for debugging purpose. Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Rename a struct field to describe a cea component betterOliver Logush
[why] Need to fix the code so it does not use reserved keywords [how] Change the total_length member of the cea struct Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Oliver Logush <oliver.logush@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Adding dpia debug bits for hpd delayMeenakshikumar Somasundaram
[Why] Need to have dpia debug bits for configuring hpd delay. [How] Added hpd_delay_in_ms variable in dpia_debug_options. Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: meenakshikumar somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Move link_enc init logic to DCJude Shih
[Why] We shouldn't be accessing res_pool funcs from DM level, therefore, we should create API and let the flow be done in DC level. [How] We create new interface dp_get_link_enc to access and get the correct link_enc Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Jude Shih <shenshih@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Fix bug in debugfs crc_win_update entryWayne Lin
[Why] crc_rd_wrk shouldn't be null in crc_win_update_set(). Current programming logic is inconsistent in crc_win_update_set(). [How] Initially, return if crc_rd_wrk is NULL. Later on, we can use member of crc_rd_wrk safely. Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Fixes: 9a65df193108 ("drm/amd/display: Use PSP TA to read out crc") Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: prevent reading unitialized linksMikita Lipski
[why/how] The function can be called on boot or after suspend when links are not initialized, to prevent it guard it with NULL pointer check Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Added Check For dc->res_poolJarif Aftab
[WHY] -To ensure dc->res_pool has been initialized [HOW] -Check if dc->res_pool is true in the if statement Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Jarif Aftab <jaraftab@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Prevent PSR disable/reenable in HPD IRQWyatt Wood
[Why] When HPD IRQ occurs, it triggers a PSR disable and reenable directly through dc layer. Since it does not pass through the power layer, the layer that tracks whether PSR is enabled or disabled and which masks are set, this layer is now out of sync with the real PSR state in FW. Theoretically PSR can be enabled during hw programming sequences or any other situation where we must disable PSR. [How] Check if PSR is enabled before doing PSR disable/reenable. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Fix DPIA outbox timeout after S3/S4/resetNicholas Kazlauskas
[Why] The HW interrupt gets disabled after S3/S4/reset so we don't receive notifications for HPD or AUX from DMUB - leading to timeout and black screen with (or without) DPIA links connected. [How] Re-enable the interrupt after S3/S4/reset like we do for the other DC interrupts. Guard both instances of the outbox interrupt enable or we'll hang during restore on ASIC that don't support it. Fixes: 524a0ba6fab955 ("drm/amd/display: Fix DPIA outbox timeout after GPU reset") Reviewed-by: Jude Shih <Jude.Shih@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Add W/A for PHY tests with certain LTTPRGeorge Shen
[Why] Certain LTTPR require output VS/PE to be explicitly set during PHY test automation. [How] Add vendor-specific sequence to set LTTPR output VS/PE. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: George Shen <George.Shen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amd/display: Apply LTTPR workarounds to non-transparent modeGeorge Shen
[Why] Some of the vendor-specific workarounds added for transparent mode also need to be applied to non-transparent mode in order to succeed link training consistently. [How] Remove transparent mode check for the required workarounds. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: George Shen <George.Shen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amdgpu: only skip get ecc info for aldebaranStanley.Yang
skip get ecc info for aldebarn through check ip version do not affect other asic type Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/amdkfd: Correct the value of the no_atomic_fw_version variablechen gong
145: navi10 IP_VERSION(10, 1, 10) navi12 IP_VERSION(10, 1, 2) navi14 IP_VERSION(10, 1, 1) 92: sienna_cichlid IP_VERSION(10, 3, 0) navy_flounder IP_VERSION(10, 3, 2) vangogh IP_VERSION(10, 3, 1) dimgrey_cavefish IP_VERSION(10, 3, 4) beige_goby IP_VERSION(10, 3, 5) yellow_carp IP_VERSION(10, 3, 3) Signed-off-by: chen gong <curry.gong@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Graham Sider <Graham.Sider@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-07drm/bridge: parade-ps8640: Add backpointer to drm_device in drm_dp_auxDouglas Anderson
When we added the support for the AUX channel in commit 13afcdd7277e ("drm/bridge: parade-ps8640: Add support for AUX channel") we forgot to set "drm_dev" to avoid the warning splat at the beginning of drm_dp_aux_register(). Since everything was working I guess I never noticed the splat when testing against mainline. In any case, it's easy to fix. This is basically just like commit 6cba3fe43341 ("drm/dp: Add backpointer to drm_device in drm_dp_aux") but just for the parade-ps8640. Fixes: 13afcdd7277e ("drm/bridge: parade-ps8640: Add support for AUX channel") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20211206162907.1.I1f5d1eba741e4663050ec1b8e39a753f6e42e38b@changeid
2021-12-07drm/panel: Update Boe-tv110c9m and Inx-hj110iz initial codeyangcong
At present, we have enough panel to confirm the effect, update the initial code to achieve the best effect. Such as gamma, Gop timing. They are all minor modifications and doesn't affect the lighting of the panel. a)Boe-tv110c9m panel Optimized touch horizontal grain. b)Inx-hj110iz panel Optimized GOP timing and gamma. Signed-off-by: yangcong <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20211201023230.344976-1-yangcong5@huaqin.corp-partner.google.com
2021-12-07drm/i915: Allow cdclk squasher to be reconfigured liveVille Syrjälä
Supposedly we should be able to change the cdclk squasher waveform even when many pipes are active. Make it so. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-6-mika.kahola@intel.com
2021-12-07drm/i915/display/dg2: Read CD clock from squasher tableMika Kahola
To calculate CD clock with squasher unit, we set CD clock ratio to fixed value of 34. The CD clock value is read from CD clock squasher table. BSpec: 54034 v2: Read ratio from register (Ville) Drop unnecessary local variable (Ville) Get CD clock from the given table v3: Calculate CD clock frequency based on waveform bit pattern (Ville) [v4: vsyrjala: Actually do a proper blind readout from the hardware] [v5: vsyrjala: Use has_cdclk_squasher()] Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-5-mika.kahola@intel.com
2021-12-07drm/i915/display/dg2: Set CD clock squashing registersMika Kahola
Set CD clock squashing registers based on selected CD clock. v2: use slk_cdclk_decimal() to compute decimal values instead of a specific table (Ville) Set waveform based on CD clock table (Ville) Drop unnecessary local variable (Ville) v3: Correct function naming (Ville) Correct if-else structure (Ville) [v4: vsyrjala: Fix spaces vs. tabs] [v5: vsyrjala: Fix cd2x divider calculation (Uma), Add warn to waveform lookup (Uma), Handle bypass freq in waveform lookup, Generalize waveform handling in bxt_set_cdclk()] Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-4-mika.kahola@intel.com
2021-12-07drm/i915/display/dg2: Sanitize CD clockMika Kahola
In case of CD clock squashing the divider is always 1. We don't need to calculate the divider in use so let's skip that for DG2. v2: Drop unnecessary local variable (Ville) v3: Avoid if-else structure (Ville) [v4: vsyrjala: Fix cd2x divider calculation (Uma), Introduce has_cdclk_squasher()] Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-3-mika.kahola@intel.com
2021-12-07drm/i915/display/dg2: Introduce CD clock squashing tableMika Kahola
For CD clock squashing method, we need to define corresponding CD clock table for reference clocks, dividers and ratios for all CD clock options. BSpec: 54034 v2: Add CD squashing waveforms as part of CD clock table (Ville) v3: Waveform is 16 bits wide (Ville) [v4: vsyrjala: Nuke the non-squasher based table, Set .divider=2 for consistency, Pack intel_cdclk_vals a bit nicer] v5: Fix error in waveform value (Swati) v6 (Lucas): Rebase on upstream v7 (MattR): Drop 40.8, 81.6, and 122.4 MHz frequencies to reflect new bspec update. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-2-mika.kahola@intel.com
2021-12-07drm/i915/selftests: Follow up on increase timeout in i915_gem_contexts selftestsBruce Chang
Follow up on below commit, to increase the timeout further on new platforms, to accomodate the additional time required for the completion of guc submissions for numerous requests created in loop. commit 5e076529e2652244ec20a86d8f99ba634a16c4f4 Author: Matthew Brost <matthew.brost@intel.com> Date: Mon Jul 26 20:17:03 2021 -0700 drm/i915/selftests: Increase timeout in i915_gem_contexts selftests Signed-off-by: Bruce Chang <yu.bruce.chang@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211207003845.12419-1-yu.bruce.chang@intel.com
2021-12-07drm/rockchip: pass 0 to drm_fbdev_generic_setup()John Keeping
Allow drm_fbdev_generic_setup() to pick the default bpp value for the framebuffer. This has no functional impact because the default is 32, given that mode_config.preferred_depth is not set for Rockchip. Suggested-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20211101114622.813536-1-john@metanate.com
2021-12-07drm/rockchip: use generic fbdev setupJohn Keeping
The Rockchip fbdev code does not add anything compared to drm_fbdev_generic_setup(); the one custom function for .fb_mmap does the same thing as gem_prime_mmap which is called by the helper. Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20211029115014.264084-1-john@metanate.com
2021-12-07drm/i915/ddi: add use_edp_hobl() and use_edp_low_vswing() helpersJani Nikula
Localize HOBL and low vswing VBT lookups to a couple of small helpers, and get rid of a bunch of local variables. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211203131318.2885969-1-jani.nikula@intel.com
2021-12-07drm/i915/snps: use div32 version of MPLLB word clock for UHBRJani Nikula
The mode set sequence for 128b/132b requires setting the div32 version of MPLLB clock. Bspec: 53880, 54128 Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211202144456.2541305-1-jani.nikula@intel.com
2021-12-07drm/i915/xelpd: Add Pipe Color Lut caps to platform configUma Shankar
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for extended range. It has 511 entries for gamma with additional 2 entries for extended range. v2: Updated lut size for 10bit gamma, added lut_tests (Ville) v3: Dropped the gamma lut tests fields (Ville) Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211207071135.3660332-4-uma.shankar@intel.com
2021-12-07drm/i915/xelpd: Enable Pipe DegammaUma Shankar
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation to incorparate the extended lut size for XE_LPD. v2: Added a helper for degamma lut size (Ville) Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211207071135.3660332-3-uma.shankar@intel.com
2021-12-07drm/i915/xelpd: Enable Pipe color support for D13 platformUma Shankar
Enable pipe color support for Display 13 platforms. Currently limit to just 10bit gamma and later extend it for logarithmic gamma, once the new UAPI is agreed by community and implemented by a userspace consumer. v2: Updated dev_priv to i915 (Ville) Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211207071135.3660332-2-uma.shankar@intel.com
2021-12-06drm/i915/dmc: Change max DMC FW size on ADL-PMadhumitha Tolakanahalli Pradeep
Increase the max size of DMC on ADL-P to account for support of new features in the current/upcoming DMC versions. Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211207023718.322349-1-madhumitha.tolakanahalli.pradeep@intel.com
2021-12-06drm/i915: Introduce new macros for i915 PTEMichael Cheng
Certain functions within i915 uses macros that are defined for specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT (Some architectures don't even have these macros defined, like ARM64). Instead of re-using bits defined for the CPU, we should use bits defined for i915. This patch introduces two new 64 bit macros, GEN8_PAGE_PRESENT and GEN8_PAGE_RW, to check for bits 0 and 1 and, to replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915. v2(Michael Cheng): Use GEN8_ instead of I915_ Signed-off-by: Michael Cheng <michael.cheng@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> [ Move defines together with other GEN8 defines ] Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211206215245.513677-2-michael.cheng@intel.com
2021-12-06drm/msm: Initialize MDSS irq domain at probe timeDmitry Baryshkov
Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order"), the DSI host gets initialized earlier, but this caused unability to probe the entire stack of components because they all depend on interrupts coming from the main `mdss` node (mdp5, or dpu1). To fix this issue, move mdss device initialization (which include irq domain setup) to msm_mdev_probe() time, as to make sure that the interrupt controller is available before dsi and/or other components try to initialize, finally satisfying the dependency. Fixes: 8f59ee9a570c ("drm/msm/dsi: Adjust probe order") Co-Developed-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211201202023.2313971-1-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-12-06drm/msm: Allocate msm_drm_private early and pass it as driver dataAngeloGioacchino Del Regno
In preparation for registering the mdss interrupt controller earlier, move the allocation of msm_drm_private from component bind time to msm_drv probe; this also allows us to use the devm variant of kzalloc. Since it is not right to allocate the drm_device at probe time (as it should exist only when all components are bound, and taken down when components get cleaned up), the only way to make this happen is to pass a pointer to msm_drm_private as driver data (like done in many other DRM drivers), instead of one to drm_device like it's currently done in this driver. This is also simplifying some bind/unbind functions around drm/msm, as some of them are using drm_device just to grab a pointer to the msm_drm_private structure, which we now retrieve in one call. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211201105210.24970-2-angelogioacchino.delregno@collabora.com Signed-off-by: Rob Clark <robdclark@chromium.org>
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