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path: root/drivers/gpu/drm
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2018-03-20drm/sun4i: hdmi: Fix an error handling path in 'sun4i_hdmi_bind()'Christophe JAILLET
If we can not allocate the HDMI encoder regmap, we still need to free some resources before returning. Fixes: 4b1c924b1fc1 ("drm/sun4i: hdmi: create a regmap for later use") Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/14c42391e1b562c7495bda6ad6fa1d24ec8dc052.1521413031.git.christophe.jaillet@wanadoo.fr
2018-03-20sched/wait, drivers/drm: Convert wait_on_atomic_t() usage to the new ↵Peter Zijlstra
wait_var_event() API The old wait_on_atomic_t() is going to get removed, use the more flexible wait_var_event() API instead. Unlike wake_up_atomic_t(), wake_up_var() will issue the wakeup even if the variable is not 0. No change in functionality. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: David Airlie <airlied@linux.ie> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-03-19drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.Dhinakaran Pandiyan
If bios sets up an MST output and hardware state readout code sees this is an SST configuration, when disabling the encoder we end up calling ->post_disable_dp() hook instead of the MST version. Consequently, we write to the DP_SET_POWER dpcd to set it D3 state. Further along when we try enable the encoder in MST mode, POWER_UP_PHY transaction fails to power up the MST hub. This results in continuous link training failures which keep the system busy delaying boot. We could identify bios MST boot discrepancy and handle it accordingly but a simple way to solve this is to write to the DP_SET_POWER dpcd for MST too. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105470 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reported-by: Laura Abbott <labbott@redhat.com> Cc: stable@vger.kernel.org Fixes: 5ea2355a100a ("drm/i915/mst: Use MST sideband message transactions for dpms control") Tested-by: Laura Abbott <labbott@redhat.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180314054825.1718-1-dhinakaran.pandiyan@intel.com (cherry picked from commit ad260ab32a4d94fa974f58262f8000472d34fd5b) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-03-19drm/sun4i: backend: Support YUV planesMaxime Ripard
Now that we have the guarantee that we will have only a single YUV plane, actually support them. The way it works is not really straightforward, since we first need to enable the YUV mode in the plane that we want to setup, and then we have a few registers to setup the YUV buffer and parameters. We also need to setup the color correction to actually have something displayed. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/66088c1398bd3189123f28a89a7ccc669fe9f296.1519931807.git-series.maxime.ripard@bootlin.com
2018-03-19drm/amd/pp: Remove unneeded void * casts for Vega10Rex Zhu
Removes unneeded void * casts for the following pointers: hwmgr->backend hwmgr->smu_backend Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-19drm/amd/pp: Delete get_xclk function in powerplay (v2)Rex Zhu
use asic's callback function get_xclk in amdgpu v2: squash in removal of leftover debug info (drm/amd/pp: Delete debug info in smu7_hwmgr.c) (Rex) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-19drm/amd/pp: Clean up header file for Vega10Rex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-19drm/amd/pp: Move functions to smu backend table for vega10Rex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-19drm/amd/pp: Mark bunches of functins in vega10_smumgr.c staticRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-19drm/amd/pp: Remove dead functions in vega10_smumgr.cRex Zhu
use smc_table_manager function to copy/save tables to/from smu. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-19drm/amdgpu: Delete dead code when early initRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-19drm/amd/display: fix dereferencing possible ERR_PTR()Shirish S
This patch fixes static checker warning caused by "36cc549d5986: "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)" Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-19drm/amd/display: Refine disable VGAClark Zheng
bad case won't follow normal sense, it will not enable vga1 as usual, but vga2,3,4 is on. Signed-off-by: Clark Zheng <clark.zheng@amd.com> Reviewed-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-19drm/sun4i: backend: Check that we only have a single YUV planeMaxime Ripard
Just like for the frontend, a single plane can use a YUV format. Make sure we have that constraint covered in our atomic_check. This is preliminary to the actual YUV support to make sure we don't end up in an impossible to support situation. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/2f8586493d9139b12efe7e94f65e9a149f818e0e.1519931807.git-series.maxime.ripard@bootlin.com
2018-03-19drm/sun4i: Add driver support for A80 display pipelineChen-Yu Tsai
This patch adds support for the compatible strings of the A80 display pipeline. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180315114136.24747-6-wens@csie.org
2018-03-19drm/sun4i: Add support for A80 TCONsChen-Yu Tsai
The Allwinner A80 SoC has 2 documented TCONs. The display pipeline diagram from the user manual shows a third TCON, but it's missing an interrupt line, and its registers are not explained either. It's also not used in Allwinner's vendor BSP. The first TCON only has channel 0, for LCD panel output. The TCON hardware setup is peculiar in that the eDP reset must also be deasserted to allow access to the TCON. How the eDP module is wired in the SoC itself is never explained. The second TCON only has channel 1, and its output is connected to the HDMI encoder block. This patch adds a "needs_edp_reset" field to the tcon quirks structure, and adds quirks and compatible strings for the 2 documented TCONs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180315114136.24747-4-wens@csie.org
2018-03-19drm: Reduce object size of DRM_DEV_<LEVEL> usesJoe Perches
These macros are similar to the DRM_<LEVEL> with the addition of a struct device * to the arguments. Convert the single drm_dev_printk function into 2 separate functions. drm_dev_printk with a KERN_<LEVEL> * for generic use and drm_dev_dbg for conditional masked use. Remove the __func__ argument and use __builtin_return_address(0) to be similar to the DRM_<LEVEL> macros uses. Convert the DRM_DEV_<LEVEL> macros to remove now unnecessary arguments and use a consistent style. These macros are rarely used in the generic gpu/drm code so the code size does not change much for a defconfig, but when more drivers are enabled, there is ~4k savings. Many of these macros have no existing use at all. $ size -t drivers/gpu/drm/built-in.a | tail -1 1877530 44651 995 1923176 1d5868 (TOTALS) $ size -t drivers/gpu/drm/built-in.a | tail -1 1877527 44651 995 1923173 1d5865 (TOTALS) $ size -t drivers/gpu/drm/built-in.a | tail -1 17166750 2689238 108352 19964340 130a1b4 (TOTALS) $ size -t drivers/gpu/drm/built-in.a | tail -1 17168888 2691734 108352 19968974 130b3ce (TOTALS) Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/e5c164946e15375ac71b69b75f296efdf0b76e6d.1521233717.git.joe@perches.com
2018-03-19drm: dma_bufs: Fixed checkpatch issuesPaul McQuade
Fix a couple of checkpatch issues Signed-off-by: Paul McQuade <paulmcquad@gmail.com> [seanpaul squashed series of 4 into one patch, and changed commit msg] Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180319005225.1545-1-paulmcquad@gmail.com
2018-03-19drm/msm: fix building without debugfsArnd Bergmann
The adreno driver stopped building when CONFIG_DEBUGFS is disabled: drivers/gpu/drm/msm/adreno/adreno_device.c: In function 'adreno_load_gpu': drivers/gpu/drm/msm/adreno/adreno_device.c:153:16: error: 'const struct msm_gpu_funcs' has no member named 'debugfs_init' if (gpu->funcs->debugfs_init) { ^~ drivers/gpu/drm/msm/adreno/adreno_device.c:154:13: error: 'const struct msm_gpu_funcs' has no member named 'debugfs_init' gpu->funcs->debugfs_init(gpu, dev->primary); ^~ This adds an #ifdef around the code that references the hidden pointer. Fixes: 331dc0bc195b ("drm/msm: add a5xx specific debugfs") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-03-19drm/msm/mdp5: don't pre-reserve LM's if no dual-dsiRob Clark
If there is only a single DSI interface, don't reserve the first two layer-mixers for the dual-DSI use-case. This was causing problems for WB, not being able to assign a LM, on 8x16, which has only two LM's and a single DSI. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-03-19drm/msm/mdp5: add missing LM flush bitsRob Clark
For some reason, layer-mixer 3 and 4 were missing. LM3 is used for writeback on 8x16. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-03-19drm/msm/mdp5: print a bit more of the atomic stateRob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-03-19drm/msm/mdp5: rework CTL START signal handlingRob Clark
For DSI cmd-mode and writeback, we need to write the CTL's START register to kick things off, but we only want to do that once both the encoder and the crtc have a chance to write their corresponding flush bits. The difficulty is that when there is a full modeset (ie. encoder state has changed) we want to defer the start until encoder->enable(). But if only plane's have changed, we want to do this from crtc->commit(). The start_mask was a previous attempt to handle this, but it didn't really do the right thing since atomic conversion. Instead track in the crtc state that the start should be deferred, set to try from encoder's (or in future writeback's) atomic_check(). This way the state is part of the atomic state, and rollback can work properly if an atomic test fails. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-03-19drm/msm: Trigger fence completion from GPUBjorn Andersson
Interrupt commands causes the CP to trigger an interrupt as the command is processed, regardless of the GPU being done processing previous commands. This is seen by the interrupt being delivered before the fence is written on 8974 and is likely the cause of the additional CP_WAIT_FOR_IDLE workaround found for a306, which would cause the CP to wait for the GPU to go idle before triggering the interrupt. Instead we can set the (undocumented) BIT(31) of the CACHE_FLUSH_TS which will cause a special CACHE_FLUSH_TS interrupt to be triggered from the GPU as the write event is processed. Add CACHE_FLUSH_TS to the IRQ masks of A3xx and A4xx and remove the workaround for A306. Suggested-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-03-19drm/msm/dsi: fix direct caller of msm_gem_free_object()Rob Clark
This should be using drm_gem_object_put(). Also since this is done only in driver unload path, we don't need to synchronize setting tx_gem_obj to NULL, so juse use the _unlocked() variant. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-03-19drm/msm: strip out msm_fence_cbRob Clark
Remnants of pre-dma_fence fencing which got left behind by mistake. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-03-19drm/msm: rename mdp->dispRob Clark
Since new display controller is called "dpu" instead of "mdp". Lets make the name of the toplevel directory for the display controllers a bit more generic. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2018-03-19drm/msm/dsi: Fix potential NULL pointer dereference in msm_dsi_modeset_initGustavo A. R. Silva
_dev_ is being dereferenced before it is null checked, hence there is a potential null pointer dereference. Fix this by moving the pointer dereference after _dev_ has been null checked. Fixes: d4e7f38d70ef ("drm/msm/dsi: check msm_dsi and dsi pointers before use") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-03-19drm/msm/adreno/a5xx_debugfs: fix potential NULL pointer dereferenceGustavo A. R. Silva
_minor_ is being dereferenced before it is null checked, hence there is a potential null pointer dereference. Fix this by moving the pointer dereference after _minor_ has been null checked. Fixes: 024ad8df763f ("drm/msm: add a5xx specific debugfs") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-03-19drm/i915/gvt: force to set all context control bits from guestZhenyu Wang
Our shadow context content is from guest but with masked control reg like CTX_CONTEXT_CONTROL, we need to make sure all settings from guest would be set when this context is on hw, this trys to force mask enable bits for all to ensure every bits setting would be effective on hw. One regression found related to once inhibit bit is set, gpu engine are working on inhibit state until MI_LOAD_REG_IMM command or context image clear inhibit bit with mask bit set to 1, and val bit set to 0. In gvt-g currently workload has the highest priority, so gvt-g workload could trigger preempt context easily, preempt context set inhibit bit, then gvt-g workload is scheduled in, but gvt-g workload shadow context image usually doesn't set inhibit mask bit, so gpu is still in inhibit state when gvt workload is running. This caused gpu hang. Suggested-by: Zhang, Xiong <xiong.y.zhang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Zhang, Xiong <xiong.y.zhang@intel.com>
2018-03-19drm/tegra: Shutdown on driver unbindThierry Reding
Since commit 846c7dfc1193 ("drm/atomic: Try to preserve the crtc enabled state in drm_atomic_remove_fb, v2."), removing the last framebuffer will no longer disable the corresponding pipeline, which causes the KMS core to complain about leaked connectors on driver unbind. Fix this by calling drm_atomic_helper_shutdown() on driver unbind, which will cause all display pipelines to be shut down and therefore drop the extra references on the connectors. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-19drm/tegra: dsi: Don't disable regulator on ->exit()Thierry Reding
The regulator is controlled as part of runtime PM, so it should not be additionally disabled from the ->exit() callback. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-19drm/tegra: dc: Detach IOMMU group from domain only onceThierry Reding
Detaching from an IOMMU group multiple times can lead to a crash. This could potentially be fixed in the IOMMU driver, but it's easy to avoid the subsequent detach operations in this driver, so do that as well. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-19drm/i915/gvt: Update PDPs after a vGPU mm object is pinned.Zhi Wang
The PDPs of a shadow page will only be valid after a vGPU mm is pinned. So the PDPs in the shadow context should be updated then. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-03-19drm/i915/gvt: Invalidate vGPU PPGTT mm objects during a vGPU reset.Zhi Wang
As different OSes might handling GVT PPGTT creation/destroy notification differently during a vGPU reset. A better approach is invalidating all vGPU PPGTT mm objects during vGPU reset. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-03-19drm/i915/kvmgt: Handle kzalloc failureChangbin Du
Out-of-memory error must be handled correctly. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-03-19drm/i915/gvt: fix spelling mistake: "destoried" -> "destroyed"Colin Ian King
Trivial fix to spelling mistake in gvt_err error message text. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-03-19drm/i915/gvt: Remove reduntant printing of untracked mmioColin Xu
Reduntant message prints when: - linux guest creating. - dma-buf win10 guest boot. - xonotic stress testing in linux guest. Add below registers to default MMIO handler: 0xd00, RPM_CONFIG0 0xd40, RC6_LOCATION 0x65010, HSW_AUD_MISC_CTRL 0x6671c, 0x700a0, CUR_FBC_CTL 0x7239c, v2: - Should init i915_reg_t using uint32_t instead of _MMIO macro. (compiling errors) - Use defined offset in i915_reg.h (zhenyu) Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-03-17drm/tegra: prime: Implement ->{begin,end}_cpu_access()Thierry Reding
These callbacks allow the exporter to swap in and pin the backing storage for buffers as well as invalidate the cache in preparation for accessing the buffer from the CPU, and flush the cache and unpin the backing storage when the CPU is done modifying the buffer. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-17drm/tegra: gem: Map pages via the DMA APIThierry Reding
When allocating pages, map them with the DMA API in order to invalidate caches. This is the correct usage of the API and works just as well as faking up the SG table and using the dma_sync_sg_for_device() function. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-17drm/tegra: hub: Use private object for global stateThierry Reding
Rather than subclass the global atomic state to store the hub display clock and rate, create a private object and store this data in its state. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-16drm/vc4_validate: Remove VLA usageGustavo A. R. Silva
In preparation to enabling -Wvla, remove VLA. In this particular case use macro ARRAY_SIZE so the length of array _bo_ can be computed at preprocessing time. The use of stack Variable Length Arrays needs to be avoided, as they can be a vector for stack exhaustion, which can be both a runtime bug or a security flaw. Also, in general, as code evolves it is easy to lose track of how big a VLA can get. Thus, we can end up having runtime failures that are hard to debug. Also, fixed as part of the directive to remove all VLAs from the kernel: https://lkml.org/lkml/2018/3/7/621 Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20180313143151.GA27486@embeddedgus
2018-03-16amdgpu/dm: Default PRE_VEGA ASIC support to 'y'Harry Wentland
Even though we default PRE_VEGA support to 'n' upstream in amd-staging we want to keep it enabled by default. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-16drm/amd/pp: Remove the cgs wrapper for notify smu version on APURex Zhu
Refine commit f49e9bac191b ("drm/amd/pp: Get and save Rv smu version") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-16drm/amd/display: fix dereferencing possible ERR_PTR()Shirish S
This patch fixes static checker warning caused by "36cc549d5986: "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)" Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-16drm/amd/display: Refine disable VGAClark Zheng
bad case won't follow normal sense, it will not enable vga1 as usual, but vga2,3,4 is on. Signed-off-by: Clark Zheng <clark.zheng@amd.com> Reviewed-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-16drm: Make drm_mode_vrefresh() a bit more accurateVille Syrjälä
Do the refresh rate calculation with a single division. This gives us slightly more accurate results, especially for interlaced since we don't just double the final truncated result. We do lose one bit compared to the old way, so with an interlaced mode the new code can only handle ~2GHz instead of the ~4GHz the old code handeled. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180313150759.27620-2-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2018-03-16drm: Nuke the useless 'ret' variable from drm_mode_convert_umode()Ville Syrjälä
No need to store the return value in a variable since we don't have to do any unwinding. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180313150759.27620-1-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2018-03-16drm/i915: Use drm_color_lut_size()Ville Syrjälä
Avoid all the sizeof(drm_color_lut) business by using drm_color_lut_size() to convert the blob length into number of LUT entries. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180223192506.29992-6-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2018-03-16drm/i915: Remove the blob->data castsVille Syrjälä
Now that blob->data is void* again we don't need to cast it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180223192506.29992-5-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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