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path: root/drivers/gpu
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2015-12-14drm/msm/dsi: Add dsi_cfg for APQ8064Archit Taneja
Add a dsi_cfg entry for APQ8064. Since this is the first DSIv2 chip to be supported, add a list of bus clocks that are required by the DSIv2 block. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/dsi: Set up link clocks for DSIv2Archit Taneja
DSIv2 (DSI on older A family chips) has slightly different link clock requirements. First, we have an extra clock called src_clk (with a dedicated RCG). This is required by the DSI controller to process the pixel data coming from MDP. It needs to be set at the rate "pclk * bytes_per_pixel". We also need to explicitly configure esc_clk. On DSI6G chips, we don't need to set a rate to esc_clk because its RCG is always sourced from crystal clock (19.2 Mhz in all cases), which is within the escape clock frequency range in the mipi DSI spec. For chips with DSIv2, the crystal clock rate may not be within the required range (27Mhz on APQ8064). Therefore, we derive it from the DSI byte clock. We calculate an esc_clck rate that is within the mipi spec and also divisible by the byte clock rate. When setting rate and enabling the link clocks, we make sure that byte_clk is configured before esc_clk, and src_clk before pixel_clk. We create two different link_enable funcs for DSI6G and DSIv2 since the sequences are different. We also obtain two extra source clocks (dsi_src_clk and esc_src_clk) and set their parent to the clocks provided by DSI PLL. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/dsi: Parse bus clocks from a listArchit Taneja
DSI bus clocks seem to vary between different DSI host versions, and the SOC to which they belong. Even the enable/disable sequence varies. Provide a list of bus clock names in dsi_cfg. The driver will use this to retrieve the clocks, and enable/disable them. Add bus clock lists for DSI6G, and DSI for MSM8916(this is DSI6G too, but there is no MMSS_CC specific clock since there is no MMSS clock controller on 8916). Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/dsi: Delay dsi_clk_initArchit Taneja
Initialize clocks only after we get the DSI host version. This will allow us to get clocks using a pre-defined list based on the DSI major/minor version of the host. This is required since clock requirements of different major DSI revisions(v2 vs 6g) aren't the same. Modify dsi_get_version to get the interface clock, and then put it after it is used. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/dsi: Use a better way to figure out DSI versionArchit Taneja
The current version checking mechanism works fine for DSI6G blocks. It doesn't work so well for older generation DSIv2 blocks. The initial read of REG_DSI_6G_HW_VERSION(offset 0x0) would result in a read of REG_DSI_CTRL for DSIv2. This register won't necessarily be 0 on DSIv2. It can be non zero if DSI was previously initialized by the bootloader. Instead of reading offset 0x0, we now read offset 0x1f0. For DSIv2, this register is DSI_VERSION, and is bound to be non-zero. On DSI6G, this register(offset 0x1f0) is SCRATCH_REGISTER_0, which no one ever seems to touch, and from all register dumps I'vc seen, holds 0 all the time. Modify dsi_get_version to read REG_DSI_VERSION to determine whether we are DSI6G or DSIv2. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/dsi: Add DSI PLL for 28nm 8960 PHYArchit Taneja
Add DSI PLL common clock framework clocks for 8960 PHY. The PLL here is different from the ones found in B family msm chips. As before, the DSI provides two clocks to the outside world. dsixpll and dsixpllbyte (x = 1, 2). dsixpll is a regular clock divider, but dsixpllbyte is modelled as a custom clock divider. dsixpllbyte is the starting point of the PLL configuration. It is the one that sets up the VCO clock rate. We need the VCO clock rate in the form: F * byteclk, where F is a multiplication factor that varies on the byte clock the DSI driver is trying to set. We use the custom clk_ops for dsixpllbyte to ensure that the parent (VCO) is set at this rate. An additional divider (POSTDIV1) generates the bitclk. Since bit clock can be derived from byteclock, we calculate it internally, and don't expose it as a clock. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/dsi: Add support for 28nm PHY on 8960Archit Taneja
DSI PHY on MSM8960 and APQ8064 is a 28nm PHY that's different from the supported 28nm LP PHY found in newer chips. Add support for the new PHY. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/dsi: Don't get byte/pixel source clocks from DTArchit Taneja
We retrieve the byte and pixel source clocks (RCG clocks) in the dsi driver via DT. These are needed so that we can re-parent these source clocks if we want to drive it using a different DSI PLL. We shouldn't get these via DT because they aren't clocks that directly serve as inputs to the dsi host. Fortunately, there is a static parent-child link between the byte_clk_src/pixel_clk_src and byte_clk/pixel_clk clocks. So, we can retrieve the source clocks via clk_get_parent. Do this instead of retrieving via DT. Cc: Rob Herring <robh@kernel.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/mdp4: Initialize DSI encodersArchit Taneja
Create DSI encoders during modeset_init. The 2 encoders should ideally be one command mode and one video mode DSI encoder respectively, but we don't support command mode yet. We just create 2 of the same because the dsi driver expects it, we end up using only the first one. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/mdp4: Call custom round_pixclk helper only if the encoder type is TMDSArchit Taneja
The mdp_kms round_pixclk op creates problems when we have more interfaces in use. It calls the DTV encoder's helper by default. Check on encoder type and call the corresponding encoder's func meant for rounding pixel clock. DSI and LVDS don't require rounding, so just return rate in their case. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/dsi: Add a mdp4 encoder for DSIVinay Simha BN
Create an mdp4 incoder for DSI. Only DSI video mode is supported as of now. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Vinay Simha BN <vinaysimha@inforcecomputing.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/mdp4: Initialize LCDC encoder even if panel driver isn't availableArchit Taneja
Currently, the driver defers if it doesn't find a drm_panel. This forces us to have a drm_panel, if not, the driver isn't usable. Make the lcdc encoder initialization independent of the availability of the drm panel. We only check if there is a panel node specified in DT. If it isn't, then we don't initialize the encoder at all. The panel node is passed to the lcdc encoder and lvds connector drivers. The connector driver takes the responsibility to retrieve the drm_panel from the panel node, and update the status on whether the panel is connected or not. This makes the panel usable even if the drm_panel driver is inserted as a module later on. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/mdp4: Clean up modeset_initArchit Taneja
modeset_init() for mdp4 isn't very flexible. That makes it hard to add more interfaces. Split out the encoder/connector creation code in modeset_init into a separate function. This is similar to what's done in modeset_init for mdp5. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/adreno: Remove CONFIG_OF checksArchit Taneja
Remove CONFIG_OF checks in adreno_device.c. The downstream bus scaling stuff is included only when CONFIG_OF is not set. So, remove that too. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/hdmi: remove CONFIG_OF checksArchit Taneja
We now only care about kernels that support DT. Remote the non-DT stuff. While we're at it, use of_device_get_match_data to retrieve match data. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/mdp: Remove CONFIG_OF checks from MDP driversArchit Taneja
We don't intend to use downstream non-DT kernels anymore, so remove CONFIG_OF checks. Update the TODO comment so that we don't forget about max_clk setting for non APQ8064 chips having MDP4. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm: Update compatible strings for mdpArchit Taneja
Create distinct compatible strings for mdp4 and mdp5. Keep "qcom,mdss_mdp" as is to support downstream kernels. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm: Remove non-DT code in msm_drvArchit Taneja
Support for non-DT kernels was mainly to use v3.4 downstream kernels. This is no longer a priority now as we have reasonable support upstream. Remove CONFIG_OF from the top level msm_drv.c file. While we're at it, clean up the data matching process using of_device_get_match_data. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/msm/mdp5: high precision vblank timestamp supportArchit Taneja
MDP5 has line count and frame count registers for each interface. Enable these counters and use them to implement the get_vblank_timestamp drm driver op. The line counter starts with the value 1 at the beginning of the VSYNC pulse and ends with value VTOTAL at the end of VFP. This value is used to determine whether we're in blanking period or not, and an adjusted value of this counter is used to get vpos as expected by get_scanout_position. Since there is no way to calculate hpos, we always set it to 0. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-12-14drm/tegra: Advertise DRIVER_ATOMICThierry Reding
The driver has supported atomic mode-setting for quite a while. It's time to advertise that. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: Use DRIVER level for IOMMU aperture messageThierry Reding
This allows the message to be shown even if core messages are disabled globally in DRM. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: checking for IS_ERR() instead of NULLDan Carpenter
The tegra_sor_hdmi_find_settings() function returns NULL on error and not an ERR_PTR. Fixes: 459cc2c6800b ('drm/tegra: sor: Add HDMI support') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: dc: Add missing of_node_put()Julia Lawall
for_each_matching_node() performs an of_node_get() on each iteration, so a break out of the loop requires an of_node_put(). A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e; @@ for_each_matching_node(n,...) { ... ( of_node_put(n); | e = n | + of_node_put(n); ? break; ) ... } ... when != n // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: Implement subsystem-level suspend/resumeThierry Reding
Use the drm_atomic_helper_suspend() and drm_atomic_helper_resume() helpers to implement subsystem-level suspend/resume. v2: suspend framebuffer device to avoid concurrency issues v3: resume fbdev on failure to suspend (Emil Velikov) Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: sor: Remove unnecessary conditionalThierry Reding
Checking for sor->aux in eDP specific code is unnecessary because eDP inherently requires a valid AUX channel. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: sor: Operate on struct drm_dp_aux *Thierry Reding
Instead of getting a pointer to the driver-specific wrapper of AUX channels, use the AUX channel objects directly to avoid hackish casting between the two types. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: Use drm_gem_object_unreference_unlocked()Daniel Vetter
This only grabs the mutex when really needed, but still has a might- acquire lockdep check to make sure that's always possible. With this patch Tegra DRM is officially struct_mutex free, yay! v2: refernce_unlocked doesn't exist as kbuild spotted. Cc: Thierry Reding <thierry.reding@gmail.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> [treding@nvidia.com: remove unused variables] Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: Don't take dev->struct_mutex in mmap offset ioctlDaniel Vetter
Since David Herrmann's mmap vma manager rework we don't need to grab dev->struct_mutex any more to prevent races when looking up the mmap offset. Drop it and instead don't forget to use the unref_unlocked variant (since the drm core still cares). v2: Finally get rid of the copypasta from another commit in this commit message. And convert to _unlocked like we need to (Patrik). Cc: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: Use unlocked gem unreferencingDaniel Vetter
For drm_gem_object_unreference callers are required to hold dev->struct_mutex, which these paths don't. Enforcing this requirement has become a bit more strict with commit ef4c6270bf2867e2f8032e9614d1a8cfc6c71663 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Oct 15 09:36:25 2015 +0200 drm/gem: Check locking in drm_gem_object_unreference Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: Use new multi-driver module helpersThierry Reding
Use the new multi-driver module helpers to get rid of some boilerplate in the module initialization and cleanup functions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14gpu: host1x: Add Tegra210 supportThierry Reding
The host1x unit found in Tegra210 SoCs is very similar to the unit in Tegra124, but it has 2 additional channels for a total of 14 channels. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14gpu: host1x: Remove core driver on unregisterThierry Reding
When unregistering a host1x driver, make sure to unregister the core driver as well to prevent it from sticking around and oppose reloading of the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14gpu: host1x: Use platform_register/unregister_drivers()Thierry Reding
These new helpers simplify implementing multi-driver modules and properly handle failure to register one driver by unregistering all previously registered drivers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/omap: fix fbdev pix format to support all platformsTomi Valkeinen
omap_fbdev always creates a framebuffer with ARGB8888 pixel format. On OMAP3 we have VIDEO1 overlay that does not support ARGB8888, and on OMAP2 none of the overlays support ARGB888. This patch changes the omap_fbdev's fb to XRGB8888, which is supported by all platforms. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Tested-by: H. Nikolaus Schaller <hns@goldelico.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-12-13drm/exynos: gem: remove old unused prototypesMarek Szyprowski
This patch removes old, unused function prototypes from exynos_drm_gem.h. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: fimd: fix dma burst size setting for small plane sizeMarek Szyprowski
This patch fixes trashed display of buffers cropped to very small width. Even if DMA is unstable and causes tearing when changing the burst size, it is still better than displaying a garbage. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: fix clipping when scaling is enabledMarek Szyprowski
This patch fixes calculation of src x/y offset for negative crtc x/y values when scaling is enabled. This fixes possible IOMMU fault when scaling is enabled. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: mixer: use ratio precalculated in exynos_stateMarek Szyprowski
Common plane code already calculates and checks for supported scalling modes, so additional code in mixer driver can be now removed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: add generic check for plane stateMarek Szyprowski
This patch adds generic check for plane state - display area dimensions, so drivers can always assume that they get valid plane state to set. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: introduce exynos_drm_plane_config structureMarek Szyprowski
This patch adds common structure for keeping plane configuration and capabilities data. This patch is inspired by similar code developed by Tobias Jakobi. Changelog v2: - fix vidi_win_types(i) call. vidi_win_types is not a function. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: mixer: enable video overlay plane only when VP is availableMarek Szyprowski
Video overlay plane should be registered only when suitable hardware sub-block (Video Processor) is available. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: mixer: use crtc->state->adjusted_mode instead of crtc->modeMarek Szyprowski
This patch replaces usage of crtc->mode with crtc->state->adjusted_mode like it is already done in common plane code. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: introduce exynos_drm_plane_state structureMarek Szyprowski
This patch introduces exynos_drm_plane_state structure, which subclasses drm_plane_state and holds precalculated data suitable for configuring Exynos hardware. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: move dma_addr attribute from exynos plane to exynos fbMarek Szyprowski
DMA address is a framebuffer attribute and the right place for it is exynos_drm_framebuffer not exynos_drm_plane. This patch also introduces helper function for getting dma address of the given framebuffer. Changelog v2: - use state->fb instead of plane->base.fb. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: exynos7-decon: remove excessive checkMarek Szyprowski
Display area is already checked by exynos plane core, so there is no need for such check in driver code. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: rotator: convert to common clock frameworkMarek Szyprowski
This driver was not used after introduction of common clock framework. This patch adds missing prepare/unprepare calls and allows to use it again with current kernel code. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: gsc: add device tree support and remove usage of static mappingsSeung-Woo Kim
This patch adds device tree support for exynos_drm_gsc. This patch also fixed build issue on non-Exynos platforms, thus dependency on !ARCH_MULTIPLATFORM can be now removed. The driver cannot be used simultaneously with V4L2 Mem2Mem GScaller driver thought. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: gsc: fix wrong pm_runtime stateSeung-Woo Kim
At probe time, gsc clock is not enabled, so pm_runtime state should be deactive. So this patch removes pm_runtime_set_active() from gsc_probe(). Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: gsc: prepare and unprepare gsc clockSeung-Woo Kim
Ths patch changes the clk_enable and clk_disable call in gsc driver into clk_prepare_enable and clk_disable_unprepare. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-13drm/exynos: dp: add of_graph dt binding support for panelInki Dae
This patch adds of_graph dt binding support for panel device and also keeps the backward compatibility. i.e., The dts file for Exynos5800 based peach pi board has a panel property so we need to keep the backward compatibility. Changelog v3: - bind only one of two nodes outbound - panel or bridge. Changelog v2: - return -EINVAL if getting a port node failed. Signed-off-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
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