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2019-01-28drm/qxl: drop unused offset parameter from qxl_io_create_primary()Gerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-12-kraxel@redhat.com
2019-01-28drm/qxl: move qxl_primary_apply_cursor to correct placeGerd Hoffmann
The qxl device ties the cursor to the primary surface. Therefore calling qxl_io_destroy_primary() and qxl_io_create_primary() to switch the framebuffer causes the cursor information being lost and the driver must re-apply it. The correct call order to do that is qxl_io_destroy_primary() + qxl_io_create_primary() + qxl_primary_apply_cursor(). The old code did qxl_io_destroy_primary() + qxl_primary_apply_cursor() + qxl_io_create_primary(). Due to qxl_primary_apply_cursor request being queued in a ringbuffer and qxl_io_create_primary() trapping to the hypervisor instantly there is a high chance that qxl_io_create_primary() is processed first even with the wrong call order. But it's racy and thus not reliable. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-11-kraxel@redhat.com
2019-01-28drm/qxl: use QXL_GEM_DOMAIN_SURFACE for dumb gem objectsGerd Hoffmann
dumb buffers are used as qxl surfaces, so allocate them as QXL_GEM_DOMAIN_SURFACE. Should usually be allocated in PRIV ttm domain then, so this reduces VRAM memory pressure. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-10-kraxel@redhat.com
2019-01-28drm/qxl: use QXL_GEM_DOMAIN_SURFACE for shadow bo.Gerd Hoffmann
The shadow bo is used as qxl surface, so allocate it as QXL_GEM_DOMAIN_SURFACE. Should usually be allocated in PRIV ttm domain then, so this reduces VRAM memory pressure. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-9-kraxel@redhat.com
2019-01-28drm/qxl: allow both PRIV and VRAM placement for QXL_GEM_DOMAIN_SURFACEGerd Hoffmann
qxl surfaces (used for framebuffers and gem objects) can live in both VRAM and PRIV ttm domains. Update placement setup to include both. Put PRIV first in the list so it is preferred, so VRAM will have more room for objects which must be allocated there. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-8-kraxel@redhat.com
2019-01-28drm/qxl: use separate offset spaces for the two slots / ttm memory types.Gerd Hoffmann
Without that ttm offsets are not unique, they can refer to objects in both VRAM and PRIV memory (aka main and surfaces slot). One of those "why things didn't blow up without this" moments. Probably offset conflicts are rare enough by pure luck. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-7-kraxel@redhat.com
2019-01-28drm/qxl: drop unused fields from struct qxl_deviceGerd Hoffmann
slot_id_bits and slot_gen_bits can be read directly from qxlrom instead. va_slot_mask is never used anywhere. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-6-kraxel@redhat.com
2019-01-28drm/qxl: change the way slot is detectedFrediano Ziglio
Instead of relaying on surface type use the actual placement. This allow to have different placement for a single type of surface. Signed-off-by: Frediano Ziglio <fziglio@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-5-kraxel@redhat.com [ kraxel: rebased, adapted to upstream changes ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-01-28drm/qxl: simplify slot managementGerd Hoffmann
Drop pointless indirection, remove the mem_slots array and index variables, drop dynamic allocation. Store memslots in qxl_device instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-4-kraxel@redhat.com
2019-01-28drm/qxl: drop unused qxl_fb_virtual_addressGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-3-kraxel@redhat.com
2019-01-28drm/qxl: drop ttm_mem_reg arg from qxl_hw_surface_alloc()Gerd Hoffmann
Not used, is always NULL. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Link: http://patchwork.freedesktop.org/patch/msgid/20190118122020.27596-2-kraxel@redhat.com
2019-01-28drm/rockchip: fix for mailbox read validation.Damian Kos
This is basically the same fix as in commit fa68d4f8476b ("drm/rockchip: fix for mailbox read size") but for cdn_dp_mailbox_validate_receive function. See patchwork.kernel.org/patch/10671981/ for details. Signed-off-by: Damian Kos <dkos@cadence.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/1542640463-18332-1-git-send-email-dkos@cadence.com
2019-01-28drm/i915: Wait for a moment before forcibly resetting the deviceChris Wilson
During igt, we ask to reset the device if any requests are still outstanding at the end of a test, as this quickly kills off any erroneous hanging request streams that may escape a test. However, since it may take the device a few milliseconds to flush itself after the end of a normal test, *cough* guc *cough*, we may accidentally tell the device to reset itself after it idles. If we wait a moment, our usual I915_IDLE_ENGINES_TIMEOUT of 200ms (seems a bit high, but still better than umpteen hangchecks!), we can differentiate better between a stuck engine and a healthy one, and so avoid prematurely forcing the reset and any extra complications that may entail. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190128010245.20148-1-chris@chris-wilson.co.uk
2019-01-27drm/rockchip: check yuv2yuv existence before assigning window dataHeiko Stuebner
Before assigning window data, we should check if the yuv2yuv vop-data is set at all, because it looks like it can otherwise reference something wrong, as I saw on my rk3188 today which ended up in a null pointer dereference in vop_plane_atomic_update when accessing the yuv2yuv data. Fixes: 1c21aa8f2b68 ("drm/rockchip: Fix YUV buffers color rendering") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/2556882.Heuq80WCVD@phil
2019-01-27drm/atmel-hlcdc: fix clipping of planesPeter Rosin
With the help from drm_atomic_helper_check_plane_state function, clipping now handles planes to be partially or totally off-screen. The plane is disabled if it is not visible. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190110151020.30468-4-peda@axentia.se
2019-01-27drm/atmel-hlcdc: do not swap w/h of the crtc when a plane is rotatedPeter Rosin
The destination crtc rectangle is independent of source plane rotation. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190110151020.30468-3-peda@axentia.se
2019-01-27drm/atmel-hlcdc: rotate planes counterclockwisePeter Rosin
Ouch, the driver rotates planes clockwise, which is simply not correct. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190110151020.30468-2-peda@axentia.se
2019-01-26drm/i915: Disable -WuninitializedNathan Chancellor
This warning is disabled by default in scripts/Makefile.extrawarn when W= is not provided but this Makefile adds -Wall after this warning is disabled so it shows up in the build when it shouldn't: In file included from drivers/gpu/drm/i915/intel_breadcrumbs.c:895: drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c:350:34: error: variable 'wq' is uninitialized when used within its own initialization [-Werror,-Wuninitialized] DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq); ^~ ./include/linux/wait.h:74:63: note: expanded from macro 'DECLARE_WAIT_QUEUE_HEAD_ONSTACK' struct wait_queue_head name = __WAIT_QUEUE_HEAD_INIT_ONSTACK(name) ~~~~ ^~~~ ./include/linux/wait.h:72:33: note: expanded from macro '__WAIT_QUEUE_HEAD_INIT_ONSTACK' ({ init_waitqueue_head(&name); name; }) ^~~~ 1 error generated. Explicitly disable the warning like commit 46e2068081e9 ("drm/i915: Disable some extra clang warnings"). Link: https://github.com/ClangBuiltLinux/linux/issues/220 Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nick Desaulniers <nick.desaulniers@gmail.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190126071122.24557-1-natechancellor@gmail.com
2019-01-25drm/i915: correct the pitch check for NV12 framebufferP Raviraj Sitaram
framebuffer for NV12 requires the pitch to the multiplier of 4, instead of the width. This patch corrects it. For instance, a 480p video, whose width and pitch are 854 and 896 respectively, is excluded for NV12 plane so far. Changes since v1: - Removed check for NV12 buffer dimensions since additional checks are done for viewport size in intel_sprite.c Signed-off-by: Dongseong Hwang <dongseong.hwang@intel.com> Signed-off-by: P Raviraj Sitaram <raviraj.p.sitaram@intel.com> Cc: Chandra Konduru <chandra.konduru@intel.com> Cc: Vidya Srinivas <vidya.srinivas@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1545208152-22658-1-git-send-email-raviraj.p.sitaram@intel.com
2019-01-25drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to ↵ndesaulniers@google.com
undefined SW FP routines arch/x86/Makefile disables SSE and SSE2 for the whole kernel. The AMDGPU drivers modified in this patch re-enable SSE but not SSE2. Turn on SSE2 to support emitting double precision floating point instructions rather than calls to non-existent (usually available from gcc_s or compiler_rt) floating point helper routines. Link: https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html Link: https://github.com/ClangBuiltLinux/linux/issues/327 Cc: stable@vger.kernel.org # 4.19 Reported-by: S, Shirish <Shirish.S@amd.com> Reported-by: Matthias Kaehlcke <mka@google.com> Suggested-by: James Y Knight <jyknight@google.com> Suggested-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Matthias Kaehlcke <mka@chromium.org> Tested-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: support Vega12 retrieving and setting ppfeaturesEvan Quan
Enable retrieving and setting ppfeatures on Vega12. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: support Vega12 SOCclk and DCEFclk dpm level settingsEvan Quan
Enable SOCclk and DCEFclk dpm level retrieving and setting on Vega12. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: support Vega10 retrieving and setting ppfeaturesEvan Quan
Enable retrieving and setting ppfeatures on Vega10. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: support Vega10 SOCclk and DCEFclk dpm level settingsEvan Quan
Enable SOCclk and DCEFclk dpm level retrieving and setting on Vega10. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: avoid frequent metrics table exportEvan Quan
That's unnecessary. Also it makes more sense to show all the clocks on one metrics table export. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: correct Vega20 gfxclk readout under DSEvan Quan
Current implementation cannot report the correct gfxclk under DS. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Connect dig_fe to otg directly instead of calling bioshersen wu
[Why] After call bios table crtc_source_select, dal will program fmt again. The bios table program dig_source_select and other fmt register for bios usage which is redundancy and uncessary. [How] Program dig_soruce_select register directly Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: 3.2.15Steven Chiu
Signed-off-by: Steven Chiu <steven.chiu@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: take dpms_off into account for edp turn off logicEric Yang
[why] Previously we incorrectly skipped backlight control when stream is present but dpms_off = true. This causes backlight to remain on in the we boot up or resume into a external display only configuration where VBIOS posted on the eDP. [How] Add dpms_off into the condition for edp need to turn off. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25revert "drm/amd/display: Add condition to sync eDP SW status and HW status"Eric Yang
[Why] This change causes regression for S4 resume where gamma is not programmed. The change incorrectly updates the requested dpms_off state. This reverts commit d2b1d6bbc56afab8ebae9d52d7ca0ea3569bd600. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Adjust ABM 2.2 contrast parametersJosip Pavic
[Why] Improved contrast in ABM 2.2 is desired [How] Increase the contrast factor for ABM levels 2, 3 and 4 Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Default to linear output gammaKrunoslav Kovac
[Why] Our output TF calculation doesn't work if no user-specified gamma correction. Normally, user provides this, but driver sohuld just assume default (linear) gamma otherwise. [How] Remove output TF dependency on user gamma being provided. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Fix use of uninitialized unionJohn Barberiz
[Why] An uninitialized variable would randomly initialize to a large value. This caused enough delay to fail DP Compliance Test 400.2.1. [How] Initialize the variable. Signed-off-by: John Barberiz <John.Barberiz@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Create switching mechanism for ABM 2.2Josip Pavic
[Why] Need method of detecting which version of the DMCU FW is loaded and load the appropriate iRAM. [How] Create definition for ABM 2.2 iRAM, and load it if the DMCU FW version number matches the ABM 2.2 version; otherwise load ABM 2.1 iRAM. Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Update DMCU versioning mechanismJosip Pavic
[Why] Current date based versioning doesn't tell us about feature version and build version, and is not useful for debug. [How] Add versioning based on feature and build Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Know what a pageflip isDavid Francis
[Why] We were assuming that any commit with allow_modeset == false was a pageflip. This was against drm intention and only worked by sheer luck [How] A pageflip is the change from one framebuffer to another Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Perform plane updates only when neededDavid Francis
[Why] Our old logic: if pageflip, update freesync and plane address. Otherwise, update everything. This over-updated on non-pageflip cases, and it failed to update if pageflip and non-pageflip changes occurred on the same commit [How] Update flip_addrs on pageflips. Update scaling_info when it changes. Update color fields on color changes. Updates plane_info always because we don't have a good way of knowing when it needs to be updated. Unfortunately, this means that every stream commit involves two calls into DC. In particular, on pageflips there is a second, pointless update that changes nothing but costs several microseconds (about a 50% increase in time taken). The update is fast, but there are comparisons and some useless programming. Leave TODOs indicating dissatisfaction. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Call into DC once per multiplane flipDavid Francis
[Why] amdgpu_dm_commit_planes was performing multi-plane flips incorrectly: It waited for vblank once per flipped plane It prepared flip ISR and acquired the corresponding vblank ref once per plane, although it closed ISR and put the ref once per crtc It called into dc once per flipped plane, duplicating some work [How] Wait for vblank, get vblank ref, prepare flip ISR, and call into DC only once, and only if there is a pageflip Make freesync continue to update planes even if vrr information has already been changed Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Simplify underscan and ABM commitDavid Francis
[Why] Underscan and ABM are connector properties but require updates to DC stream state. Previously, on updates to these properties the affected stream and all its planes were committed. This is unnecessary; only a few fields on the stream need to be changed. [How] If scaling or ABM have changed, change the stream and create a stream update with those changes. Call DC with only those fields. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Let updates with no scaling changes be fastDavid Francis
[Why] DC was assuming that any surface_update->scaling_info meant the update was at least medium. However, if nothing has changed there is no scaling to program, so there is no problem with the update being fast [How] If every update flag is not set, the update is fast Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Introduce DC VM interfaceEryk Brol
Virtual memory allows display to support flipping to surfaces which are not allocated contiguously in memory with physical addresses, instead a 1-4 level page table is used. This is beneficial because it allows the scattering of large surfaces to improve memory efficiency and security. Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Restructure DCN10 hubbubEryk Brol
[Why] Change DCN10 hubbub to use hubbub as a base and allow all future DCN hubbubs to do the same instead of using DCN10_hubbub. This increases readability and doesn't require future hubbubs to inherit anything other than the base hubbub struct. [How] Create separate DCN10_hubbub struct which uses the hubbub struct as a base. Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: fix eDP fast bootup for pre-raven asichersen wu
[Why] For fastboot, Bios will light up eDP before SW driver is loaded. SW driver will check if eDP is lit by bios through reading the BIOS_SCRATCH_3 register. If lit, SW driver will not power down eDP power and phy to save time. Definition of BIOS_SCRATCH_3 are missing for pre-raven asic. This causes eDP fast boot to not work property. For some eDP panels, even if dp tx sends NoVideoStream_flag =1 and dpcd 0x600=2, eDP rx may not handle properly. This may cause a short flash on screen. [How] Add definition of BIOS_SCRATCH_3 for all asic Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Yongqiang Sun <yongqiang.sun@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/sched: Rework HW fence processing.Andrey Grodzovsky
Expedite job deletion from ring mirror list to the HW fence signal callback instead from finish_work, together with waiting for all such fences to signal in drm_sched_stop we garantee that already signaled job will not be processed twice. Remove the sched finish fence callback and just submit finish_work directly from the HW fence callback. v2: Fix comments. v3: Attach hw fence cb to sched_job v5: Rebase Suggested-by: Christian Koenig <Christian.Koenig@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/sched: Refactor ring mirror list handling.Andrey Grodzovsky
Decauple sched threads stop and start and ring mirror list handling from the policy of what to do about the guilty jobs. When stoppping the sched thread and detaching sched fences from non signaled HW fenes wait for all signaled HW fences to complete before rerunning the jobs. v2: Fix resubmission of guilty job into HW after refactoring. v4: Full restart for all the jobs, not only from guilty ring. Extract karma increase into standalone function. v5: Rework waiting for signaled jobs without relying on the job struct itself as those might already be freed for non 'guilty' job's schedulers. Expose karma increase to drivers. v6: Use list_for_each_entry_safe_continue and drm_sched_process_job in case fence already signaled. Call drm_sched_increase_karma only once for amdgpu and add documentation. v7: Wait only for the latest job's fence. Suggested-by: Christian Koenig <Christian.Koenig@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: enable MGPU fan boost feature on Vega10Evan Quan
For those SKUs which support this feature only. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: support Vega10 fan table V3Evan Quan
MGPU fan boost related parameter is added. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: remove old CI DPM implementationAlex Deucher
The power smu7 powerplay code is much more robust and has been the default for a while now. Remove the old code. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/radeon: check if device is root before getting pci speed capsAlex Deucher
Check if the device is root rather before attempting to see what speeds the pcie port supports. Fixes a crash with pci passthrough in a VM. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109366 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: Add missing power attribute to APU checkAlex Deucher
Add missing power_average to visible check for power attributes for APUs. Was missed before. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-19 03:04:47 +0000