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Refactor, and move the tiling geometry functions to dispnv50/tile.h,
so they can be re-used by drm_panic.
No functional impact.
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241022185553.1103384-3-jfalempe@redhat.com
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Add support for ABGR2101010, used by the nouveau driver.
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241022185553.1103384-2-jfalempe@redhat.com
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CRTC creation uses drmm_crtc_init_with_planes(), which automatically
handles cleanup. However, an unnecessary call to drm_crtc_cleanup() is
still present in the vkms_output_init() error path.
Fixes: 99cc528ebe92 ("drm/vkms: Use drmm_crtc_init_with_planes()")
Signed-off-by: José Expósito <jose.exposito89@gmail.com>
Reviewed-by: Maíra Canal <mcanal@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241031183835.3633-1-jose.exposito89@gmail.com
Acked-by: Louis Chauvet <louis.chauvet@bootlin.com>
Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
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When remaining resources are being cleaned up on driver close,
outstanding VM mappings may result in resources being leaked, due
to an object reference loop, as shown below, with each object (or
set of objects) referencing the object below it:
PVR GEM Object
GPU scheduler "finished" fence
GPU scheduler “scheduled” fence
PVR driver “done” fence
PVR Context
PVR VM Context
PVR VM Mappings
PVR GEM Object
The reference that the PVR VM Context has on the VM mappings is a
soft one, in the sense that the freeing of outstanding VM mappings
is done as part of VM context destruction; no reference counts are
involved, as is the case for all the other references in the loop.
To break the reference loop during cleanup, free the outstanding
VM mappings before destroying the PVR Context associated with the
VM context.
Signed-off-by: Brendan King <brendan.king@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/8a25924f-1bb7-4d9a-a346-58e871dfb1d1@imgtec.com
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This adds a linked list of VM contexts which is needed for the next patch
to be able to correctly track VM contexts for destruction on file close.
It is only safe for VM contexts to be removed from the list and destroyed
when not in interrupt context.
Signed-off-by: Brendan King <brendan.king@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/e57128ea-f0ce-4e93-a9d4-3f033a8b06fa@imgtec.com
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Changes in Dynamic Range and Mastering infoframe
should not trigger a full modeset. Therefore, allow
fastset. DP SDP programming is already hooked up in the
fastset flow but HDMI AVI infoframe update is not, add it.
Any other infoframe that can be fastset should be added to
the helper intel_hdmi_fastset_infoframes().
v3:
- Create a wrapper intel_ddi_update_pipe_hdmi to stick to
uniform naming (Jani)
- Do not disable HDMI AVI infoframe if already disabled (Uma)
v2:
- Update HDMI AVI infoframe during fastset.
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241023044122.3889137-1-chaitanya.kumar.borah@intel.com
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We are currently seeing unexpected link trainings with several different
eDP panels. These are caused by these panels stating bad link status in
their dpcd registers. This can be observed by doing following test:
1. Boot up without Xe module loaded
2. Load Xe module with PSR disabled:
$ modprobe xe enable_psr=0
3. Read panel link status register
$ dpcd_reg read --offset 0x200e --count=1
0x200e: 00
4. Enable PSR, sleep for 2 seconds and disable PSR again:
$ echo 0x1 > /sys/kernel/debug/dri/0/i915_edp_psr_debug
$ echo "-1" > /sys/kernel/debug/dri/0000:00:02.0/xe_params/enable_psr
$ echo 0x0 > /sys/kernel/debug/dri/0/i915_edp_psr_debug
$ sleep 2
$ cat /sys/kernel/debug/dri/0/i915_edp_psr_status | grep status
$ echo 0x1 > /sys/kernel/debug/dri/0/i915_edp_psr_debug
Source PSR/PanelReplay status: DEEP_SLEEP [0x80310030]
5. Now read panel link status registers again:
$ dpcd_reg read --offset 0x200e --count=1
0x200e: 80
Workaround this by not trusting link status registers after PSR is enabled
until first short pulse interrupt is received.
v2:
- clear link_ok flag on pipe disable
- remove useless comment
- modify intel_dp_needs_link_retrain return statement
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241029122415.1789528-1-jouni.hogander@intel.com
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Currently, even though there is a bit to control FEC enable/disable
individually, the FEC Decode Enable sequence is sent by the SOC only
once TRANS_CONF enable is set. This ties the FEC enabling too tightly
to modeset and therefore cannot be re-issued (in case of failure)
without a modeset.
From PTL, FEC_DECODE_EN sequence can be sent to a DPRX independent
of TRANS_CONF enable. This allows us to re-issue an FEC_DECODE_EN
sequence without a modeset. Hence allowing us to have a retry
mechanism in case the DPRX does not respond with an FEC_ENABLE
within certain amount of time.
While at it, replace struct drm_i915_private with struct intel_display
v4:
- More code refactor [Jani]
- use struct intel_display [Jani]
- Optimize logging [Jani]
v3:
- Make the commit message more legible [Jani]
- Refactor code to re-use existing code [Jani]
- Do away with platform dependent FEC enable checks [Jani]
v2:
- Refactor code to avoid duplication and improve readability [Jani]
- In case of PTL, wait for FEC status directly after FEC enable [Srikanth]
- Wait for FEC_ENABLE_LIVE_STATUS to be cleared before
re-enabling FEC [Srikanth]
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241024061002.4085137-1-chaitanya.kumar.borah@intel.com
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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next
Backmerge Linus tree for some drm-fixes needed for msm and xe merges.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Add support for Exynos 7870 DECON in the Exynos 7 DECON driver.
Some Exynos 7 series SoCs (Exynos 7580 onwards) have different
register values. In order to address such changes, include a driver
data struct (named decon_data) so that correct base addresses and
shift values can be provided.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
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The DECON channels are not cleared properly as the windows aren't
shadow protected. When accompanied with an IOMMU, it pagefaults, and
the kernel panics.
Implement shadow protect/unprotect, along with a standalone update,
for channel clearing to properly take effect.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
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The clkdiv values are incorrect as ideal_clk is in kHz and the clock
rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Modify the functions to accept a pointer to struct decon_context
instead.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
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exynos_drm_crtc_wait_pending_update, exynos_drm_crtc_finish_update
are not used anymore.
Signed-off-by: Kwanghoon Son <k.son@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Replace 'initailization' with 'initialization' in the comment.
Signed-off-by: Shen Lichuan <shenlichuan@vivo.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Unfortunately the tooling doesn't check documents placed before funciton
prototypes. Such comments frequently become outdated, miss several
params, etc. Move documentation for the functions to be placed before
the actual function body, allowing 'make W=1' to actually check these
comments and report an error.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/622690/
Link: https://lore.kernel.org/r/20241102-dpu-docs-rework-v1-1-d735853fd6db@linaro.org
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fdget() is the first thing done in scope, all matching fdput() are
immediately followed by leaving the scope.
Reviewed-by: Christian Brauner <brauner@kernel.org>
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
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Move existing register definitions to mdss.xml and use generated defines
for registers access instead of hand-coding everything in the source
file.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/615312/
Link: https://lore.kernel.org/r/20240921-msm-mdss-ubwc-v1-2-411dcf309d05@linaro.org
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In preparation of adding more registers, move MDSS-related headers to
the separate top-level file.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/615310/
Link: https://lore.kernel.org/r/20240921-msm-mdss-ubwc-v1-1-411dcf309d05@linaro.org
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Move a call to dpu_plane_check_inline_rotation() to the
dpu_plane_atomic_check_sspp() function, so that the rot90 constraints
are checked for both SSPP blocks. Also move rotation field from struct
dpu_plane_state to struct dpu_sw_pipe_cfg.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/621485/
Link: https://lore.kernel.org/r/20241025-dpu-virtual-wide-v6-6-0310fd519765@linaro.org
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Split dpu_plane_atomic_check() function into two pieces:
dpu_plane_atomic_check_nosspp() performing generic checks on the pstate,
without touching the associated SSPP blocks,
and
dpu_plane_atomic_check_sspp(), which takes into account used SSPPs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/621484/
Link: https://lore.kernel.org/r/20241025-dpu-virtual-wide-v6-5-0310fd519765@linaro.org
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Max upscale / downscale factors are constant between platforms. In
preparation to adding support for virtual planes and allocating SSPP
blocks on demand move max scaling factors out of the HW catalog and
handle them in the dpu_plane directly. If any of the scaling blocks gets
different limitations, this will have to be handled separately, after
the plane refactoring.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/621481/
Link: https://lore.kernel.org/r/20241025-dpu-virtual-wide-v6-4-0310fd519765@linaro.org
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The virt_formats / virt_num_formats are not used by the current driver
and are not going to be used in future since formats for virtual planes
are handled in a different way, by forbidding unsupported combinations
during atomic_check. Drop those fields now.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/621479/
Link: https://lore.kernel.org/r/20241025-dpu-virtual-wide-v6-3-0310fd519765@linaro.org
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In preparation for virtualized planes support, move pstate->pipe
initialization from dpu_plane_reset() to dpu_plane_atomic_check(). In
case of virtual planes the plane's pipe will not be known up to the
point of atomic_check() callback.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/621477/
Link: https://lore.kernel.org/r/20241025-dpu-virtual-wide-v6-2-0310fd519765@linaro.org
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Use the drm_rect_fp_to_int() helper instead of using the hand-written
code.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/621476/
Link: https://lore.kernel.org/r/20241025-dpu-virtual-wide-v6-1-0310fd519765@linaro.org
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https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes
Driver Changes:
- Fix missing HPD interrupt enabling, bringing one PM refactor with it
(Imre / Maarten)
- Workaround LNL GGTT invalidation not being visible to GuC
(Matthew Brost)
- Avoid getting jobs stuck without a protecting timeout (Matthew Brost)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/tsbftadm7owyizzdaqnqu7u4tqggxgeqeztlfvmj5fryxlfomi@5m5bfv2zvzmw
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Starting with display version 13 the fuse bit to disable Display PM has
been removed.
v2: Bit removed starting with display version 13 (MattR)
v3: DG2 still uses this fuse bit (MattR)
Bspec: 50075, 69464
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030195507.2753404-1-clinton.a.taylor@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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The recent attempt to make the MediaTek DRM driver build for non-ARM
compile tests made the driver unbuildable for arm64 platforms. Since
this is used on both ARM and arm64 platforms, just drop the dependency
on ARM.
Fixes: d2db0b8fd70b ("drm/mediatek: Allow build with COMPILE_TEST=y")
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241029111309.737263-1-wenst@chromium.org
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
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Compile-testing random configurations leads to failures in
dcss-kms.c from a missing declaration:
drivers/gpu/drm/imx/dcss/dcss-kms.c:95:8: error: use of undeclared identifier 'drm_bridge_attach'
95 | ret = drm_bridge_attach(encoder, bridge, NULL,
| ^
drivers/gpu/drm/imx/dcss/dcss-kms.c:96:5: error: use of undeclared identifier 'DRM_BRIDGE_ATTACH_NO_CONNECTOR'
96 | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
| ^
Include the header directly.
Fixes: 004555a18d57 ("drm/imx/dcss: Allow build with COMPILE_TEST=y")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241028163527.2425783-1-arnd@kernel.org
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https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for v6.13:
All of the previous pull request, with MORE!
Core Changes:
- Update documentation for scheduler start/stop and job init.
- Add dedede and sm8350-hdk hardware to ci runs.
Driver Changes:
- Small fixes and cleanups to panfrost, omap, nouveau, ivpu, zynqmp, v3d,
panthor docs, and leadtek-ltk050h3146w.
- Crashdump support for qaic.
- Support DP compliance in zynqmp.
- Add Samsung S6E88A0-AMS427AP24 panel.
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/deeef745-f3fb-4e85-a9d0-e8d38d43c1cf@linux.intel.com
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The const MAX_BRIDGES is unused after the commit 4d1a1e4686bd ("drm/msm:
remove msm_drm_private::bridges field"), drop it now.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/622537/
Link: https://lore.kernel.org/r/20241031-dpu-move-topology-v1-3-8ffa8122d3b6@linaro.org
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The MAX_H_TILES_PER_DISPLAY const is only used by the DPU driver, move
it to the corresponding header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/622536/
Link: https://lore.kernel.org/r/20241031-dpu-move-topology-v1-2-8ffa8122d3b6@linaro.org
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The struct msm_display_topology is only used by the DPU driver. Remove
it from the global header and move it to DPU-specific header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/622534/
Link: https://lore.kernel.org/r/20241031-dpu-move-topology-v1-1-8ffa8122d3b6@linaro.org
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https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-fixes
Mediatek DRM Fixes - 20241028
1. Fix degradation problem of alpha blending
2. Fix color format MACROs in OVL
3. Fix get efuse issue for MT8188 DPTX
4. Fix potential NULL dereference in mtk_crtc_destroy()
5. Correct dpi power-domains property
6. Add split subschema property constraints
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20241028135846.3570-1-chunkuang.hu@kernel.org
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There may be a potential integer overflow issue in
_dpu_core_perf_calc_clk(). crtc_clk is defined as u64, while
mode->vtotal, mode->hdisplay, and drm_mode_vrefresh(mode) are defined as
a smaller data type. The result of the calculation will be limited to
"int" in this case without correct casting. In screen with high
resolution and high refresh rate, integer overflow may happen.
So, we recommend adding an extra cast to prevent potential
integer overflow.
Fixes: c33b7c0389e1 ("drm/msm/dpu: add support for clk and bw scaling for display")
Signed-off-by: Zichen Xie <zichenxie0106@gmail.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/622206/
Link: https://lore.kernel.org/r/20241029194209.23684-1-zichenxie0106@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.12-2024-10-31:
amdgpu:
- DCN 3.5 fix
- Vangogh SMU KASAN fix
- SMU 13 profile reporting fix
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241031151539.3523633-1-alexander.deucher@amd.com
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Follow the established symbol name pattern and rename platform data
structures.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/622213/
Link: https://lore.kernel.org/r/20241029-msm-dp-rename-v2-3-13c5c03fad44@linaro.org
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Follow the estalished prefix and rename eDP bridge symbols to use
msm_edp_ prefix, moving the edp to the end of the symbol name.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/622210/
Link: https://lore.kernel.org/r/20241029-msm-dp-rename-v2-2-13c5c03fad44@linaro.org
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For historical reasons a lot of symbols in the MSM DisplayPort driver
used the generic dp_ prefix. Perform a mass-rename of those symbols to
use msm_dp prefix.
Basically this is a result of the following script:
sed drivers/gpu/drm/msm/dp/* -i -e 's/\<dp_/msm_dp_/g'
sed drivers/gpu/drm/msm/dp/* -i -e 's/"msm_dp_/"dp_/g'
sed drivers/gpu/drm/msm/dp/* -i -e 's/msm_\(dp_sdp_header\|dp_sdp\)\>/\1/g'
Yes, this also results in renaming of several struct fields in addition
to renaming the structs and functions, but I think the simple solution
is better than the more complex one.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202410250305.UHKDhtxy-lkp@intel.com/
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/622211/
Link: https://lore.kernel.org/r/20241029-msm-dp-rename-v2-1-13c5c03fad44@linaro.org
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From LNL onwards there is a new hardware feature, which
allows to detect if the driver wrongly allocated DBuf
entries and they happen to overlap. If enabled this will
cause a specific interrupt to occur.
We now handle it in the driver, by writing correspondent
error message to kernel log.
v2: Initialize dbuf overlap flag in runtime_defaults (Jani Nikula)
v3: Unmask the overlap detection interrupt (Uma)
v4: use display over i915 (Jani Nikula)
v5: Use display instead of dev_priv (Jani Nikula)
v6: rebased to resolve merge conflicts
Bspec: 69450, 69464
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030103319.207235-1-vinod.govindapillai@intel.com
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At least the i-tec USB-C Nano 2x Display Docking Station (containing a
Synaptics MST branch device) requires the driver to update the source
OUI DPCD registers to expose its DSC capability. Accordingly update the
OUI for all sink types (besides eDP where this has been done already).
v2: Rebased on latest patch version.
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11776
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025160259.3088727-9-imre.deak@intel.com
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The DP sink's capabilities, like DSC, may depend on the source OUI
written to the sink. On eDP this OUI value could have been reset before
the detection started if the panel power on it got disabled. Make sure
the OUI is re-written at the beginning of detection in this case, before
the sink capabilities are read out.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025160259.3088727-8-imre.deak@intel.com
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The eDP sink's capabilities, like DSC, may depend on the source OUI
written to the sink, so ensure the OUI is written before reading out the
capabilities.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025160259.3088727-7-imre.deak@intel.com
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Reuse intel_dp_detect_dsc_caps() which already checks for the source's
DSC cap and retrieves the DPCD version from the DPRX caps.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025160259.3088727-6-imre.deak@intel.com
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While updating the source OUI on the sink the driver should avoid
writing the OUI if it's already up-to-date to prevent the sink from
resetting itself in response to the update. On eDP - the only output
type where the OUI was updated so far - the driver ensured this by
comparing the current source OUI DPCD register values with the expected
Intel OUI value, skipping the update in case of a match. On some non-eDP
sinks - at least on Synaptics branch devices - this method doesn't work,
since the source OUI DPCD registers read back as all 0, even after
updating the registers.
Handle the above kind of sinks by tracking when the OUI was updated and
so should be valid, regardless of what the DPCD registers contain.
eDP sinks reset the written source OUI value when the panel power is
disabled, invalidate the OUI state accordingly.
This is required by a follow-up patch updating the source OUI for
non-eDP sink types as well.
v2: Fix setting intel_dp::oui_valid=true, if the DPCD register contains
already the expected value.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025160259.3088727-5-imre.deak@intel.com
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If the source OUI DPCD register value matches the expected Intel OUI
value, the write timestamp doesn't get updated leaving it at the 0
initial value if the OUI wasn't written before. This can lead to an
incorrect wait duration in intel_dp_wait_source_oui(), since jiffies is
not inited to 0 in general (on a 32 bit system INITIAL_JIFFIES is set to
5 minutes ahead of wrap-around). Fix this by intializing the write
timestamp in the above case as well.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025160259.3088727-4-imre.deak@intel.com
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The sink's capabilities, like the DSC caps, depend on the source OUI
written to the sink's DPCD registers and so this OUI value should be
valid for the whole duration of the detection. An eDP sink will reset
this OUI value when the panel power is disabled, so prevent the
disabling - happening by default after a 1 sec idle period - for the
whole duration of detection.
v2: Update the documentation for intel_pps_on(). (Jani)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025160259.3088727-3-imre.deak@intel.com
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Make sure that a DP connector detection doesn't happen in parallel
with an ongoing modeset on the connector. The reasons for this are:
- Besides reading the capabilities, EDID etc. the detection may change
the state of the sink (via the AUX bus), for instance by setting the
LTTPR mode or the source OUI (the latter introduced by an upcoming
patch). It's better to avoid such changes affecting an onging modeset
in any way.
- During a modeset's link training any access to DPCD registers, besides
the registers used for link training should be avoided, at least in
the LTTPR non-transparent and transparent link training modes.
Such asynchronous accesses - besides connector detection - can also
happen via the AUX device node for instance, for those a parallel
modeset will have to be avoided in a similar way to the change in this
patch. (A topic for a follow-up change.)
- The source OUI written to an eDP sink is valid only while the panel
power is enabled. A modeset on eDP will enable/disable the panel power
synchronously; this should be prevented in the middle of the connector
detection, to ensure a consistent sink state (which depends on the
source OUI) for the whole duration of detection. The panel power could
still get disabled during detection after an idle period (1 sec), this
will be prevented by the next patch.
v2: (Ville)
- s/wait_for_crtc_hw_done/wait_for_connector_hw_done
- Get drm_device using an intel_display instead of drm_i915_private ptr.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025160259.3088727-2-imre.deak@intel.com
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Short circuiting TDR on jobs not started is an optimization which is not
required. On LNL we are facing an issue where jobs do not get scheduled
by the GuC if it misses a GGTT page update. When this occurs let the TDR
fire, toggle the scheduling which may get the job unstuck, and print a
warning message. If the TDR fires twice on job that hasn't started,
timeout the job.
v2:
- Add warning message (Paulo)
- Add fixes tag (Paulo)
- Timeout job which hasn't started after TDR firing twice
v3:
- Include local change
v4:
- Short circuit check_timeout on job not started
- use warn level rather than notice (Paulo)
Fixes: 7ddb9403dd74 ("drm/xe: Sample ctx timestamp to determine if jobs have timed out")
Cc: stable@vger.kernel.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025214330.2010521-2-matthew.brost@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit 35d25a4a0012e690ef0cc4c5440231176db595cc)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
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On LNL without a mmio read before a GGTT invalidate the GuC can
incorrectly read the GGTT scratch page upon next access leading to jobs
not getting scheduled. A mmio read before a GGTT invalidate seems to fix
this. Since a GGTT invalidate is not a hot code path, blindly do a mmio
read before each GGTT invalidate.
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: stable@vger.kernel.org
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Reported-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3164
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241023221200.1797832-1-matthew.brost@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit 5a710196883e0ac019ac6df2a6d79c16ad3c32fa)
[ Fix conflict with mmio vs gt argument ]
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
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