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2021-01-26drm/i915: Extract intel_crtc_dbuf_weights()Ville Syrjälä
Extract the code to calculate the weights used to chunk up the dbuf between pipes. There's still extra stuff in there that shouldn't be there and must be moved out, but that requires a bit more state to be tracked in the dbuf state. v2: Keep crtc_state->wm.skl.ddb Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-7-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Add pipe ddb entries into the dbuf stateVille Syrjälä
The dbuf state will be where we collect all the inter-pipe dbuf allocation stuff. Start by adding the actual per-pipe ddb entries there. Originally the plan was to move them there outright, but that no longer works as we're no longer guaranteed to have a dbuf state when it comes time to sanity check the ddb overlaps in skl_commit_modeset_enables(). I think when I wrote this originally we did the watermark/ddb calculation last, and so we couldn't have any crtcs in the state w/o also having the dbuf state. But that has since changed and we do the watermark/ddb calculation much earlier, and thus it is now possible to commit crtcs w/o a dbuf state. So we keep another copy of the information in the crtc state. v2: Rebase v3: Duplicate the entries instead of moving Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-6-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Introduce skl_ddb_entry_for_slices()Ville Syrjälä
Generalize icl_get_first_dbuf_slice_offset() into something that just gives us the start+end of the dbuf chunk covered by the specified slices as a standard ddb entry. Initial idea was to use it during readout as well, but we shall see. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-5-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Introduce intel_dbuf_slice_size()Ville Syrjälä
Put the code into a function with a descriptive name. Also relocate the code a bit help future work. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-4-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Pass the crtc to skl_compute_dbuf_slices()Ville Syrjälä
skl_compute_dbuf_slices() has no use for the crtc state, so just pass the crtc itself. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-3-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Extract intel_crtc_ddb_weight()Ville Syrjälä
skl_ddb_get_pipe_allocation_limits() doesn't care how the weights for distributing the ddb are caclculated for each pipe. Put that calculation into a separate function so that such mundane details are hidden from view. v2: s/adjusted_mode/pipe_mode/ Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-2-ville.syrjala@linux.intel.com
2021-01-25drm/i915: Fix vblank evasion with vrrVille Syrjälä
With vrr enabled the hardware no longer latches the registers automagically at vblank start. The point at which it will do the latching even when no push has been sent is the vmax decision boundary. That is the thing we need to evade to avoid our register latching to get split between two frames. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-18-manasi.d.navare@intel.com
2021-01-25drm/i915: Fix vblank timestamps with VRRVille Syrjälä
To get sensible vblank timestamping behaviour we need to feed the vmax based timings to the vblank code, otherwise it'll chop off the scanline counter when it exceeds the minumum vtotal. Additionally with VRR we have three cases to consider when we generate the vblank timestamp: 1) we are in vertical active -> nothing special needs to be done, just return the current scanout position and the core will calculate the timestamp corresponding to the past time when the current vertical active started 2) we are in vertical blank and no push has been sent -> the hardware will keep extending the vblank presumably to its maximum length, so we make the timestmap match the expected time when the max length vblank will end. Since the timings used for this are now based on vmax nothing special actually needs to be done 3) we are in vblank and a push has been sent so the vblank is about to terminate -> presumably we want the timestmap to accurately reflect when the vblank will terminate, so we use the sampled frame timestamp vs. current timestamp to guesstimate how far along the vblank exit we are, and then we adjust the reported scanout position accordingly so that the core will see that the vblank is close to ending. v2: * Fix the else if (use_scanline_Counter) (Manasi) Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-17-manasi.d.navare@intel.com
2021-01-25drm/i915: Add vrr state dumpVille Syrjälä
Dump vrr state alongside everything else. Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-16-manasi.d.navare@intel.com
2021-01-25drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä
With VRR the earliest the registers can get latched are at flipline decision boundary, calculate that as vrr_vmin_vblank_start() and the latest the regsiters can get latched are vmax decision boundary calculate that as vrr_vmax_vblank_start() v2: * Remove TODO and adjust extra scanline const (Manasi) Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-15-manasi.d.navare@intel.com
2021-01-25drm/i915/display: Add HW state readout for VRRManasi Navare
This functions gets the VRR config from the VRR registers to match the crtc state variables for VRR. v2: * Rebase (Manasi) * Use HAS_VRR (Jani N) v3: * Get pipeline_full, flipline (Ville) Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-14-manasi.d.navare@intel.com
2021-01-25drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare
If VRR is enabled, the sink should ignore MSA parameters and regenerate incoming video stream without depending on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN bit if VRR is enabled. Reset this bit on VRR disable. v2: * ACtually set the dpcd msa ignore bit (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-13-manasi.d.navare@intel.com
2021-01-25drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare
This patch disables the VRR enable and VRR PUSH bits in the HW during commit modeset disable sequence. Thsi disable will happen when the port is disabled or when the userspace sets VRR prop to false and requests to disable VRR. v2: * Use intel_de_rmw (Jani N) v3: * Remove rmw (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-12-manasi.d.navare@intel.com
2021-01-25drm/i915/display/vrr: Send VRR push to flip the frameManasi Navare
VRR achieves vblank stretching using the HW PUSH functionality. So once the VRR is enabled during modeset then for each flip request from userspace, in the atomic tail pipe_update_end() we need to set the VRR push bit in HW for it to terminate the vblank at configured flipline or anytime after flipline or latest at the Vmax. The HW clears the PUSH bit after the double buffer updates are completed. v2: * Move send push to after irq en (Manasi) * Call send push unconditionally (Jani N) v3: * Stall w.r.t Vrr vmax (Manasi, Gary Smith) v4: * Remove the rmw (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Gary Smith <gary.k.smith@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-11-manasi.d.navare@intel.com
2021-01-25drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare
This patch computes the VRR parameters from VRR crtc states and configures them in VRR registers during CRTC enable in the modeset enable sequence. v2: * Remove initialization to 0 (Jani N) * Use correct pipe %c (Jani N) v3: * Remove debug prints (Ville) * Use cpu_trans instead of pipe for TRANS_VRR regs (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-10-manasi.d.navare@intel.com
2021-01-25drm/i915: Rename VRR_CTL reg fieldsVille Syrjälä
Give the pipeline full line count bits more descriptive names Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-9-manasi.d.navare@intel.com
2021-01-25drm/i915/display: VRR + DRRS cannot be enabled togetherVille Syrjälä
If VRR is enabled, DRRS cannot be enabled, so make this check in atomic check. Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-8-manasi.d.navare@intel.com
2021-01-25drm/i915/display/dp: Do not enable PSR if VRR is enabledManasi Navare
Even though our HW supports PSR + VRR, the available panels do not work reliably with PSR and VRR together. So if user requested VRR and is supported by HW enable that and do not enable PSR in that case. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-7-manasi.d.navare@intel.com
2021-01-25drm/i915/display/dp: Compute VRR state in atomic_checkManasi Navare
This forces a complete modeset if vrr drm crtc state goes from enabled to disabled and vice versa. This patch also computes vrr state variables from the mode timings and based on the vrr property set by userspace as well as hardware's vrr capability. v2: *Rebase v3: * Vmin = max (vtotal, vmin) (Manasi) v4: * set crtc_state->vrr.enable = 0 for disable request v5: * drm_dbg_kms, squash crtc states def patch (Jani N) v6: * Move vrr modeset check to separate function (Jani N) v7: * Ville's fixes - vmin, vmax rename, fix rounding dir * Add pipeline full, flipline to crtc state * Pass conn state to vrr_compute_config (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-6-manasi.d.navare@intel.com
2021-01-25drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()Ville Syrjälä
Extract intel_crtc_scanlines_since_frame_timestamp() from __intel_get_crtc_scanline_from_timestamp(). We'll reuse this for VRR vblank timestamps. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-5-manasi.d.navare@intel.com
2021-01-25drm/i915: Extract intel_mode_vblank_start()Ville Syrjälä
We want to calculate the vblank_start for vblank evasion differently for vrr. To make that nicer lets first extract the current non-vrr case to a helper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-4-manasi.d.navare@intel.com
2021-01-25drm/i915: Store framestart_delay in dev_privVille Syrjälä
The vrr calculations will need to know the framestart delay value we use. Currently we program it always to zero, but should that change we probably want to stash it somewhere. Could stick it into the crtc_state I suppose, but since we never change it let's just stuff it into dev_priv for now. v2: * Rebase on drm-tip (Manasi) v3: * Framestart_delay as 1 - 4 to align with HW Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-3-manasi.d.navare@intel.com
2021-01-25drm/i915/display/dp: Attach and set drm connector VRR propertyAditya Swarup
This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v8: * Use HAS_VRR, remove drm_conn declaration (Jani N) * Fix typos in Comment (Jani N) v7: * Move the helper to separate file (Manasi) v6: * Remove unset of prop v5: * Fix the vrr prop not being set in kernel (Manasi) * Unset the prop on connector disconnect (Manasi) v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (Manasi) v2: * Just set this in intel_dp_get_modes instead of new hook (Jani) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-2-manasi.d.navare@intel.com
2021-01-25drm/i915/display/vrr: Create VRR file and add VRR capability checkManasi Navare
We create a new file for all VRR related helpers. Also add a function to check vrr capability based on platform support, DPCD bits and EDID monitor range. v2: * Remove author (Jani N) * Define HAS_VRR (Jani N) * Ensure intel_dp can be obtained from conn (Jani N) v3: * Fix the header indent (Manasi) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125200818.2015-1-manasi.d.navare@intel.com
2021-01-25drm/amd/display: Fix HDMI deep color output for DCE 6-11.Mario Kleiner
This fixes corrupted display output in HDMI deep color 10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3. It will hopefully also provide fixes for other DCE's up to DCE-11, assuming those will need similar fixes, but i could not test that for HDMI due to lack of suitable hw, so viewer discretion is advised. dce110_stream_encoder_hdmi_set_stream_attribute() is used for HDMI setup on all DCE's and is missing color_depth assignment. dce110_program_pix_clk() is used for pixel clock setup on HDMI for DCE 6-11, and is missing color_depth assignment. Additionally some of the underlying Atombios specific encoder and pixelclock setup functions are missing code which is in the classic amdgpu kms modesetting path and the in the radeon kms driver for DCE6/DCE8. encoder_control_digx_v3() - Was missing setup code wrt. amdgpu and radeon kms classic drivers. Added here, but untested due to lack of suitable test hw. encoder_control_digx_v4() - Added missing setup code. Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color output at 10 bpc and 12 bpc. Note that encoder_control_digx_v5() has proper setup code in place and is used, e.g., by DCE-11.2, but this code wasn't used for deep color setup due to the missing cntl.color_depth setup in the calling function for HDMI. set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon kms. Added here, but untested due to lack of hw. set_pixel_clock_v6() - Missing setup code added. Successfully tested on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI deep color output with 10 bpc or 12 bpc. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/amd/display: Fix 10/12 bpc setup in DCE output bit depth reduction.Mario Kleiner
In set_clamp(), the comments and definitions for the COLOR_DEPTH_101010 and COLOR_DEPTH_121212 cases directly contradict the code comment which explains how this should work, whereas the COLOR_DEPTH_888 case is consistent with the code comments. Comment says the bitmask should be chosen to align to the top-most 10 or 12 MSB's on a 14 bit bus, but the implementation contradicts that: 10 bit case sets a mask for 12 bpc clamping, whereas 12 bit case sets a mask for 14 bpc clamping. Note that during my limited testing on DCE-8.3 (HDMI deep color) and DCE-11.2 (DP deep color), this didn't have any obvious ill effects, neither did fixing it change anything obvious for the better, so this fix may be inconsequential on DCE, and just reduce the confusion of innocent bystanders when reading the code and trying to investigate problems with 10 bpc+ output. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25amdgpu: fix clang build warningArnd Bergmann
clang warns about the -mhard-float command line arguments on architectures that do not support this: clang: error: argument unused during compilation: '-mhard-float' [-Werror,-Wunused-command-line-argument] Move this into the gcc-specific arguments. Fixes: e77165bf7b02 ("drm/amd/display: Add DCN3 blocks to Makefile") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/amd/display: Fix a potential NULL dereferenceDan Carpenter
The debug printk dereferences "link->link_enc" before we have ensured that it is non-NULL. Fix this potential NULL derefence by moving the printk after the check. Fixes: 64ff0882426e56 ("drm/amd/display: Log link/connector info provided in BIOS object table") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/amd/display: change license of color_table.cJonathan Gray
Change the license of color_table.c to match color_table.h granting permission to modify and distribute. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/amdgpu: Fix masking binary not operator on two mask operationsColin Ian King
Currently the ! operator is incorrectly being used to flip bits on mask values. Fix this by using the bit-wise ~ operator instead. Addresses-Coverity: ("Logical vs. bitwise operator") Fixes: 3c9a7b7d6e7520 ("drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3") Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/amd/pm: store and reinstate swsmu user power configurationsArunpravin
store swsmu user power configurations which include power limit, clock frequencies, fan speed and fan mode on suspend and reinstate on resume. V2: Addressed Lijo's review comments added a function to set clock interdependencies add check on fan control mode to reapply fan speed V3: Addressed review comments from Alex moved store logic and reinstate function call into swSMU V4: added a logic to keep off storing configurations in suspend V5: Addressed review comments from Lijo add a restore flag give restore priority to mclk comparing fclk and socclk Signed-off-by: Arunpravin <Arunpravin.PaneerSelvam@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/amd/amdgpu: add error handling to amdgpu_virt_read_pf2vf_dataJingwen Chen
[Why] when vram lost happened in guest, try to write vram can lead to kernel stuck. [How] When the readback data is invalid, don't do write work, directly reschedule a new work. Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Monk Liu<monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/amd/display: fix 64-bit division issue on 32-bit OSLang Yu
Replace "/" with div_u64 for 32-bit OS. On 32-bit OS, the use of "/" for 64-bit division will cause build error, i.e. "__udivdi3/__divdi3 undefined!". Fixes: ea7154d8d9fb26 ("drm/amd/display: Update dcn30_apply_idle_power_optimizations() code") Signed-off-by: Lang Yu <Lang.Yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25Revert "drm/amd/display: Tune min clk values for MPO for RV"Pratik Vishwakarma
This reverts commit 57eeaf47a613c67d0380cf0afad73d8f52df2670. Original issue of flash line when MPO enabled on idle screen was fixed by raising clocks. This had negative effect of extra power being drained. With the upstream commit 9d03bb102028 ("drm/amd/display: disable dcn10 pipe split by default") flash line issue was fixed and had positive effect for battery life. Hence this patch is no more required. Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/amdgpu: race issue when jobs on 2 ring timeoutHorace Chen
Fix a racing issue when jobs on 2 rings timeout simultaneously. If 2 rings timed out at the same time, the amdgpu_device_gpu_recover will be reentered. Then the adev->gmc.xgmi.head will be grabbed by 2 local linked list, which may cause wild pointer issue in iterating. lock the device earily to prevent the node be added to 2 different lists. also increase karma for the skipped job since the job is also timed out and should be guilty. Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/amdgpu: Make contiguous pinning optionalFelix Kuehling
Enable pinning of VRAM without forcing it to be contiguous. When memory is already pinned, make sure it's contiguous if requested. Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-25drm/gma500: Get rid of duplicate NULL checksAndy Shevchenko
Since GPIOs are optional we don't need to repeat checks that are done in the GPIO API. Remove them for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-25drm/gma500: Convert to use new SCU IPC APIAndy Shevchenko
Convert the GMA500 driver to use the new SCU IPC API. This allows us to get rid of the duplicate PMC IPC implementation which is now covered in SCU IPC driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-25drm/vc4: Correct POS1_SCL for hvs5Dom Cobley
Fixes failure with 4096x1080 resolutions [ 284.315379] WARNING: CPU: 1 PID: 901 at drivers/gpu/drm/vc4/vc4_plane.c:981 vc4_plane_mode_set+0x1374/0x13c4 [ 284.315385] Modules linked in: ir_rc5_decoder rpivid_hevc(C) bcm2835_codec(C) bcm2835_isp(C) bcm2835_mmal_vchiq(C) bcm2835_gpiomem v4l2_mem2mem videobuf2_dma_contig videobuf2_memops videobuf2_v4l2 videobuf2_common videodev mc cdc_acm xpad ir_rc6_decoder rc_rc6_mce gpio_ir_recv fuse [ 284.315509] CPU: 1 PID: 901 Comm: kodi.bin Tainted: G C 5.10.7 #1 [ 284.315514] Hardware name: BCM2711 [ 284.315518] Backtrace: [ 284.315533] [<c0cc5ca0>] (dump_backtrace) from [<c0cc6014>] (show_stack+0x20/0x24) [ 284.315540] r7:ffffffff r6:00000000 r5:68000013 r4:c18ecf1c [ 284.315549] [<c0cc5ff4>] (show_stack) from [<c0cca638>] (dump_stack+0xc4/0xf0) [ 284.315558] [<c0cca574>] (dump_stack) from [<c022314c>] (__warn+0xfc/0x158) [ 284.315564] r9:00000000 r8:00000009 r7:000003d5 r6:00000009 r5:c08cc7dc r4:c0fd09b8 [ 284.315572] [<c0223050>] (__warn) from [<c0cc67ec>] (warn_slowpath_fmt+0x74/0xe4) [ 284.315577] r7:c08cc7dc r6:000003d5 r5:c0fd09b8 r4:00000000 [ 284.315584] [<c0cc677c>] (warn_slowpath_fmt) from [<c08cc7dc>] (vc4_plane_mode_set+0x1374/0x13c4) [ 284.315589] r8:00000000 r7:00000000 r6:00001000 r5:c404c600 r4:c2e34600 [ 284.315596] [<c08cb468>] (vc4_plane_mode_set) from [<c08cc984>] (vc4_plane_atomic_check+0x40/0x1c0) [ 284.315601] r10:00000001 r9:c2e34600 r8:c0e67068 r7:c0fc44e0 r6:c2ce3640 r5:c3d636c0 [ 284.315605] r4:c2e34600 [ 284.315614] [<c08cc944>] (vc4_plane_atomic_check) from [<c0860504>] (drm_atomic_helper_check_planes+0xec/0x1ec) [ 284.315620] r9:c2e34600 r8:c0e67068 r7:c0fc44e0 r6:c2ce3640 r5:c3d636c0 r4:00000006 [ 284.315627] [<c0860418>] (drm_atomic_helper_check_planes) from [<c0860658>] (drm_atomic_helper_check+0x54/0x9c) [ 284.315633] r9:c2e35400 r8:00000006 r7:00000000 r6:c2ba7800 r5:c3d636c0 r4:00000000 [ 284.315641] [<c0860604>] (drm_atomic_helper_check) from [<c08b7ca8>] (vc4_atomic_check+0x25c/0x454) [ 284.315645] r7:00000000 r6:c2ba7800 r5:00000001 r4:c3d636c0 [ 284.315652] [<c08b7a4c>] (vc4_atomic_check) from [<c0881278>] (drm_atomic_check_only+0x5cc/0x7e0) [ 284.315658] r10:c404c6c8 r9:ffffffff r8:c472c480 r7:00000003 r6:c3d636c0 r5:00000000 [ 284.315662] r4:0000003c r3:c08b7a4c [ 284.315670] [<c0880cac>] (drm_atomic_check_only) from [<c089ba60>] (drm_mode_atomic_ioctl+0x758/0xa7c) [ 284.315675] r10:c3d46000 r9:c3d636c0 r8:c2ce8a70 r7:027e3a54 r6:00000043 r5:c1fbb800 [ 284.315679] r4:0281a858 [ 284.315688] [<c089b308>] (drm_mode_atomic_ioctl) from [<c086e9f8>] (drm_ioctl_kernel+0xc4/0x108) [ 284.315693] r10:c03864bc r9:c1fbb800 r8:c3d47e64 r7:c089b308 r6:00000002 r5:c2ba7800 [ 284.315697] r4:00000000 [ 284.315705] [<c086e934>] (drm_ioctl_kernel) from [<c086ee28>] (drm_ioctl+0x1e8/0x3a0) [ 284.315711] r9:c1fbb800 r8:000000bc r7:c3d47e64 r6:00000038 r5:c0e59570 r4:00000038 [ 284.315719] [<c086ec40>] (drm_ioctl) from [<c041f354>] (sys_ioctl+0x35c/0x914) [ 284.315724] r10:c2d08200 r9:00000000 r8:c36fa300 r7:befdd870 r6:c03864bc r5:c36fa301 [ 284.315728] r4:c03864bc [ 284.315735] [<c041eff8>] (sys_ioctl) from [<c0200040>] (ret_fast_syscall+0x0/0x28) [ 284.315739] Exception stack(0xc3d47fa8 to 0xc3d47ff0) [ 284.315745] 7fa0: 027eb750 befdd870 00000000 c03864bc befdd870 00000000 [ 284.315750] 7fc0: 027eb750 befdd870 c03864bc 00000036 027e3948 0281a640 0281a850 027e3a50 [ 284.315756] 7fe0: b4b64100 befdd844 b4b5ba2c b49c994c [ 284.315762] r10:00000036 r9:c3d46000 r8:c0200204 r7:00000036 r6:c03864bc r5:befdd870 [ 284.315765] r4:027eb750 Fixes: c54619b0bfb3 ("drm/vc4: Add support for the BCM2711 HVS5") Signed-off-by: Dom Cobley <popcornmix@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Tested-By: Lucas Nussbaum <lucas@debian.org> Tested-By: Ryutaroh Matsumoto <ryutaroh@ict.e.titech.ac.jp> Link: https://patchwork.freedesktop.org/patch/msgid/20210121105759.1262699-2-maxime@cerno.tech
2021-01-25drm/vc4: Correct lbm size and calculationDom Cobley
LBM base address is measured in units of pixels per cycle. That is 4 for 2711 (hvs5) and 2 for 2708. We are wasting 75% of lbm by indexing without the scaling. But we were also using too high a size for the lbm resulting in partial corruption (right hand side) of vertically scaled images, usually at 4K or lower resolutions with more layers. The physical RAM of LBM on 2711 is 8 * 1920 * 16 * 12-bit (pixels are stored 12-bits per component regardless of format). The LBM address indexes work in units of pixels per clock, so for 4 pixels per clock that means we have 32 * 1920 = 60K Fixes: c54619b0bfb3 ("drm/vc4: Add support for the BCM2711 HVS5") Signed-off-by: Dom Cobley <popcornmix@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Tested-By: Lucas Nussbaum <lucas@debian.org> Tested-By: Ryutaroh Matsumoto <ryutaroh@ict.e.titech.ac.jp> Link: https://patchwork.freedesktop.org/patch/msgid/20210121105759.1262699-1-maxime@cerno.tech
2021-01-25Merge tag 'v5.11-rc5' of ↵Dave Airlie
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next Backmerge v5.11-rc5 into drm-next to clean up a bunch of conflicts we are dragging around. Signed-off-by: Dave Airlie <airlied@redhat.com>
2021-01-22drm/i915/tgl: Add Clear Color support for TGL Render DecompressionRadhakrishna Sripada
Render Decompression is supported with Y-Tiled main surface. The CCS is linear and has 4 bits of data for each main surface cache line pair, a ratio of 1:256. Additional Clear Color information is passed from the user-space through an offset in the GEM BO. Add a new modifier to identify and parse new Clear Color information and extend Gen12 render decompression functionality to the newly added modifier. v2: Fix has_alpha flag for modifiers, omit CC modifier during initial plane config(Matt). Fix Lookup error. v3: Fix the panic while running kms_cube v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt) v5: Fix typos and wrap comments(Matt) v6: - Use format block descriptors to get the subsampling calculations for the CCS surface right. - Use helpers to convert between main and CCS surfaces. - Prevent coordinate checks for the CC surface. - Simplify reading CC value from surface map, add description of CC val layout. - Remove redundant ccval variable from skl_program_plane(). v7: - Move the CC value readout after syncing against any GPU write on the FB obj (Nanley, Chris) - Make sure the CC value readout works on platforms w/o struct pages (dGFX) and other non-coherent platforms wrt. CPU reads (none atm). (Chris) v8: - Rebase on the function param order change of i915_gem_object_read_from_page(). - Clarify code comment on the clear color value format and the required FB obj pinning/syncing by the caller. - Remove redundant variables in intel_atomic_prepare_plane_clear_colors(). v9: - Fix s/sizeof(&ccval)/sizeof(ccval)/ typo. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Cc: Nanley G Chery <nanley.g.chery@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210115213952.1040398-1-imre.deak@intel.com
2021-01-22drm/i915/gem: Add a helper to read data from a GEM object pageImre Deak
Add a simple helper to read data with the CPU from the page of a GEM object. Do the read either via a kmap if the object has struct pages or an iomap otherwise. This is needed by the next patch, reading a u64 value from the object (w/o requiring the obj to be mapped to the GPU). Suggested by Chris. v2 (Chris): - Sanitize the type and order of func params. - Avoid consts requiring too many casts. - Use BUG_ON instead of WARN_ON, simplify the conditions. - Fix __iomem sparse errors. - Leave locking/syncing/pinning up to the caller, require only that the caller has pinned the object pages. - Check for iomem backing store before reading via an iomap. v3: - Fix offset passed to io_mapping_map_wc() missing a mem.region.start delta. (Chris, Matthew) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.william.auld@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20210120213834.1435710-1-imre.deak@intel.com
2021-01-22drm/i915/hdcp: Fix uninitialized symbolAnshuman Gupta
Move (num_hdcp_streams > 0) condition to stream_encryption() code block, where it actually belongs. This fixes the static analysis error of uninitialized symbol 'ret'. v2: - return 0 as the return value is already checked. [Ankit] Cc: Ramalingam C <ramalingam.c@intel.com> Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120103032.15198-1-anshuman.gupta@intel.com
2021-01-22drm/i915/hdcp: Fix WARN_ON(data->k > INTEL_NUM_PIPES)Anshuman Gupta
Initialize no. of streams transmitted on a port to zero such that intel_hdcp_required_content_stream() can prepared the content stream after subsequemt attmept to enable hdcp after a HDCP failure. v2: - Initialize k at top level instead of else branch. [Jani] Cc: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210119064655.1605-2-anshuman.gupta@intel.com
2021-01-21drm/i915/dp: Don't use DPCD backlights that need PWM enable/disableLyude Paul
We haven't yet implemented support for backlights that need to be enabled/disabled via PWM instead of AUX, which means we'll break things if we enable DPCD backlight control on these machines. Luckily though since most of these machines work fine just using the plain PWM backlight controls anyway, there shouldn't be any issue with just leaving DPCD backlight controls disabled in such situations. This should fix the issues with PWM being left on that were being observed on fi-bdw-samus. Signed-off-by: Lyude Paul <lyude@redhat.com> Reviewed-by: "Ville Syrjälä" <ville.syrjala@linux.intel.com> Fixes: 4a8d79901d5b ("drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)") Testcase: igt/gem_exec_suspend/basic-s0 # fi-bdw-samus Cc: Lyude Paul <lyude@redhat.com> Cc: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210121183644.2627282-1-lyude@redhat.com
2021-01-22Merge tag 'drm-intel-gt-next-2021-01-21-1' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next Cross-subsystem Changes: - Includes gvt-gt-next-2021-01-18 + header check fix for GVT Driver Changes: - Fix for #2955: Clear potentially malicious register state before executing clear residuals security mitigation (Chris) - Fixes that lead to marking per-engine-reset as supported on Gen7 (Chris) - Remove per-client stats from debugfs/i915_gem_objects) (Tvrtko, Chris) - Add arbitration check before semaphore wait (Chris) - Apply interactive priority to explicit flip fences (Chris) - Make GEM errors non-fatal by default to help capturing logs during development (Chris) - Fix object page offset within a region in error capture (CQ, Matt A) - Close race between enable_breadcrumbs and cancel_breadcrumbs (Chris) - Almagamate clflushes on suspend/freeze to speed up S/R (Chris) - Protect used framebuffers from casual eviction (Chris) - Fix the sgt.pfn sanity check (Kui, Matt A) - Reduce locking around i915_request.lock and ctx->engines_mutex (Chris) - Simplify tracking for engine->fw_active and stats.active (Chris) - Constrain pool objects by mapping type (Chris, Matt A) - Use shrinkable status for unknown swizzle quirks (Chris) - Do not suspend bonded requests if one hangs (Chris) - Restore "Skip over completed active execlists" optimization (Chris) - Move stolen node into GEM object union (Chris) . Split gem_create into own file (Matt A) - Convert object_create into object_init in LMEM region code (Matt A) - Reduce test_and_set_bit to set_bit in i915_request_submit() (Chris) - Mark up protected uses of 'i915_request_completed' (Chris) - Remove extraneous inline modifiers (Chris) - Add function to define defaults for GuC/HuC enable (John) - Improve code locality by moving closer to single user (Matt A, Chris) - Compiler warning fixes (Matt A, Chris) - Selftest / CI improvements (Chris) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210121150747.GA58732@jlahtine-mobl.ger.corp.intel.com
2021-01-22Merge tag 'amd-drm-fixes-5.11-2021-01-21' of ↵Dave Airlie
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-5.11-2021-01-21: amdgpu: - Green Sardine fixes - Vangogh fixes - Renoir fixes - Misc display fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210121160129.3981-1-alexander.deucher@amd.com
2021-01-22Merge tag 'drm-intel-fixes-2021-01-21' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes drm/i915 fixes for v5.11-rc5: - HDCP fixes - PMU wakeref fix - Fix HWSP validity race - Fix DP protocol converter accidental 4:4:4->4:2:0 conversion for RGB Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87a6t2kzgb.fsf@intel.com
2021-01-21drm/i915: Unify the sanity checks for the buf trans tablesVille Syrjälä
Get rid of the "I like my random new style best" approach and unify the handling for the DDI buf trans table sanity checks once again. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201207203512.1718-2-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
generated by cgit (git 2.34.1) at 2025-09-13 15:01:32 +0000