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path: root/drivers/gpu
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2021-01-15Merge drm/drm-next into drm-intel-nextRodrigo Vivi
Syncing drm-intel-next and drm-intel-gt-next to unblock ADL enabling. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2021-01-16drm/i915: split fdi code out from intel_display.cDave Airlie
This just refactors out the fdi code to a separate file. Signed-off-by: Dave Airlie <airlied@redhat.com> [Jani: cleaned up intel_fdi.h a bit.] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f9d52c3d91f0973af308ede16e266fc9b753ecf9.1610622609.git.jani.nikula@intel.com
2021-01-16drm/i915: refactor pll code out into intel_dpll.cDave Airlie
This pulls a large chunk of the pll calculation code out of intel_display.c to a new file. One function makes sense to be an inline, otherwise this is pretty much a straight copy cover. Also all the remaining hooks for g45 and older end up the same now. Signed-off-by: Dave Airlie <airlied@redhat.com> [Jani: cleaned up intel_dpll.h a bit, de-duped intel_panel_use_ssc().] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/74b58e0572858b5d1734818ca594a23040d7d44f.1610622609.git.jani.nikula@intel.com
2021-01-16drm/i915: refactor some crtc code out of intel display. (v2)Dave Airlie
There may be more crtc code that can be pulled out, but this is a good start. v2: move plane before this. Signed-off-by: Dave Airlie <airlied@redhat.com> [Jani: cleaned up intel_crtc.h a bit.] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/eacbe964f90d189c5940c12af5e09091b37a19c3.1610622609.git.jani.nikula@intel.com
2021-01-15drm/i915/gt: Convert stats.active to plain unsigned intChris Wilson
As context-in/out is now always serialised, we do not have to worry about concurrent enabling/disable of the busy-stats and can reduce the atomic_t active to a plain unsigned int, and the seqlock to a seqcount. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210115142331.24458-3-chris@chris-wilson.co.uk
2021-01-15drm/i915/gt: Extract busy-stats for ring-schedulerChris Wilson
Lift the busy-stats context-in/out implementation out of intel_lrc, so that we can reuse it for other scheduler implementations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210115142331.24458-2-chris@chris-wilson.co.uk
2021-01-15drm/i915/gt: Drop atomic for engine->fw_active trackingChris Wilson
Since schedule-in/out is now entirely serialised by the tasklet bitlock, we do not need to worry about concurrent in/out operations and so reduce the atomic operations to plain instructions. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210115142331.24458-1-chris@chris-wilson.co.uk
2021-01-15drm/vkms: Fix missing kmalloc allocation failure checkColin Ian King
Currently the kmalloc allocation for config is not being null checked and could potentially lead to a null pointer dereference. Fix this by adding the missing null check. Addresses-Coverity: ("Dereference null return value") Fixes: 2df7af93fdad ("drm/vkms: Add vkms_config type") Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Sumera Priyadarsini <sylphrenadin@gmail.com> Signed-off-by: Melissa Wen <melissa.srw@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210115130911.71073-1-colin.king@canonical.com
2021-01-15drm/amdgpu/display: these forward declarations are not usedZhiJie.Zhang
Remove them. Signed-off-by: ZhiJie.Zhang <zhangzhijie@loongson.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-15drm/amd/display: fix the coding style issue of integrated_infoHuang Rui
Follow the coding style of size of a struct, changing to: p = kmalloc(sizeof(*p), ...); Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-15drm/amd/pm: update driver if version for navy_flounderJiansong Chen
It's in accordance with pmfw 65.22.0 for navy_flounder. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-15drm/amd/display: fix the system memory page fault because of copy overflowHuang Rui
The buffer is allocated with the size of pointer and copy with the size of data structure. Then trigger the system memory page fault. Use the orignal data structure to get the object size. Fixes: 3a00c04212d1 ("drm/amd/display/dc/core/dc_link: Move some local data from the stack to the heap") Signed-off-by: Huang Rui <ray.huang@amd.com> Cc: Lee Jones <lee.jones@linaro.org> Reviewed-by: Jinzhou.Su <Jinzhou.Su@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-15drm/amdgpu: updated fw attestation interfaceJohn Clements
updated interface to be compatible with latest FW Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-15drm/amdgpu: toggle on DF Cstate after finishing xgmi injectionGuchun Chen
Fixes: 5c23e9e05e42 ("drm/amdgpu: Update RAS XGMI error inject sequence") Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-15drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when outputting YCbCr 4:4:4Ville Syrjälä
Let's not enable the 4:4:4->4:2:0 conversion bit in the DFP unless we're actually outputting YCbCr 4:4:4. It would appear some protocol converters blindy consult this bit even when the source is outputting RGB, resulting in a visual mess. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2914 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111164111.13302-1-ville.syrjala@linux.intel.com Fixes: 181567aa9f0d ("drm/i915: Do YCbCr 444->420 conversion via DP protocol converters") Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2021-01-15drm/tegra: Fix reference leak when pm_runtime_get_sync() failsQinglang Miao
The PM reference count is not expected to be incremented on return in these Tegra functions. However, pm_runtime_get_sync() will increment the PM reference count even on failure. Forgetting to put the reference again will result in a leak. Replace it with pm_runtime_resume_and_get() to keep the usage counter balanced. Fixes: fd67e9c6ed5a ("drm/tegra: Do not implement runtime PM") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-15drm/tegra: gr2d: Add compatible for Tegra114Dmitry Osipenko
Tegra114 has GR2D hardware block, support it by the 2D driver. Tested-by: Anton Bambura <jenneron@protonmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-15drm/tegra: gr2d: Correct swapped device-tree compatiblesDmitry Osipenko
The device-tree compatibles are swapped in the code, correct them. Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Tested-by: Matt Merhar <mattmerhar@protonmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-15drm/tegra: dc: Enable display controller driver for Tegra114Dmitry Osipenko
Display controller driver isn't listed as a DRM sub-device for Tegra114, thus display driver isn't loaded on Tegra114. Enable display controller driver for Tegra114 SoC. Tested-by: Anton Bambura <jenneron@protonmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-15drm/tegra: vic: Add comments on STREAMID registersMikko Perttunen
Add comments clarifying use of the THI_STREAMID0 and THI_STREAMID1 registers. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-15drm/tegra: falcon: Support newer VIC firmwareMikko Perttunen
Support newer VIC firmware by accepting the new magic number 0x10fe, loading the full code segment instead of just the first page at boot time, and skipping FCE setup if the firmware header indicates that FCE is handled internally by the firmware. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-15drm/i915: add back static declarationMatthew Auld
warning: symbol '__i915_gem_object_create_stolen' was not declared. Should it be static? warning: symbol '_i915_gem_object_stolen_init' was not declared. Should it be static? Signed-off-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20210115101329.880667-1-matthew.auld@intel.com
2021-01-15drm/i915: Pass port to intel_panel_bl_funcs.get()Lyude Paul
In the next commit where we split PWM related backlight functions from higher-level backlight functions, we'll want to be able to retrieve the backlight level for the current display panel from the intel_panel_bl_funcs->setup() function using pwm_funcs->get(). Since intel_panel_bl_funcs->setup() is called before we've fully read in the current hardware state into our atomic state, we can't grab atomic modesetting locks safely anyway in intel_panel_bl_funcs->setup(), and some PWM backlight functions (vlv_get_backlight() in particular) require knowing the currently used pipe we need to be able to discern the current display pipe through other means. Luckily, we're already passing the current display pipe to intel_panel_bl_funcs->setup() so all we have to do in order to achieve this is pass down that parameter to intel_panel_bl_funcs->get(). So, fix this by accepting an additional pipe parameter in intel_panel_bl_funcs->get(), and leave figuring out the current display pipe up to the caller. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114221709.2261452-2-lyude@redhat.com
2021-01-15drm/amdgpu: Remove unused variableNirmoy Das
Remove unused space_needed variable. Fixes: 453f617a30aa ("drm/amdgpu: Resize BAR0 to the maximum available size, even if it doesn't cover VRAM") Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/413807/
2021-01-15drm/i915: Try to guess PCH type even without ISA bridgeZhenyu Wang
Some vmm like hyperv and crosvm don't supply any ISA bridge to their guest, when igd passthrough is equipped on these vmm, guest i915 display may couldn't work as guest i915 detects PCH_NONE pch type. When i915 runs as guest, this patch guess pch type through gpu type even without ISA bridge. v2: Fix CI warning v3: Add HAS_DISPLAY()= true condition beforce guessing virt pch, then refactori. v4: Fix CI warning Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Co-developed-by: Xiong Zhang <xiong.y.zhang@intel.com> Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114005819.4290-1-xiong.y.zhang@intel.com
2021-01-15drm/vc4: Initialize vc4_drm_driver with CMA helper defaultsThomas Zimmermann
The function vc4_prime_import_sg_table() is an otherwise empty wrapper around CMA's drm_gem_cma_prime_import_sg_table(). Removing it in favor of the latter allows to initialize vc4_drm_driver with CMA's initializer macro. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210114084949.29014-1-tzimmermann@suse.de
2021-01-15drm/hisilicon/hibmc: Remove hibmc_ttm.cThomas Zimmermann
The file is not in use. It got re-added by a rebased patch. Removing it. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Fixes: 4d4dad21cc7b ("drm/hibmc: Remove references to struct drm_device.pdev") Reviewed-by: Tian Tao <tiantao6@hisilicon.com> Reported-by: Tian Tao <tiantao6@hisilicon.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Xinliang Liu <xinliang.liu@linaro.org> Cc: Tian Tao <tiantao6@hisilicon.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Xinwei Kong <kong.kongxinwei@hisilicon.com> Cc: Chen Feng <puck.chen@hisilicon.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Gong junjie <gongjunjie2@huawei.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210113113107.12005-1-tzimmermann@suse.de
2021-01-15drm/i915/display: Bitwise or the conversion colour specifier togetherChris Wilson
drivers/gpu/drm/i915/display/intel_dp.c:6922 intel_dp_update_420() warn: should this be a bitwise op? drivers/gpu/drm/i915/display/intel_dp.c:6922 intel_dp_update_420() warn: should this be a bitwise op? drivers/gpu/drm/i915/display/intel_dp.c:6923 intel_dp_update_420() warn: should this be a bitwise op? Inside drm_dp_downstream_rgb_to_ycbcr_conversion(), that parameter 'color_spc' is used as return port_cap[3] & color_spc, implying that it is indeed a mask and not a boolean value. Fixes: 522508b665df ("drm/i915/display: Let PCON convert from RGB to YCbCr if it can") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201223103917.14687-1-chris@chris-wilson.co.uk
2021-01-15drm/i915/region: convert object_create into object_initMatthew Auld
Give more flexibility to the caller, if they already have an allocated object, in case they wish to apply some transformation to the object prior to handing it over to the region specific initialisation step, like in gem_create_ext where we would like to first apply the extensions to the object. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20210114182402.840247-3-matthew.auld@intel.com
2021-01-15drm/i915/gem: sanity check object size in gem_createMatthew Auld
Depending on the regions min_page_size we might need to adjust the object size, ensure this matches our expectations. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20210114182402.840247-2-matthew.auld@intel.com
2021-01-15drm/i915/gem: split gem_create into own fileMatthew Auld
In preparation for gem_create_ext break out the gem_create uAPI, so that we don't clutter i915_gem.c once we start adding various extensions Signed-off-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20210114182402.840247-1-matthew.auld@intel.com
2021-01-15drm/i915: Reduce test_and_set_bit to set_bit in i915_request_submit()Chris Wilson
Avoid the full blown memory barrier of test_and_set_bit() by noting the completed request and removing it from the lists. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114135612.13210-5-chris@chris-wilson.co.uk
2021-01-15drm/i915/gem: Reduce ctx->engines_mutex for get_engines()Chris Wilson
Take a snapshot of the ctx->engines, so we can avoid taking the ctx->engines_mutex for a mere read in get_engines(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114135612.13210-4-chris@chris-wilson.co.uk
2021-01-15drm/i915/gem: Reduce ctx->engine_mutex for reading the clone sourceChris Wilson
When cloning the engines from the source context, we need to ensure that the engines are not freed as we copy them, and that the flags we clone from the source correspond with the engines we copy across. To do this we need only take a reference to the src->engines, rather than hold the src->engine_mutex, so long as we verify that nothing changed under the read. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114135612.13210-3-chris@chris-wilson.co.uk
2021-01-15drm/i915: Drop i915_request.lock serialisation around await_startChris Wilson
Originally, we used the signal->lock as a means of following the previous link in its timeline and peeking at the previous fence. However, we have replaced the explicit serialisation with a series of very careful probes that anticipate the links being deleted and the fences recycled before we are able to acquire a strong reference to it. We do not need the signal->lock crutch anymore, nor want the contention. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114135612.13210-2-chris@chris-wilson.co.uk
2021-01-15drm/i915: Mark up protected uses of 'i915_request_completed'Chris Wilson
When we know that we are inside the timeline mutex, or inside the submission flow (under active.lock or the holder's rcu lock), we know that the rq->hwsp is stable and we can use the simpler direct version. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114135612.13210-1-chris@chris-wilson.co.uk
2021-01-15Merge drm/drm-next into drm-intel-gt-nextJoonas Lahtinen
Backmerging to get a common base for merging topic branches between drm-intel-next and drm-intel-gt-next. Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2021-01-15Merge tag 'imx-drm-next-2021-01-08' of ↵Dave Airlie
git://git.pengutronix.de/git/pza/linux into drm-next drm/imx: compile test fixes - Fix COMPILE_TEST builds with CONFIG_OF disabled. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/8c048f3677f706de306c19ecf6868c4109c1c40d.camel@pengutronix.de
2021-01-15Merge tag 'drm-intel-gt-next-2021-01-14' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next UAPI Changes: - Deprecate I915_PMU_LAST and optimize state tracking (Tvrtko) Avoid relying on last item ABI marker in i915_drm.h, add a comment to mark as deprecated. Cross-subsystem Changes: Core Changes: Driver Changes: - Restore clear residuals security mitigations for Ivybridge and Baytrail (Chris) - Close #1858: Allow sysadmin to choose applied GPU security mitigations through i915.mitigations=... similar to CPU (Chris) - Fix for #2024: GPU hangs on HSW GT1 (Chris) - Fix for #2707: Driver hang when editing UVs in Blender (Chris, Ville) - Fix for #2797: False positive GuC loading error message (Chris) - Fix for #2859: Missing GuC firmware for older Cometlakes (Chris) - Lessen probability of GPU hang due to DMAR faults [reason 7, next page table ptr is invalid] on Tigerlake (Chris) - Fix REVID macros for TGL to fetch correct stepping (Aditya) - Limit frequency drop to RPe on parking (Chris, Edward) - Limit W/A 1406941453 to TGL, RKL and DG1 (Swathi) - Make W/A 22010271021 permanent on DG1 (Lucas) - Implement W/A 16011163337 to prevent a HS/DS hang on DG1 (Swathi) - Only disable preemption on gen8 render engines (Chris) - Disable arbitration around Braswell's PDP updates (Chris) - Disable arbitration on no-preempt requests (Chris) - Check for arbitration after writing start seqno before busywaiting (Chris) - Retain default context state across shrinking (Venkata, CQ) - Fix mismatch between misplaced vma check and vma insert for 32-bit addressing userspaces (Chris, CQ) - Propagate error for vmap() failure instead kernel NULL deref (Chris) - Propagate error from cancelled submit due to context closure immediately (Chris) - Fix RCU race on HWSP tracking per request (Chris) - Clear CMD parser shadow and GPU reloc batches (Matt A) - Populate logical context during first pin (Maarten) - Optimistically prune dma-resv from the shrinker (Chris) - Fix for virtual engine ownership race (Chris) - Remove timeslice suppression to restore fairness for virtual engines (Chris) - Rearrange IVB/HSW workarounds properly between GT and engine (Chris) - Taint the reset mutex with the shrinker (Chris) - Replace direct submit with direct call to tasklet (Chris) - Multiple corrections to virtual engine dequeue and breadcrumbs code (Chris) - Avoid wakeref from potentially hard IRQ context in PMU (Tvrtko) - Use raw clock for RC6 time estimation in PMU (Tvrtko) - Differentiate OOM failures from invalid map types (Chris) - Fix Gen9 to have 64 MOCS entries similar to Gen11 (Chris) - Ignore repeated attempts to suspend request flow across reset (Chris) - Remove livelock from "do_idle_maps" VT-d W/A (Chris) - Cancel the preemption timeout early in case engine reset fails (Chris) - Code flow optimization in the scheduling code (Chris) - Clear the execlists timers upon reset (Chris) - Drain the breadcrumbs just once (Chris, Matt A) - Track the overall GT awake/busy time (Chris) - Tweak submission tasklet flushing to avoid starvation (Chris) - Track timelines created using the HWSP to restore on resume (Chris) - Use cmpxchg64 for 32b compatilibity for active tracking (Chris) - Prefer recycling an idle GGTT fence to avoid GPU wait (Chris) - Restructure GT code organization for clearer split between GuC and execlists (Chris, Daniele, John, Matt A) - Remove GuC code that will remain unused by new interfaces (Matt B) - Restructure the CS timestamp clocks code to local to GT (Chris) - Fix error return paths in perf code (Zhang) - Replace idr_init() by idr_init_base() in perf (Deepak) - Fix shmem_pin_map error path (Colin) - Drop redundant free_work worker for GEM contexts (Chris, Mika) - Increase readability and understandability of intel_workarounds.c (Lucas) - Defer enabling the breadcrumb interrupt to after submission (Chris) - Deal with buddy alloc block sizes beyond 4G (Venkata, Chris) - Encode fence specific waitqueue behaviour into the wait.flags (Chris) - Don't cancel the breadcrumb interrupt shadow too early (Chris) - Cancel submitted requests upon context reset (Chris) - Use correct locks in GuC code (Tvrtko) - Prevent use of engine->wa_ctx after error (Chris, Matt R) - Fix build warning on 32-bit (Arnd) - Avoid memory leak if platform would have more than 16 W/A (Tvrtko) - Avoid unnecessary #if CONFIG_PM in PMU code (Chris, Tvrtko) - Improve debugging output (Chris, Tvrtko, Matt R) - Make file local variables static (Jani) - Avoid uint*_t types in i915 (Jani) - Selftest improvements (Chris, Matt A, Dan) - Documentation fixes (Chris, Jose) Signed-off-by: Dave Airlie <airlied@redhat.com> # Conflicts: # drivers/gpu/drm/i915/gt/intel_breadcrumbs.c # drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h # drivers/gpu/drm/i915/gt/intel_lrc.c # drivers/gpu/drm/i915/gvt/mmio_context.h # drivers/gpu/drm/i915/i915_drv.h From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114152232.GA21588@jlahtine-mobl.ger.corp.intel.com
2021-01-15Merge branch '04.01-ampere-lite' of git://github.com/skeggsb/linux into ↵Dave Airlie
topic/nouveau-ampere-modeset This adds support for basic modeseting on the nvidia ampere chipsets. This code should all be contained to just those and have no effect on current hardware. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Ben Skeggs <skeggsb@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv5LmMP+HbDUQBf_dy1-0eS9fA32k8HWo4y5X4-7rsw-yw@mail.gmail.com
2021-01-15Merge tag 'drm-intel-next-2021-01-12' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next - PSR fixes and improvements for selective fetch (Jose) - GVT build fixed and cleanup (Jani) - RKL display fixes (Lee, Matt) - DSI fix (Hans) - Panel Power and Backlight fixes (Anshuman, Jani) - RPM fix (Chris) - Fix HTI port checking (Jose) - Clean-up in cursor code (Ville) - Once again, trying to use fast+narrow link on eDP (Ville) - DG1 display fix (Matt) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210112175151.GA90999@intel.com
2021-01-15Merge branch '04.00-ampere-lite-fixes' of git://github.com/skeggsb/linux ↵Dave Airlie
into drm-fixes As requested, here's a tree with the non-Ampere-specific fixes split out, as most of them are potentially relevant to already-supported GPUs. - irq handling fix - expansion ROM fix - hw init dpcd disable - aux semaphore owner field fix - vram heap sizing fix - notifier at 0 is valid fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Ben Skeggs <skeggsb@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv4P90mcF_ByAh+ghz+ZVD2N2bPbD7xHYYArE1kYrvsGcQ@mail.gmail.com
2021-01-15Merge tag 'amd-drm-fixes-5.11-2021-01-14' of ↵Dave Airlie
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-5.11-2021-01-14: amdgpu: - Update repo location in MAINTAINERS - Add some new renoir PCI IDs - Revert CRC UAPI changes - Revert OLED display fix which cases clocking problems for some systems - Misc vangogh fixes - GFX fix for sienna cichlid - DCN1.0 fix for pipe split - Fix incorrect PSP command amdkfd: - Fix possible out of bounds read in vcrat creation Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114201354.3998-1-alexander.deucher@amd.com
2021-01-15Merge tag 'drm-intel-fixes-2021-01-14' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes drm/i915 fixes for v5.11-rc4: - Allow the sysadmin to override security mitigations - Restore clear-residual mitigations for ivb/byt - Limit VFE threads based on GT - GVT: fix vfio edid and full display detection - Fix DSI DSC power refcounting - Fix LPT CPU mode backlight takeover - Disable RPM wakeref assertions during driver shutdown - Fix DSI sequence sleeps Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87sg73pz42.fsf@intel.com
2021-01-15drm/nouveau/disp/ga10[24]: initial supportBen Skeggs
UEFI/RM no longer use IED scripts from the VBIOS, though they appear to have been updated for use by the x86 VBIOS code, so we should be able to continue using them for the moment. Unfortunately, we require some hacks to do so, as the BeforeLinkTraining IED script became a pointer to an array of scripts instead, without a revbump of the relevant tables. There's also some changes to SOR clock divider fiddling, which are hopefully correct enough that things work as they should. AFAIK, GA100 shouldn't have display, so it hasn't been added. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-15drm/nouveau/dmaobj/ga10[24]: initial supportBen Skeggs
Appears to be compatible with GV100 code, and not required on GA100, as it shouldn't have display. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-15drm/nouveau/i2c/ga10[024]: initial supportBen Skeggs
Appears to be compatible with GM200 code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-15drm/nouveau/gpio/ga10[024]: initial supportBen Skeggs
GA100 appears to be compatible with GK104 code, the others have some register moves. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-15drm/nouveau/bar/ga10[024]: initial supportBen Skeggs
Appears to be compatible with TU102 code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-15drm/nouveau/mmu/ga10[024]: initial supportBen Skeggs
Appears to be compatible with TU102 code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit (git 2.34.1) at 2025-09-15 04:33:27 +0000