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path: root/drivers/gpu
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2020-07-08drm/amd/display: Request PHYCLK adjustment on PHY enable/disableJoshua Aberback
[Why] Currently we don't explicitly send a request for a minimum PHYCLK, and we hope that the dependencies other clocks have will raise PHYCLK when needed. [How] - new clk_mgr function to keep track of PHYCLK requirements - request maximum requirement across all links - remove PHYCLK from clock state comparator, as it doesn't come from DML Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amd/display: 3.2.93Anthony Koo
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amd/display: [FW Promotion] Release 0.0.23Anthony Koo
[Header Changes] - Drop unused firmware SCRATCH bits from interface Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amd/display: Remove VSC infoframe dep on DMCURoman Li
[Why] VSC infoframe is needed for PSR. Previously only DMCU controller supported PSR. Now DMUB also implements PSR. [How] Remove VSC infoframe dependency on DMCU. Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amd/display: Send VSIF on unsupported modes on DALJaehyun Chung
[Why] Current DAL behaviour is to not send VSIF if mode does not support VRR (ie. FS range is < 10Hz). However, we should still set FS Native Color Active bit in some unsupported mode cases. [How] Remove check for if VRR is supported before building infopacket. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amd/display: Register initIgor Kravchenko
[Why] Driver re-initialize registers already set in FW [How] Transfer init to FW Signed-off-by: Igor Kravchenko <Igor.Kravchenko@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amd/display: Add diags scaling log by defaultDmytro Laktyushkin
Print scaling parameters as they are calculated in diags. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amdgpu: fix coding error of mmhub pg enablementLikun Gao
MMHUB powergating should be disabled on navi12 and enabled on sienna cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amdgpu: use RREG32_KIQ to read register when get cg stateLikun Gao
Use RREG32_KIQ to read gfx register when try to get gfx/sdma clockgating state instead of RREG32, as it will result to system hard hang when GPU is enter into GFXOFF state. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amdgpu: updated ta ucode loadingJohn Clements
add support for loading ucode with ta_firmware_header_v2_0 Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amdgpu: updated ta ucode headerJohn Clements
added definition for ta_firmware_header_v2_0 Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amdgpu: add TMR destory function for pspHuang Rui
TMR is required to be destoried with GFX_CMD_ID_DESTROY_TMR while the system goes to suspend. Otherwise, PSP may return the failure state (0xFFFF007) on Gfx-2-PSP command GFX_CMD_ID_SETUP_TMR after do multiple times suspend/resume. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amdgpu: asd function needs to be unloaded in suspend phaseHuang Rui
Unload ASD function in suspend phase. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/i915/huc: Adjust HuC state accordingly after GuC fetch errorMichał Winiarski
Firmware "Selected" state is a transient state - we don't expect to see it after finishing driver probe, we even have asserts sprinkled over i915 to confirm whether that's the case. Unfortunately - we don't handle the transition out of "Selected" in case of GuC fetch error, leading those asserts to fire when calling "intel_huc_is_used()". v2: Add dbg print when moving HuC into error state (Daniele) Reported-by: Marcin Bernatowicz <marcin.bernatowicz@intel.com> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Marcin Bernatowicz <marcin.bernatowicz@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200708100843.297655-2-michal@hardline.pl
2020-07-08drm/i915/uc: Extract uc usage details into separate debugfsMichał Winiarski
It has been pointed out that information about HuC usage doesn't belong in guc_info debugfs. Let's move "supported/used/wanted" matrix to a separate debugfs file, keeping guc_info strictly about GuC. Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Lukasz Fiedorowicz <lukasz.fiedorowicz@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200708100843.297655-1-michal@hardline.pl
2020-07-08drm/i915/hdcp: Fix the return handling of drm_hdcp_check_ksvs_revokedRamalingam C
drm_hdcp_check_ksvs_revoked() returns the number of revoked keys and error codes when the SRM parsing is failed. Errors in SRM parsing can't affect the HDCP auth, hence with this patch, I915 will look out for revoked key count alone. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> cc: Sean Paul <seanpaul@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run> Link: https://patchwork.freedesktop.org/patch/msgid/20200429134555.22106-1-ramalingam.c@intel.com
2020-07-08drm/stm: repair runtime power managementMarek Vasut
Add missing pm_runtime_get_sync() into ltdc_crtc_atomic_enable() to match pm_runtime_put_sync() in ltdc_crtc_atomic_disable(), otherwise the LTDC might suspend via runtime PM, disable clock, and then fail to resume later on. The test which triggers it is roughly -- run qt5 application which uses eglfs platform and etnaviv, stop the application, sleep for 15 minutes, run the application again. This leads to a timeout waiting for vsync, because the LTDC has suspended, but did not resume. Fixes: 35ab6cfbf211 ("drm/stm: support runtime power management") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Yannick Fertré <yannick.fertre@st.com> Cc: Philippe Cornu <philippe.cornu@st.com> Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Vincent Abriou <vincent.abriou@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> To: dri-devel@lists.freedesktop.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-arm-kernel@lists.infradead.org Acked-by: Philippe Cornu <philippe.cornu@st.com> Tested-by: Yannick Fertre <yannick.fertre@st.com> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200229221649.90813-1-marex@denx.de
2020-07-08drm/stm: ltdc: remove call of pm-runtime functionsYannick Fertre
It is not necessary to suspend or stop the ltdc clocks to modify the pixel clock. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Acked-by: Philippe Cornu <philippe.cornu@st.com> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200701120402.6444-1-yannick.fertre@st.com
2020-07-08drm/i915/hdcp: Update CP as per the kernel internal stateAnshuman Gupta
Content Protection property should be updated as per the kernel internal state. Let's say if Content protection is disabled by userspace, CP property should be set to UNDESIRED so that reauthentication will not happen until userspace request it again, but when kernel disables the HDCP due to any DDI disabling sequences like modeset/DPMS operation, kernel should set the property to DESIRED, so that when opportunity arises, kernel will start the HDCP authentication on its own. Somewhere in the line, state machine to set content protection to DESIRED from kernel was broken and IGT coverage was missing for it. This patch fixes it. v2: - Fixing hdcp CP state in connector atomic check function intel_hdcp_atomic_check(). [Maarten] This will require to check hdcp->value in intel_hdcp_update_pipe() in order to avoid enabling hdcp, if it was already enabled. v3: - Rebased. Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/350962/?series=72664&rev=2 #v1 Link: https://patchwork.freedesktop.org/patch/359396/?series=72251&rev=3 #v2 Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630082048.22308-1-anshuman.gupta@intel.com
2020-07-08drm/hisilicon/hibmc: Move drm_fbdev_generic_setup() down to avoid the splatZenghui Yu
The HiSilicon hibmc driver triggers a splat at boot time as below [ 14.137806] ------------[ cut here ]------------ [ 14.142405] hibmc-drm 0000:0a:00.0: Device has not been registered. [ 14.148661] WARNING: CPU: 0 PID: 496 at drivers/gpu/drm/drm_fb_helper.c:2233 drm_fbdev_generic_setup+0x15c/0x1b8 [ 14.158787] [...] [ 14.278307] Call trace: [ 14.280742] drm_fbdev_generic_setup+0x15c/0x1b8 [ 14.285337] hibmc_pci_probe+0x354/0x418 [ 14.289242] local_pci_probe+0x44/0x98 [ 14.292974] work_for_cpu_fn+0x20/0x30 [ 14.296708] process_one_work+0x1c4/0x4e0 [ 14.300698] worker_thread+0x2c8/0x528 [ 14.304431] kthread+0x138/0x140 [ 14.307646] ret_from_fork+0x10/0x18 [ 14.311205] ---[ end trace a2000ec2d838af4d ]--- This turned out to be due to the fbdev device hasn't been registered when drm_fbdev_generic_setup() is invoked. Let's fix the splat by moving it down after drm_dev_register() which will follow the "Display driver example" documented by commit de99f0600a79 ("drm/drv: DOC: Add driver example code"). Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200706144713.1123-1-yuzenghui@huawei.com
2020-07-08drm/nouveau/nouveau: fix page fault on device private memoryRalph Campbell
If system memory is migrated to device private memory and no GPU MMU page table entry exists, the GPU will fault and call hmm_range_fault() to get the PFN for the page. Since the .dev_private_owner pointer in struct hmm_range is not set, hmm_range_fault returns an error which results in the GPU program stopping with a fatal fault. Fix this by setting .dev_private_owner appropriately. Fixes: 08ddddda667b ("mm/hmm: check the device private page owner in hmm_range_fault()") Cc: stable@vger.kernel.org Signed-off-by: Ralph Campbell <rcampbell@nvidia.com> Reviewed-by: Jason Gunthorpe <jgg@mellanox.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-07-08drm/nouveau/svm: fix migrate page regressionRalph Campbell
The patch to add zero page migration to GPU memory inadvertently included part of a future change which broke normal page migration to GPU memory by copying too much data and corrupting GPU memory. Fix this by only copying one page instead of a byte count. Fixes: 9d4296a7d4b3 ("drm/nouveau/nouveau/hmm: fix migrate zero page to GPU") Signed-off-by: Ralph Campbell <rcampbell@nvidia.com> Reviewed-by: John Hubbard <jhubbard@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-07-08drm/nouveau/i2c/g94-: increase NV_PMGR_DP_AUXCTL_TRANSACTREQ timeoutBen Skeggs
Tegra TRM says worst-case reply time is 1216us, and this should fix some spurious timeouts that have been popping up. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-07-08drm/nouveau/kms/nv50-: bail from nv50_audio_disable() early if audio not enabledBen Skeggs
Prevents "snd_hda_codec_hdmi hdaudioC1D0: HDMI: pin nid 5 not registered" that occur on some configurations. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-07-07drm/i915/gt: Pin the rings before marking activeChris Wilson
On eviction, we acquire the vm->mutex and then wait on the vma->active. Therefore when binding and pinning the vma, we must follow the same sequence, lock/pin the vma then mark it active. Otherwise, we mark the vma as active, then wait for the vm->mutex, and meanwhile the evictor holding the mutex waits upon us to complete our activity. Fixes: 8ccfc20a7d56 ("drm/i915/gt: Mark ring->vma as active while pinned") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: <stable@vger.kernel.org> # v5.6+ Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200706170138.8993-1-chris@chris-wilson.co.uk (cherry picked from commit 8567774e87e23a57155e5102f81208729b992ae6) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2020-07-07drm/i915/display: Implement new combo phy initialization stepJosé Roberto de Souza
This is new step that was recently added to the combo phy initialization. v2: - using intel_de_rmw() v3: - going back to read() modify and write() as group register can't be read BSpec: 49291 Cc: Clinton A Taylor <clinton.a.taylor@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200625195252.39312-1-jose.souza@intel.com
2020-07-07drm/meson: overlay: fix build failureNeil Armstrong
The recent GCC compiler is very picky with the VD_H_START() and AFBC_DEC_PIXEL_BGN_H() macros, triggering a runtime assert error as: In function 'meson_overlay_setup_scaler_params', inlined from 'meson_overlay_atomic_update' at drivers/gpu/drm/meson/meson_overlay.c:542:2: ./include/linux/compiler.h:392:38: error: call to '__compiletime_assert_341' declared with attribute error: FIELD_PREP: value too large for the field drivers/gpu/drm/meson/meson_overlay.c:413:4: note: in expansion of macro 'AFBC_DEC_PIXEL_BGN_H' 413 | AFBC_DEC_PIXEL_BGN_H(hd_start_lines - afbc_left) | | ^~~~~~~~~~~~~~~~~~~~ ./include/linux/compiler.h:392:38: error: call to '__compiletime_assert_401' declared with attribute error: FIELD_PREP: value too large for the field It's not expected to overflow these fields, but the compiler did find a case where it overflows. We can safely ignore this, so mask the value with the field width. Fixes: e860785d57306 ("drm/meson: overlay: setup overlay for Amlogic FBC") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> [narmstrong: moved to (value) to avoid precedence issues] Link: https://patchwork.freedesktop.org/patch/msgid/20200707135009.32474-1-narmstrong@baylibre.com
2020-07-07drm/i915: Update dma-attributes for our sg DMAChris Wilson
Looking through the attributes for DMA mappings, it appears that by default dma_map_sg will try and create a kernel accessible map of the page. We never access this, as we either have a struct page already or an iomap, so we can request that the dma mapper does not create one. Without a kernel map in place, one presumes the rest of the memory control attributes do not apply. We also explicitly control the caches around the mappings, so we can ask it not to bother synchronising itself. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200706224308.22636-1-chris@chris-wilson.co.uk
2020-07-07drm/i915/gt: Pin the rings before marking activeChris Wilson
On eviction, we acquire the vm->mutex and then wait on the vma->active. Therefore when binding and pinning the vma, we must follow the same sequence, lock/pin the vma then mark it active. Otherwise, we mark the vma as active, then wait for the vm->mutex, and meanwhile the evictor holding the mutex waits upon us to complete our activity. Fixes: 8ccfc20a7d56 ("drm/i915/gt: Mark ring->vma as active while pinned") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: <stable@vger.kernel.org> # v5.6+ Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200706170138.8993-1-chris@chris-wilson.co.uk
2020-07-07drm/ast: Initialize mode setting in ast_mode_config_init()Thomas Zimmermann
There's modesetting init code in ast_main.c. Move it to ast_mode.c and merge it with the modesetting init code in ast_mode_init(). The result is ast_mode_config_init(), which initalizes the whole modesetting. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-15-tzimmermann@suse.de
2020-07-07drm/ast: Use managed mode-config initThomas Zimmermann
Using drmm_mode_config_init() sets up managed release of modesetting resources. The existing modesetting's finalizer is empty, so remove it. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-14-tzimmermann@suse.de
2020-07-07drm/ast: Replace struct ast_crtc with struct drm_crtcThomas Zimmermann
Struct ast_crtc has been cleaned up and it's now a wrapper around the DRM CRTC structure struct drm_crtc. This patch converts the driver to struct drm_crtc and removes struct ast_crtc. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-13-tzimmermann@suse.de
2020-07-07drm/ast: Init cursors before creating modesetting structuresThomas Zimmermann
The cursor helpers reserve buffer objects in VRAM and update their content. So although tied to modesetting, cursor helpers are more of a memory manager. The modesetting's cursor plane requires this functionality, so initialize cursors before modesetting. While at it, also add an error check for ast_cursor_init(). Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-12-tzimmermann@suse.de
2020-07-07drm/ast: Managed cursor releaseThomas Zimmermann
Register a release function to finalize cursors. The _fini() function gets un-exported from the source file. The function ast_mode_fini() is now empty and will be removed by a later patch. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-11-tzimmermann@suse.de
2020-07-07drm/ast: Keep cursor HW BOs mappedThomas Zimmermann
Updating the image in a cursor's HW BO requires a mapping of the BO's buffer in the kernel's address space. Cursor image updates can happen frequently and create CPU overhead. As cursor HW BOs are small and never move, they are now map exactly once during the initialization and the mapping is used throughout the driver's lifetime. This change also removes a possible source of failures from ast_cursor_show(). As the helper does not establish mappings, it cannot fail. As a result, the cursor plane's atomic-update helper does not call any failable interfaces. All failures are detected before trying to update the cursor plane. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-10-tzimmermann@suse.de
2020-07-07drm/ast: Add helper to hide cursorThomas Zimmermann
As the inverse to ast_cursor_show(), ast_cursor_hide() disables the HW cursor. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-9-tzimmermann@suse.de
2020-07-07drm/ast: Don't enable HW cursors twice during atomic updateThomas Zimmermann
The ast_cursor_show() helper enables the cursor to be displayed. No need to repeat that operation in the plane's atomic-update function. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-8-tzimmermann@suse.de
2020-07-07drm/ast: Replace ast_cursor_move() with ast_cursor_show()Thomas Zimmermann
Having a cursor move function is misleading, as it actually enables the cursor's image for displaying. So rename it to ast_cursor_show(). It's semantics is to show a cursor at the specified location on the screen. The displayed cursor is always the image in the cursor front BO. This change also simplifies struct ast_crtc to being a mere wrapper around around struct drm_crtc. It will be removed by a later patch. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-7-tzimmermann@suse.de
2020-07-07drm/ast: Move cursor pageflip into helperThomas Zimmermann
The new helper ast_cursor_page_flip() switches the cursor's front and back BOs. This simplifies the cursor plane's update helper. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-6-tzimmermann@suse.de
2020-07-07drm/ast: Update cursor image and checksum from same functionThomas Zimmermann
Cursor image and checksum go hand in hand. Update both in the same place. The helper cannot fail, so remove the return type. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-5-tzimmermann@suse.de
2020-07-07drm/ast: Move cursor fb pinning and mapping into helperThomas Zimmermann
The new helper ast_cursor_blit() updates a cursor's backbuffer HW BO from a framebuffer structure. The cursor plane's prepare_fb() function now uses the new interface. Pinning and mapping of BOs is done automatically by the helper. This includes the source BO, which was not pinned by the original code in prepare_fb(). Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-4-tzimmermann@suse.de
2020-07-07drm/ast: Pass struct ast_private instance to cursor init/fini functionsThomas Zimmermann
Removes some typecasting. v2: * use to_ast_private() instead of struct drm_device.dev_private Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-3-tzimmermann@suse.de
2020-07-07drm/ast: Move cursor functions to ast_cursor.cThomas Zimmermann
The cursor manipulation functions are unrelated to modesetting. Move them into their own file. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200702115029.5281-2-tzimmermann@suse.de
2020-07-07drm/vc4: crtc: Remove the feed_txp testsMaxime Ripard
Now that the code in vc4_crtc accessing registers is only meant for the pixelvalve, it doesn't make sense anymore to test whether we're accessing the TXP or not and we can safely remove those checks. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/c044daba470fcb1cb57e3d34d88f75325b2ebbab.1591882579.git-series.maxime@cerno.tech
2020-07-07drm/vc4: txp: Turn the TXP into a CRTC of its ownMaxime Ripard
The TXP so far has been leveraging the PixelValve infrastructure in the driver, that was really two things: the interaction with DRM's CRTC concept, the setup of the underlying pixelvalve and the setup of the shared HVS, the pixelvalve part being irrelevant to the TXP since it accesses the HVS directly. Now that we have a clear separation between the three parts, we can represent the TXP as a CRTC of its own, leveraging the common CRTC and HVS code, but leaving aside the pixelvalve setup. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20f387f881b57f3474fa42d94cfd8bc1b7b80595.1591882579.git-series.maxime@cerno.tech
2020-07-07drm/vc4: crtc: Move the txp_armed function to the TXPMaxime Ripard
The TXP driver is the only place where we need to set the txp_armed flag, so let's move the function in the TXP driver. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/12b383e7b8462e281b00c0a21b2b50f13691bead.1591882579.git-series.maxime@cerno.tech
2020-07-07drm/vc4: crtc: Move the CRTC initialisation to a separate functionMaxime Ripard
The upcoming patches to turn the TXP into a full-blown CRTC will have the same CRTC initialisation code, so let's move it into a separate, public, function so that we can reuse it later on. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/3a3026c0e7408895d154d8dea454cf6d1c459715.1591882579.git-series.maxime@cerno.tech
2020-07-07drm/vc4: crtc: Only access the PixelValve registers if we have toMaxime Ripard
The CRTC hooks are called both for the TXP and the pixelvalve, yet some will read / write the registers as if the device was a pixelvalve, which won't really work. Let's make sure we only access those registers if we are running on a PixelValve. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/b55e31869304c748920c261eba87b3275dbeb297.1591882579.git-series.maxime@cerno.tech
2020-07-07drm/vc4: crtc: Split CRTC data in twoMaxime Ripard
The vc4_crtc_data structure is currently storing data related to both the general CRTC information needed by the rest of the vc4 driver (like HVS output and available FIFOs) and some related to the pixelvalve attached to that CRTC. Let's split this into two structures so that we can reuse the CRTC part into the TXP later on. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/8eb317c91ac208d7f926d76ad421002fa0364c47.1591882579.git-series.maxime@cerno.tech
2020-07-07drm/vc4: crtc: Make state functions publicMaxime Ripard
We'll need the CRTC state related functions to be exported so that we can reuse them for the TXP. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/658f40aa01d7a45cbf6feebfc3dc6549f100d110.1591882579.git-series.maxime@cerno.tech
generated by cgit (git 2.34.1) at 2025-09-14 04:03:04 +0000