| Age | Commit message (Collapse) | Author |
|---|
|
The display controller on Tegra can use syncpoints to count VBLANK
events. syncpoints are 32-bit unsigned integers, so well suited as
VBLANK counters.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
This function is used to read the current value of the syncpt and is
useful in situations where drivers don't schedule work and wait for the
syncpoint to increment. One particular use-case is using the syncpoint
as a VBLANK counter.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Use a sized unsigned 32-bit data type (u32) to store register contents.
The SOR registers are 32 bits wide irrespective of the architecture's
data width.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
The Tegra DRM driver uses a single IO virtual address space for buffer
mappings. Provide a table of the address space usage in debugfs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Check that the desired parent clock is indeed a valid parent for the
display controller clock. This is purely cosmetic at this point since
the parent clocks are specified in DT and all the currently defined
parents are in fact valid parents of the display controller clock.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
We need to wait for all fences, not just the exclusive one.
Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
We somehow try to free the SG table twice.
Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=89734
Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
When performing a modeset, use the framebuffer pitch value to set FIMD
IMG_SIZE and Mixer SPAN registers. These are both defined as pitch - the
distance between contiguous lines (bytes for FIMD, pixels for mixer).
Fixes display on Snow (1366x768).
Signed-off-by: Daniel Stone <daniels@collabora.com>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
|
|
The legcy colorkey ioctls are only implemented for sprite planes, so
reject the ioctl for primary/cursor planes. If we want to support
colorkeying with these planes (assuming we have hw support of course)
we should just move ahead with the colorkey property conversion.
Testcase: kms_legacy_colorkey
Cc: Tommi Rantala <tt.rantala@gmail.com>
Cc: stable@vger.kernel.org
Reference: http://mid.gmane.org/CA+ydwtr+bCo7LJ44JFmUkVRx144UDFgOS+aJTfK6KHtvBDVuAw@mail.gmail.com
Reported-and-tested-by: Tommi Rantala <tt.rantala@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
|
|
This change adds the support in mdp5 kms driver for single
and dual DSI. Dual DSI case depends on the framework API
and sequence change to support dual data path.
v1: Initial change
v2: Address Rob Clark's comment
- Separate command mode encoder to a new file mdp5_cmd_encoder.c
- Rebase to not depend on msm_drm_sub_dev change
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
This change adds the DSI connector support in msm drm driver.
v1: Initial change
v2:
- Address comments from Archit + minor clean-ups
- Rebase to not depend on msm_drm_sub_dev change [Rob's comment]
v3: Fix issues when initialization is failed
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
This change is to add an interface to MDP for connector devices
setting split display information.
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
This change is to make the content in construct_encoder reflect its
name.
Also, DSI connector may be connected to video mode or command mode
encoder, so that 2 different encoders need to be constructed for DSI.
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
Normally these are called from within drm core, from the EDID parsing
code. But for dual-dsi in some drivers (at least drm/msm) we need to
call these from the driver. So they should be exported.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
|
|
This TODO can now be removed and replaced by the previous patch
"drm/msm/mdp5: Update headers (add CTL flush bits)"
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
Some upcoming targets have more bits to set in CTL_FLUSH
registers.
Example: msm8x16 needs to set TIMING1 bit so that some of the
INTF1's interface registers get flushed.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
This change adds the hw configuration for msm8x16 chipsets in
mdp5_cfg module.
Note that only one external display interface is present in this
configuration (DSI) but has not been enabled yet. It will be enabled
once drm/msm driver supports DSI connectors.
v2: add CTL flush register's hardware mask [pointed by Archit]
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
SMP blocks are configured for specific client IDs (ports).
These client IDs can be different from one chip to another for a
given pipe.
e.g.: DMA0 pipe fetch Y component is connected to:
- port #10 for MDP5 v1.3
- port #4 for MDP5 v1.6
In order to be compatible for upcoming versions of MDP5, the
client ID list is passed through the MDP5 config module rather
than using a list of hard-coded enum values.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
This patch contains the generated header file of the following
change "drm/msm/mdp5: Get SMP client list from mdp5_cfg".
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
MDP block is actually contained inside the MDSS block. For some
chipsets, the base address of the MDP registers is different from the
current (assumed) 0x100 offset.
Like CTL and LM blocks, this changes introduce a dynamic offset
for the MDP instance, which can be found out at runtime, once the
MDSS HW version is read.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
This change contains the generated header file for the following
change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain".
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
Prepare for initial DSI implementation
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
The width and height in SSPP_SRC_IMG_SIZE register should be the
size of the entire source framebuffer, not the fetch size.
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
This change adds the registers in mdp5 ping pong blocks
and split display control registers.
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
Pingpong register base addresses are different across platforms.
This change adds this information to config table and initialize
the values for 8x74 and 8084.
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
Up until now, we assume that eDP is tight to intf_0 and HDMI to
intf_3. This information shall actually come from the mdp5_cfg
module since it can change from one chip to another.
v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]
v3: add sanity check before writing in INTF_TIMING_ENGINE_EN registers
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
Some interfaces (WB, DSI Command Mode) need to be kicked off
through a START Signal. This signal needs to be sent at the right
time and requests in some cases to keep track of the pipeline
status (eg: whether pipeline registers are flushed AND output WB
buffers are ready, in case of WB interface).
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
DSI and WB interfaces need a more complex pipeline configuration
than the current mdp5_ctl_set_intf().
For example, memory output connections need to be selected for
WB. Interface mode (Video vs. Command modes) also need to be
configured for DSI.
This change takes care of configuring the whole pipeline as far
as operation mode goes. DSI and WB interfaces will be added
later.
v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
[Remove temp bisectability hack -Rob]
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
Prepare for pipeline operation mode configuration, in particular
for DSI and WB modes.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
[Throw in a #define temporarily to keep things bisectable -Rob]
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
MDP5 hardware has some limitation and requires to avoid flushing
registers more than once between two Vblanks.
This change removes all FLUSH operations (except for HW cursor)
beside the one coming from a CRTC's ->atomic_flush().
This avoid this type of behavior (eg: CRTC + 1 plane overlay):
[drm:mdp5_crtc_vblank_irq] vblank
[drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0
[drm:mdp5_ctl_commit] flush (20040) CTL + LM0
[drm:mdp5_crtc_vblank_irq] blank
[drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0
[drm:mdp5_crtc_vblank_irq] blank
and replaces it by:
[drm:mdp5_crtc_vblank_irq] vblank
[drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0
[drm:mdp5_crtc_vblank_irq] blank
[drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0
[drm:mdp5_crtc_vblank_irq] blank
Only *one* FLUSH is called between Vblanks interrupts.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
Add support to use the VRAM carveout (if specified in dtb) for fbdev
scanout buffer. This allows drm/msm to take over a bootloader splash-
screen, and avoids corruption on screen that results if the kernel uses
memory that is still being scanned out for itself.
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
We'll want to extend this a bit to handle also a reserved-memory
("stolen") region, so that drm/msm can take-over bootloader splash
screen. First split it out into it's own fxn to reduce noise in
the following patch.
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
This patch implements the virtual GEM driver with PRIME sharing which
allows vgem to import a gem object from other drivers for the purpose
of mmap-ing them to userspace. The mmap is done using the mmap
operation exported by other drivers.
v2: remove platform_device and do not attach to dma bufs
v3: use drm helpers for get/put pages
v4: correct dumb create pitch
Reviewed-by: Rob Clark <robdclark@gmail.com> (v3)
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> (v3)
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Zach Reizner <zachr@google.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
|
|
When pixel clock less than 148.5MHz, make sloopboost=2 tklvl=20
cklvl=13 increase rasing/falling time and increase data & clock
voltage driver.
When pixel clock less than 74.25MHz, make sloopboost=0 tklvl=19
cklvl=18, increase data and clock voltage driver.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
Because of iMX6 & Rockchip have differnet mpll config parameter,
the VLEVCTRL parameter would be different. In this case we should
separate VLEVCTRL setting from the common dw_hdmi driver, config
this parameter in platform driver(dw_hdmi-imx and dw_hdmi-rockchip)
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
Using a local struct pointer to reduce one level of indirection
makes the code slightly more readable.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
qemu and simics simulators both seem to expect that video should be disabled
before changing the video mode.
references:
http://git.qemu.org/?p=qemu.git;a=blob;f=hw/display/vga.c;h=c0f7b343bbab586c8593d29c7a765f1e6ca3662c;hb=HEAD#l727
http://wiki.osdev.org/Bochs_VBE_Extensions#Setting_display_resolution_and_bit_depth
Signed-off-by: Chris Ruffin <chris.ruffin@intel.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
|
|
git://anongit.freedesktop.org/drm-intel into drm-next
Final drm-misc pull for 4.0, just various things all over, including a few
more important atomic fixes. btw I didn't pick up the vmwgfx patch from
Ville's series, but one patch has one hunk touching vmwgfx and
Thomas/Jakob didn't get around to ack it. I figured it's simple enough to
be ok though.
* tag 'topic/drm-misc-2015-03-31' of git://anongit.freedesktop.org/drm-intel:
drm: line wrap DRM_IOCTL_DEF* macros
drm/atomic: Don't try to free a NULL state
drm/atomic: Clear crtcs, connectors and planes when clearing state
drm: Rewrite drm_ioctl_flags() to resemble the new drm_ioctl() code
drm: Use max() to make the ioctl alloc size code cleaner
drm: Simplify core vs. drv ioctl handling
drm: Drop ioctl->cmd_drv
drm: Fix DRM_IOCTL_DEF_DRV()
drm/atomic-helpers: Properly avoid full modeset dance
drm: atomic: Allow setting CRTC active property
drm: atomic: Expose CRTC active property
drm: crtc_helper: Update hwmode before mode_set call
drm: mode: Allow NULL modes for equality check
drm: fb_helper: Simplify exit condition
drm: mode: Fix typo in kerneldoc
drm/dp: Print the number of bytes processed for aux nacks
|
|
git://anongit.freedesktop.org/drm-intel into drm-next
This backmerges 4.0-rc6 due to the recent fixes in rc5/6
- DP link rate refactoring from Ville
- byt/bsw rps tuning from Chris
- kerneldoc for the shrinker code
- more dynamic ppgtt pte work (Michel, Ben, ...)
- vlv dpll code refactoring to prep fro bxt (Imre)
- refactoring the sprite colorkey code (Ville)
- rotated ggtt view support from Tvrtko
- roll out struct drm_atomic_state to prep for atomic update (Ander)
* tag 'drm-intel-next-2015-03-27-merge' of git://anongit.freedesktop.org/drm-intel: (473 commits)
Linux 4.0-rc6
arm64: juno: Fix misleading name of UART reference clock
drm/i915: Update DRIVER_DATE to 20150327
drm/i915: Skip allocating shadow batch for 0-length batches
drm/i915: Handle error to get connector state when staging config
drm/i915: Compare GGTT view structs instead of types
drm/i915: fix simple_return.cocci warnings
drm/i915: Add module param to test the load detect code
drm/i915: Remove usage of encoder->new_crtc from clock computations
drm/i915: Don't look at staged config crtc when changing DRRS state
drm/i915: Convert intel_pipe_will_have_type() to using atomic state
drm/i915: Pass an atomic state to modeset_global_resources() functions
drm/i915: Add dynamic page trace events
drm/i915: Finish gen6/7 dynamic page table allocation
drm/i915: Remove unnecessary gen6_ppgtt_unmap_pages
drm/i915: Fix i915_dma_map_single positive error code
drm/i915: Prevent out of range pt in gen6_for_each_pde
drm/i915: fix definition of the DRM_IOCTL_I915_GET_SPRITE_COLORKEY ioctl
drm/i915: Rip out GET_SPRITE_COLORKEY ioctl
watchdog: imgpdc: Fix default heartbeat
...
|
|
This patch makes the fsl,data-width and fsl,data-mapping device tree
properties optional if a panel is connected to the ldb output port
via the of_graph bindings. The data mapping is determined from the
display_info.bus_format field provided by the panel.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
The LDB driver changes the attached display interface's input clock mux
to the LDB_DI clock reference. Change it back again when disabling the
LVDS display. Changing back to the PLL5 for example allows to configure
the same DI for HDMI output later.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
This patch allows to optionally attach the lvds-channel to a panel
supported by a drm_panel driver using of-graph bindings, instead of
supplying the modes via display-timings in the device tree.
This depends on of_graph_get_port_by_id and uses the OF graph to
link the optional DRM panel to the LDB lvds-channel. The output
port number is 1 on devices without the 4-port input multiplexer
(i.MX5) and 4 on devices with the mux (i.MX6).
Before:
ldb {
...
lvds-channel@0 {
...
display-timings {
native-timing = <&timing1>;
timing1: etm0700g0dh6 {
hactive = <800>;
vactive = <480>;
clock-frequency = <33260000>;
hsync-len = <128>;
hback-porch = <88>;
hfront-porch = <40>;
vsync-len = <2>;
vback-porch = <33>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
...
};
};
...
};
};
After:
ldb {
...
lvds-channel@0 {
...
port@4 {
reg = <4>;
lvds_out: endpoint {
remote_endpoint = <&panel_in>;
};
};
};
};
panel {
compatible = "edt,etm0700g0dh6", "simple-panel";
...
port {
panel_in: endpoint {
remote-endpoint = <&lvds_out>;
};
};
};
[Fixed build error due to missing select on DRM_PANEL --rmk]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
The value for downsizing 8:1 is marked as reserved in the technical reference
manual and the documentation states downsizing capability up to 4:1 only.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
The DI pixel clock divider bit field is only 8 bits wide for the
integer part, so limit the divider to the 1...255 interval before
deciding whether the internal clock can be used and before writing
to the register.
Reported-by: Felix Mellmann <felix.mellmann@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
This patch consolidates the different interface_pix_fmt, pixel_fmt, pix_fmt,
and pixfmt variables to a common name "bus_format" wherever they describe the
pixel format on the bus between display controller and encoder hardware.
At the same time, it renames imx_drm_panel_format to imx_drm_set_bus_format.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Emil Renner Berthing <kernel@esmil.dk>
|
|
imx-drm internally misused the V4L2_PIX_FMT constants, which are supposed to
describe the pixel format of frame buffers in memory, to describe the pixel
format on the bus between the display controller and the encoder hardware.
Now that MEDIA_BUS_FMT constants are available to drm drivers, use those
instead.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Emil Renner Berthing <kernel@esmil.dk>
|
|
This patch allows the IPU to divide the 27 MHz input clock from
the TVE by two to obtain the 13.5 MHz pixel clock needed for
NTSC/PAL SD modes.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
This patch allows interlaced frame buffer scanout for interlaced output
via HDMI or TV-Encoder.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
