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Minor cleanup, connector and connector_state are always non-NULL here.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1456303053-28806-3-git-send-email-maarten.lankhorst@linux.intel.com
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With the addition of crtc_state->connector_mask other connectors from
different crtc's aren't needed any more to determine if a crtc has
connectors, so only call add_affected_connectors on the target crtc.
This allows a cleanup to first remove all current connectors, then
add all set->connectors to the target crtc.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1456303053-28806-2-git-send-email-maarten.lankhorst@linux.intel.com
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Currently host1x-instanciated devices have their dma_ops left to NULL,
which makes any DMA operation (like buffer import) on ARM64 fallback
to the dummy_dma_ops and fail with an error.
This patch calls of_dma_configure() with the host1x node when creating
such a device, so the proper DMA operations are set.
Suggested-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The default DMA mask covers a 32 bits address range, but host1x devices
can address a larger range on TK1 and TX1. Set the DMA mask to the range
addressable when we use the IOMMU to prevent the use of bounce buffers.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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With full-ppgtt, it takes the GPU an eon to traverse the entire 256PiB
address space, causing a loop to be detected. Under the current scheme,
if ACTHD walks off the end of a batch buffer and into an empty
address space, we "never" detect the hang. If we always increment the
score as the ACTHD is progressing then we will eventually timeout (after
~46.5s (31 * 1.5s) without advancing onto a new batch). To counter act
this, increase the amount we reduce the score for good batches, so that
only a series of almost-bad batches trigger a full reset. DoS detection
suffers slightly but series of long running shader tests will benefit.
Based on a patch from Chris Wilson.
Testcase: igt/drv_hangman/hangcheck-unterminated
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1456930109-21532-1-git-send-email-mika.kuoppala@intel.com
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GPU engine reset handshaking is something that is applicable to both full GPU
reset and engine reset, which is something that is part of the upcoming TDR
per-engine hang recovery patches. Break out the common engine reset
request/unrequest code (originally written by Mika Kuoppala) for reuse later
in the TDR enablement patch series.
v2: correct indentation and drop unused returned value (Mika)
v3: We have forcewake during reset so use *_FW reg access (Mika)
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Tomas Elf <tomas.elf@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
[Mika: Fixed format warning]
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456929984-16323-1-git-send-email-mika.kuoppala@intel.com
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Supposedly we would want to get the PWM output as close as possible to
the target, so let's round to closest.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456932138-14004-7-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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Now that the mess with AUX clock divder rounding is sorted out and
we have both cdclk and rawclk cached in dev_priv, we can clean up
the .get_aux_clock_divider() functions a bit.
The main thing here is just calling ilk_get_aux_clock_divider()
from hsw_get_aux_clock_divider() except for the LPT:H special
case.
We could go further and call g4x_get_aux_clock_divider() from
ilk_get_aux_clock_divider() for the PCH ports, but I'm sure Jani
would object, so leave that be.
While at it repeat the comment where the AUX clock comes from
in ilk_get_aux_clock_divider().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456932138-14004-6-git-send-email-ville.syrjala@linux.intel.com
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Currently we assume that hrawclk is 200MHz on VLV/CHV. That should
be true always, but just to avoid such asumptions we can read out the
actual frequency from CCK.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456932138-14004-5-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
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With the hrawclk frequency cached in dev_priv, we can simply use
g4x_get_aux_clock_divider() for VLV/CHV.
v2: Rebase due to IS_VALLYVIEW vs. IS_CHERRYVIEW split
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456932138-14004-4-git-send-email-ville.syrjala@linux.intel.com
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g4x is the first platform with DP support, so let's name the relevant
functions as g4x_ instead i9xx_ to avoid confusion.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456932138-14004-3-git-send-email-ville.syrjala@linux.intel.com
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Generalize rawclk handling by storing it in dev_priv.
Presumably our hrawclk readout works at least for CTG and ELK
since we've been using it for DP AUX on those platforms. There
are no real docs anymore after configdb vanished, so the only
reference is the public CTG GMCH spec. What bits are listed in
that doc match our code. The ELK GMCH spec have no relevant
details unfortunately.
The PNV situation is less clear. Starting from
commit aa17cdb4f836 ("drm/i915: initialize backlight max from VBT")
we assume that the CTG/ELK hrawclk readout works for PNV as well.
At least the results *seem* reasonable for one PNV machine (Lenovo
Ideapad S10-3t). Sadly the PNV GMCH spec doesn't have the goods on
the relevant register either.
So let's keep assuming it works for PNV,ELK,CTG and read it out on
those platforms. G33 also has hrawclk according to some notes
in BSpec, but we don't actually need it for anything, so let's not
even try to read it out there.
v2: Rebase due to IS_VALLYVIEW vs. IS_CHERRYVIEW split
Use KHz() all over, and kill off a few useless temp variables
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456932138-14004-2-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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git://anongit.freedesktop.org/drm-intel into drm-fixes
Small conflict as I had the balance in my tree already for testing.
* tag 'drm-intel-fixes-2016-03-03' of git://anongit.freedesktop.org/drm-intel:
drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)
drm/i915/skl: Fix power domain suspend sequence
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drm-next
Big ticket items are hdmi support for 8996 (aka snapdragon 820), and
adreno 430 support. Also one more small uapi addition to support
timestamp queries.
* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (29 commits)
drm/msm: rename hdmi symbols
drm/msm/adreno: remove duplicate adreno_hw_init() call
drm/msm: add timestamp param
drm/msm: fix small typo
drm/msm: grab struct_mutex after allocating submit
drm/msm: reject submit ioctl if no gpu
drm/msm/adreno: print details in case of a protect fault interrupt
drm/msm/adreno: get CP_RPTR from register instead of shadow memory
drm/msm/adreno: add adreno430 power control
drm/msm/adreno: support for adreno 430.
drm/msm: update generated headers
drm/msm/dsi: fix definition of msm_dsi_pll_28nm_8960_init()
drm/msm/dsi: Parse DSI lanes via DT
drm/msm/dsi: Drop VDD regulator for MSM8916
drm/msm/dsi: Remove incorrect warning on host attach
drm/msm: Free fb helper resources in msm_unload
drm/msm/mdp: Detach iommu in mdp4_destroy
drm/msm: make iommu port names const'ier
drm/msm/mdp: Use atomic helper to set crtc property
dt-bindings: msm/hdmi: Add HDMI PHY bindings
...
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Looks like this code does not need to wait atomically since it
otherwise takes the mutex.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1457015805-23742-1-git-send-email-tvrtko.ursulin@linux.intel.com
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Currently the wait_for_atomic_us only allows for a jiffie
timeout granularity which is not nice towards callers
requesting small micro-second timeouts.
Re-implement it so micro-second timeout granularity is really
supported and not just in the name of the macro.
This has another beneficial side effect that it improves
"gem_latency -n 100" results by approximately 2.5% (throughput
and latencies) and 3% (CPU usage). (Note this improvement is
relative to not yet merged execlist lock uncontention patch
which moves the CSB MMIO outside this lock.)
It also shrinks some hot functions like fw_domains_get by a
tiny 3%.
v2:
* Warn when used from non-atomic context (if possible).
* Warn on too long atomic waits.
v3:
* Added comment explaining CONFIG_PREEMPT_COUNT.
* Fixed pre-processor indentation.
(Chris Wilson)
v4:
* Commit msg update (gem_latency) and rebase.
v5:
* Commit message re-wording.
* Added comment about no need for double cond check. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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v2: Added a submenu based on an idea by Chris Wilson.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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I do not see that this needs to be done atomically and up to
one second is quite a long time to busy loop.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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This is for callers who want micro-second precision but are not
waiting from the atomic context.
v2:
* Fix atomic waits. (Dave Gordon)
* Use USEC_PER_SEC and USEC_PER_MSEC. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Global symbols in the kernel should be prefixed by the name
of the subsystem and/or driver to avoid conflicts when all
code is built-in.
In this case, function names like 'hdmi_register' or 'hdmi_set_mode'
are way too generic for an MSM specific DRM driver, so I'm renaming
them all to msm_hdmi_* here.
I also rename a lot of the 'static' symbols along with the global
names for consistency, even though those are relatively harmless;
they might only be slightly confusing when they show up in
backtraces.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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Not sure where it came from, but seem unintentional. And also not
needed on a420, so let's just drop it.
Signed-off-by: Rob Clark <robdclark@gmail.com>
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We need this for GL_TIMESTAMP queries.
Note: currently only supported on a4xx.. a3xx doesn't have this
always-on counter. I think we could emulate it with the one CP
counter that is available, but for now it is of limited usefulness
on a3xx (since we can't seem to do time-elapsed queries in any sane
way with the existing firmware on a3xx, and if you are trying to do
profiling on a tiler you want time-elapsed). We can add that later
if it becomes useful.
Signed-off-by: Rob Clark <robdclark@gmail.com>
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Signed-off-by: Rob Clark <robdclark@gmail.com>
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No real need to hold the lock over allocation, and simplifies things
slightly if we change the order.
Signed-off-by: Rob Clark <robdclark@gmail.com>
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Existing userspace wouldn't get this far, since getparam ioctl would
have failed and it would have bailed out creating a screen/context.
But all the same, we shouldn't let evil or confused userspace cause a
null ptr deref.
Signed-off-by: Rob Clark <robdclark@gmail.com>
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Signed-off-by: Craig Stout <cstout@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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As described in the downstream/kgsl driver:
Sometimes the RPTR shadow memory is unreliable causing timeouts
in adreno_idle(). Read it directly from the register instead.
Signed-off-by: Craig Stout <cstout@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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Signed-off-by: Craig Stout <cstout@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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Signed-off-by: Craig Stout <cstout@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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Pull in additional regs needed for a430, etc.
Signed-off-by: Rob Clark <robdclark@gmail.com>
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This fixes the following build failure:
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.o: In function `msm_dsi_pll_28nm_8960_init':
dsi_pll_28nm.c:(.text+0x1198): multiple definition of `msm_dsi_pll_28nm_8960_init'
drivers/gpu/drm/msm/dsi/pll/dsi_pll.o:dsi_pll.c:(.text+0x0): first defined here
Signed-off-by: Luis Henriques <luis.henriques@canonical.com>
Acked-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
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The DSI driver is currently unaware of how the DSI physical data lanes
are mapped to the logical lanes provided by the DSI controller.
Create a DT binding "qcom,data-lane-map" that provides this information
on a given platform.
The MSM DSI controller is restricted in terms of what all mappings
it can support. The lane polarity is fixed for all the lanes, the clock
lanes are fixed, and the data lanes can be swapped among each other only
for a few combinations. Apply these restrictions when we parse the DT
data.
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh@kernel.org>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
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omapdss driver now depends on omapdrm, so we no longer should select
OMAP2_DSS from omapdrm's Kconfig.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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When an error occurs in omap_gem_new() the function calls
omap_gem_free_object() to clean up. However, that function expects to be
called on a fully initialized GEM object and thus crashes.
Replace it by manual cleanup.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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Having -Werror in the omapdrm Makefile makes development and debugging a
PITA. Let's remove it.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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dispc_ovl_check() is not used anywhere, so it can be removed.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We have removed all the uses of compat code from omapdrm and the
non-compat parts of omapdss, so now we can remove all the compat code
itself.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We have now removed all uses of 'struct omap_overlay_manager', so we can
now remove the last places where it is set.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We are removing the uses of 'struct omap_overlay_manager'. This patch
changes DSI driver to use 'omap_channel' instead.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We are removing the uses of 'struct omap_overlay_manager'. This patch
changes VENC driver to use 'omap_channel' instead.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We are removing the uses of 'struct omap_overlay_manager'. This patch
changes SDI driver to use 'omap_channel' instead.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We are removing the uses of 'struct omap_overlay_manager'. This patch
changes HDMI4 driver to use 'omap_channel' instead.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We are removing the uses of 'struct omap_overlay_manager'. This patch
changes HDMI5 driver to use 'omap_channel' instead.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We are removing the uses of 'struct omap_overlay_manager'. This patch
changes DPI driver to use 'omap_channel' instead.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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The DSS output drivers check 'dssdev->manager' in disconnect()
functions. This check is not needed as the manager must always be set if
the output device was connected. Remove the check.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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Both dpi and sdi check for 'mgr != NULL' in check_timings. This check is
not necessary, as mgr must always be set before check_timings. Remove
the check.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We are removing uses of 'struct omap_overlay_manager'. This patch
changes dss_mgr_unregister_framedone_handler() to accept 'enum
omap_channel' instead of 'struct omap_overlay_manager'.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We are removing uses of 'struct omap_overlay_manager'. This patch
changes dss_mgr_register_framedone_handler() to accept 'enum
omap_channel' instead of 'struct omap_overlay_manager'.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We are removing uses of 'struct omap_overlay_manager'. This patch
changes dss_mgr_start_update() to accept 'enum omap_channel' instead of
'struct omap_overlay_manager'.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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We are removing uses of 'struct omap_overlay_manager'. This patch
changes dss_mgr_disable() to accept 'enum omap_channel' instead of
'struct omap_overlay_manager'.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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