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path: root/drivers/gpu
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2016-02-26drm/sti: reset infoframe transmission when HDMI is stoppedVincent Abriou
Clear all infoframe registers when the HDMI link is stopped. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: HDMI infoframe transmission mode not take into accountVincent Abriou
Set the infoframe transmission mode according to the type of the infoframe. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: reset HD DACS when HDA connector is createdVincent Abriou
Make sure the HD DACS are disabled when the HDA connector is created. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: fix dvo data_enable signalBich Hemon
Modify AWG algorithm in order to handle more than 1023 lines Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: adjust delay for DVOBich Hemon
Modify delay to display last pixel column on DVO Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: add missing encoder cleanup for DVO connectorVincent Abriou
Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: fix panel detection for DVO connectorVincent Abriou
The DVO connector is tag as disconnect because of a wrong management of the panel detection. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: do not clip RGB/YUV component value at connector sideVincent Abriou
Disable the clipping mode for hdmi, dvo and hda connectors. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: adapt YUV colorspace in display pipelineBich Hemon
Use BT601 for SD/ED resolution and BT709 for HD resolution Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: implement atomic_check for the planesVincent Abriou
Atomic update should never fail. Thus all checks must be done in the atomic_check function for each plane (gdp, hqvdp and cursor). Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: force cursor CLUT fetchFabien Dessenne
It may happen that the cursor is displayed with wrong colors which can be explained by a CLUT wrongly fetched at the first display. Fetching the CLUT at each commit (=move) ensures that the right colors are used, at least from the first cursor move. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: GDP cropping fails when we remove 2 pixels horizontallyVincent Abriou
GDP source width should be equal to the destination width to get rid of this issue. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: fallback for GDP scalingBich Hemon
When a GDP gets a scale request (which it does not support), it accepts it but crops or clamps and outputs a warning message. Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: GDP planes only support RGB formatsBich Hemon
Only RGB formats supported by GDP planes Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: clarify the skip frame/field messageFabien Dessenne
When a frame or a field is skipped, output a Warning message instead of an Error message. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: awg_utils code cleanupBich Hemon
data_en is a local variable that doesn't need to be set as awg_generate_instr can be called directly with the requested value. Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: update VTG timing programmingVincent Abriou
This update eases to understand the VTG programming. It also sets a VTG output id for each supported connectors. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: set DRIVER_ATOMIC for stibenjamin.gaignard@linaro.org
sti now support of atomic modesetting so set the flag to enable it. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: fix cursor coordinatesbenjamin.gaignard@linaro.org
fix x/y typo while setting cursor coordinates Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: set CRTC modesetting parametersbenjamin.gaignard@linaro.org
Set CRTC modesetting parameters to avoid warnings in atomic mode. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: fix potential crash in gdpbenjamin.gaignard@linaro.org
In some cases last_close() could be called before sti_gdp_disable() and make kernel crash because mixer structure has been destroy. Let's gdp keep a reference on vtg to fix that (like it is already done in HQVDP) Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/amdgpu: fix error handling in amdgpu_bo_list_setChristian König
Don't leak BOs in case of some error. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-26drm/amd/powerplay: fix code style warning.Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-25drm/fsl-dcu: fix register initializationStefan Agner
The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for Vybrid) whereas the register enumeration start from 1 (1-10 for LS1021a and 1-9 for Vybrid). The loop started off from 0 for both iterations and initialized the number of layers inclusive, which is one layer too many. All extensively written registers seem to be unassigned, it seems that the write to those registers did not do any harm in practice. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: use mode flags for hsync/vsync polarityStefan Agner
The current default configuration is as follows: - Invert VSYNC signal (active LOW) - Invert HSYNC signal (active LOW) The mode flags allow to specify the required polarity per mode. Furthermore, none of the current driver settings is actually a standard polarity. This patch applies the current driver default polarities as explicit flags to the display which has been introduced with the driver (NEC WQVGA "nec,nl4827hc19-05b"). The driver now also parses the flags field and applies the configuration accordingly, by using the following values as standard polarities: (e.g. when no flags are specified): - VSYNC signal not inverted (active HIGH) - HSYNC signal not inverted (active HIGH) Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: fix alpha blendingStefan Agner
Fix alpha blending by enabling alpha blending for the whole frame if a color mode with alpha channel is selected (DRM_FORMAT_ARGB*). Also support color modes without alpha channel (DRM_FORMAT_XRGB*) by just not enabling alpha blending on layer level. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: mask all interrupts on initializationStefan Agner
The state of the interrupt mask register on initialization is unknown, e.g. U-Boot could already used the DCU. So depending on the boot loader, the outcome of the interrupt mask register could be different. A defined state is much more preferable. Also, there is no value in keeping interrupts enabled which we don't need. Therefor, mask all interrupts on initialization. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: handle initialization errors properlyStefan Agner
If initialization fails (e.g. due to missing panel node or deferred probe) make sure to roll-back all operations and return the error code. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: avoid memory leak on errorsStefan Agner
Improve error handling during CRTC initialization. Especially avoid memory leaks in the primary plane initialization error path. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: remove regmap return value checksStefan Agner
It is not common to do regmap return value checks, especially not for memory mapped device. We can rule out most error returns since the conditions are static and we know they are ok (e.g. offset aligned to register stride). Also without proper error handling they are not really valuable for the user. Hence remove most of them. The check in the interrupt handler is worth keeping since a volatile register won't be readable in case register caching is still enabled. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: specify volatile registersStefan Agner
Since we are using cached registers, we need to specify volatile registers explicitly to avoid reading their value from the cache. This allows to read the correct interrupt status in fsl_dcu_drm_irq and clear the asserted bits only. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm: fsl-dcu: Fix no fb check bugMeng Yi
For state->fb or state->crtc may be NULL in fsl_dcu_drm_plane_atomic_check function, if so, return 0. Signed-off-by: Meng Yi <meng.yi@nxp.com> Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/amd: Do not make DRM_AMD_ACP default to yGeert Uytterhoeven
By default, not only this driver is enabled on all platforms, but also generic PM Domains and Multi-Function Devices. Drop the "default y" to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-25drm/amdgpu/gfx: fix off by one in rb rework (v2)Alex Deucher
When I reworked this code, I messed up num rb count. v2: use hweight32 Reviewed-by: Ken Wang <Qingquing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-25drm/i915: Remove update_sprite_watermarks.Maarten Lankhorst
Commit 791a32be6eb2 ("drm/i915: Drop intel_update_sprite_watermarks") removes the use of this variable, but forgot to remove it. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455108583-29227-5-git-send-email-maarten.lankhorst@linux.intel.com
2016-02-25drm/tilcdc: Use devm_kzalloc() and devm_kcalloc() for private dataJyri Sarha
Use devm_kzalloc() and devm_kcalloc() for private data allocation at driver load time. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Initialize crtc->portJyri Sarha
Initialize port device node pointer in the tilcdc crtc. Fixes "Falling back to first CRTC" warning from tda998x driver. The tda998x encoder driver calls drm_of_find_possible_crtcs() to initialize possible_crtcs of struct drm_encoder. The crtc->port needs to be initialized for drm_of_find_possible_crtcs() to work. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Disable sync lost interrupt if it fires on every frameJyri Sarha
Disable the sync lost interrupt if it fires on every frame for 50 consecutive frames in a row. This is relatively sure sign of the sync lost interrupt being stuck and firing on every frame even if the display otherwise appears to work OK. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Add prints on sync lost and FIFO underrun interruptsJyri Sarha
Add ratelimited prints on sync lost and FIFO underrun interrupts. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Remove the duplicate LCDC_INT_ENABLE_SET_REG in registers[]Jyri Sarha
Removes the duplicate LCDC_INT_ENABLE_SET_REG-entry in registers array. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Fix interrupt enable/disable code for version 2 tilcdcJyri Sarha
Fix interrupt enable/disable code for version 2 tilcdc. In version 2 tilcdc there is a separate register for disabling interrupts. Writing 0 to enable registers bits does not have any effect. The interrupt clear register works the same way, writing 1 to specific bit disables the interrupt and writing 0 does not have any effect. The "bug" that is fixed here does not really do any harm since the interrupts are enabled only once in the power up and disabled before power down. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: Do not update the next frame buffer close to vertical blankTomi Valkeinen
Do not update the next frame buffer close to vertical blank. This is to avoid situation when the frame changes between writing of LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: Get rid of complex ping-pong mechanismTomi Valkeinen
Get rid of complex ping-pong mechanism and replace it with simpler single buffer flipping code. The LCDC HW appears to be designed mainly static framebuffers in mind. There are two modes of operation, either static single buffer, or ping pong double buffering with two static buffers switching back and forth. Luckily the framebuffer start address is fetched only in the beginning of the frame and changing the address after that only takes effect after the next vertical blank. The page flipping code can simply write the address of the new framebuffer and the page is flipped automatically after the next vertical blank. Using the ping pong double buffering makes the flipping code way more complex and it does not provide any benefit, so it is better to switch to single buffer operation. There is still one problem in updating the framebuffer dma address on the fly. There are two registers defining the framebuffer dma area and things may break if the dma address is fetched in while the registers are are being updated. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: cleanup irq handlingTomi Valkeinen
Cleanup irq handling. Clear the irq status unconditionally and restructure the status bit conditions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: remove broken error handlingTomi Valkeinen
Remove broken error handling. The condition for handling the LCDC_SYNC_LOST and LCDC_FIFO_UNDERFLOW could never be satisfied as the LCDC_SYNC_LOST interrupt is not enabled. Also the requirement to have both LCDC_SYNC_LOST and LCDC_FIFO_UNDERFLOW fired at once before handling the error looks weird. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: split reset to a separate functionTomi Valkeinen
Split reset to a separate function and use usleep_range(250, 1000) instead of msleep(1) to to keep the reset bit on long enough. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch, changed mdelay(500) to usleep_range(250, 1000)] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: disable crtc on unloadTomi Valkeinen
Disable crtc on unload. Call tilcdc_crtc_dpms() with DRM_MODE_DPMS_OFF in the beginning of unload function. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: cleanup runtime PM handlingTomi Valkeinen
Cleanup runtime PM handling. Before the patch the usage of pm_runtime calls was inconsistent and hard to follow. After the update the pm_runtime calls are removed from set_scanout() and called around major operations that access the HW. After the patch the DPMS code does not have pm_runtime_forbid/allow calls any more and pm_runtime_irq_safe() is not set anymore. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [Added description to the patch] Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-02-25drm/tilcdc: Allocate register storage based on the actual number registersJyri Sarha
Allocate suspend/resume register storage based on the actual number registers the driver is aware of. The static allocation for register storage had fallen behind badly. Reported-by: Michael Bode <michael@bumbleB.de> Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-02-25drm/tilcdc: fix build error when !CONFIG_CPU_FREQGrygorii Strashko
Fix build error when !CONFIG_CPU_FREQ drivers/gpu/drm/tilcdc/tilcdc_drv.c: In function 'tilcdc_load': drivers/gpu/drm/tilcdc/tilcdc_drv.c:327:1: error: label 'fail_put_clk' defined but not used [-Werror=unused-label] fail_put_clk: ^ Signed-off-by: Grygorii Strashko <Grygorii.Strashko@linaro.org> Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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