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path: root/drivers/gpu
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2020-06-03drm/amd/powerplay: Enable SOCCLK ULV for sienna_cichlidLikun Gao
Enable FW DSTATE for sienna_cichlid. Enable DF CSTATE for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amd/powerplay: make gfx ds can be configure for sienna_cichlidLikun Gao
Make GFX deep sleep can be configure for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu/powerplay: set UCLK DPM for sienna_cichlidLikun Gao
Enable uclk dpm for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu/powerplay: set Thermal control for sienna_cichlidLikun Gao
Enable Auto Thermal Throttling for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amd/powerplay: enable SOC Clock Deep Sleep for sienna_cichlidLikun Gao
Enable System On Chip Clock Deep Sleep for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amd/powerplay: enable Graphics Clock Deep Sleep for sienna_cichlidLikun Gao
Enable Graphics Clock Deep Sleep for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amd/powerplay: enable Ultra Low Voltage for sienna_cichlidLikun Gao
Support Ultra Low Voltage for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amd/powerplay: set FCLK DPM for sienna_cichlidLikun Gao
Support for FCLK DPM for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amd/powerplay: set SOCCLK DPM for sienna_cichlidLikun Gao
Support for SOCCLK DPM for sienna_cichlid. Use feature mask to control DPM for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amd/powerplay: add support to set performance level for sienna_cichlidLikun Gao
Support for performance level set for sienna_cichlid. Set standard performance level not fully support, will set to auto performance level. Set peak performance level not fully support, will do nothing with it. Force clk level only support for 2 level for fine grained DPM. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2)Likun Gao
SMU11 based similar to navi1x. v2: squash in SMU IF updates Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add virtual display support for sienna_cichlidLikun Gao
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu/gfx10: change register configure for sienna_cichlidLikun Gao
Update sienna_cichlid register configuration for sienna_cichlid to match the update of header files. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlidLikun Gao
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add sdma ip block for sienna_cichlid (v5)Likun Gao
Sienna_Cichlid have 4 sdma controllers. v2: add missing license to sdma_common.h (Alex) v3: rebase (Alex) v4: squash in policy fix (Alex) v4: squash in fw_name fix Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2)Likun Gao
Add irq src headers for additional SDMA blocks. v2: Add missing licenses (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add gfx ip block for sienna_cichlid (v3)Likun Gao
Add support for GC 10.3. v2: Squash in gb_addr_config fix (Alex) v3: Add num_pkrs support (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add ih ip block for sienna_cichlidLikun Gao
Update IH handling for sienna_cichlid Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add gmc ip block for sienna_cichlidLikun Gao
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add support gfxhub for sienna_cichlid (v3)Likun Gao
GFX10.3 is used for sienna_cichlid. v2: squash in BANK_SELECT and FRAGMENT_SIZE fixes (Alex) v3: squash in smallk update (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add support on mmhub for sienna_cichlidLikun Gao
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu/soc15: add common ip block for sienna_cichlidLikun Gao
Add common ip block for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: initialize IP offset for sienna_cichlid (v2)Likun Gao
Add IP offset headers and state. V2: squash in updates (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu/soc15: add support for sienna_cichlidLikun Gao
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu/gfx10: add clockgating support for sienna_cichlidLikun Gao
Same as navi10. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu/gmc10: add sienna_cichlid supportLikun Gao
Same as navi10. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu/gfx10: add support for sienna_cichlid firmwareLikun Gao
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: set asic family and ip blocks for sienna_cichlidLikun Gao
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: set fw load type for sienna_cichlidLikun Gao
Same as Navi1x. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add sienna_cichlid gpu info firmware v2Likun Gao
gpu info fw contains chip specific parameters. v2: fix fw_name Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add sienna_cichlid asic typeLikun Gao
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amd/display: Add dcn30 Headers (v2)Jerry (Fangzhi) Zuo
DCN 3.0 display controller registers v2: squash in updates from Bhawan. Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add VCN3.0 register headers (v2)Leo Liu
Sienna_Cichlid VCN headers v2: squash in updates (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: Add ATHUB 2.1 header files (v2)Yong Zhao
v2: squash in updates (Alex) Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: add GC 10.3 header files (v2)Likun Gao
Add GC10.3 related header files. v2: squash in updates (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/amdgpu: restrict bo mapping within gpu address limitsRajneesh Bhardwaj
Have strict check on bo mapping since on some systems, such as A+A or hybrid, the cpu might support 5 level paging or can address memory above 48 bits but gpu might be limited by hardware to just use 48 bits. In general, this applies to all asics where this limitation can be checked against their max_pfn range. This restricts the range to map bo within pratical limits of cpu and gpu for shared virtual memory access. Reviewed-by: Oak Zeng <oak.zeng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-06-03drm/hdlcd: Don't call drm_crtc_vblank_off on unbindDaniel Vetter
This is already taken care of by drm_atomic_helper_shutdown(), and in that case only for the CRTC which are actually on. Only tricky bit here is that we kill the interrupt handling before we shut down crtc, so need to reorder that. Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Brian Starkey <brian.starkey@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200602095140.36678-3-daniel.vetter@ffwll.ch
2020-06-03drm/malidp: Don't call drm_crtc_vblank_off on unbindDaniel Vetter
This is already done as part of the drm_atomic_helper_shutdown(), and in that case only for the crtc which are actually on. v2: I overlooked that malidp also needs to have it's interrupt shut down reordered. Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Brian Starkey <brian.starkey@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200602095505.37509-1-daniel.vetter@ffwll.ch
2020-06-03drm/i915: Replace some hand rolled max()sVille Syrjälä
Use max() instead of hand rolling it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200512174145.3186-8-ville.syrjala@linux.intel.com Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
2020-06-03drm/i915: Reverse preemph vs. voltage swing preferenceVille Syrjälä
The DP spec says: "When the combination of the requested pre-emphasis level and voltage swing exceeds the capability of a DPTX, the DPTX shall set the pre-emphasis level according to the request and use the highest voltage swing it can output with the given pre-emphasis level." and "When a DPTX reads a request beyond the limits of this Standard, the DPTX shall set the pre-emphasis level according to the request and set the highest voltage swing level it can output with the given pre-emphasis level. If a DPTX is requested for 9.5dB of pre-emphasis level (may be supported for a DPTX) and cannot support that level, it shall set the pre-emphasis level to the next highest level, 6dB." Ie. we should first validate the pre-emphasis, and then select the appropriate vswing for it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200512174145.3186-6-ville.syrjala@linux.intel.com Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
2020-06-03drm/i915: Add {preemph,voltage}_max() vfuncsVille Syrjälä
Different platforms have different max vswing/preemph settings. Turn that into a pair vfuncs so we can decouple intel_dp.c and intel_ddi.c further. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200512174145.3186-5-ville.syrjala@linux.intel.com Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
2020-06-03drm/i915: Fix ivb cpu edp vswingVille Syrjälä
According to the DP spec supporting vswing 1 + preemph 2 is mandatory. We don't have the hw settings for that though. In order to pretend to follow the DP spec let's just select vswing 0 + preemph 2 in this case (the DP spec says to use the requested preemph in preference to the vswing when the requested values aren't supported). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200512174145.3186-4-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-06-03drm/i915: Fix ibx max vswing/preemphVille Syrjälä
IBX supports vswing level 3 and pre-emphasis level 3. Don't limit it to level 2 for those. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200512174145.3186-3-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-06-03drm/i915: Fix cpt/ppt max pre-emphasisVille Syrjälä
cpt/ppt support pre-emphasis level 3. Let's actually declare support for it, instead of clamping things to level 2. Also tweak the if-ladder in intel_dp_voltage_max() to match intel_dp_pre_emphasis_max() to make it easier to compare them. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200512174145.3186-2-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-06-03drm/shmem-helpers: Redirect mmap for imported dma-bufDaniel Vetter
Currently this seems to work by converting the sgt into a pages array, and then treating it like a native object. Do the right thing and redirect mmap to the exporter. With this nothing is calling get_pages anymore on imported dma-buf, and we can start to remove the use of the ->pages array for that case. v2: Rebase Tested-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rob Herring <robh@kernel.org> Cc: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200511093554.211493-8-daniel.vetter@ffwll.ch
2020-06-03drm/shmem-helpers: Don't call get/put_pages on imported dma-buf in vmapDaniel Vetter
There's no direct harm, because for the shmem helpers these are noops on imported buffers. The trouble is in the locks these take - I want to change dma_buf_vmap locking, and so need to make sure that we only ever take certain locks on one side of the dma-buf interface: Either for exporters, or for importers. v2: Change the control flow less compared to what's there (Thomas) Tested-by: Boris Brezillon <boris.brezillon@collabora.com> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rob Herring <robh@kernel.org> Cc: Noralf Trønnes <noralf@tronnes.org> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200514202256.490926-1-daniel.vetter@ffwll.ch
2020-06-03drm/i915: Drop i915_request.i915 backpointerChris Wilson
We infrequently use the direct i915 backpointer from the i915_request, so do we really need to waste the space in the struct for it? 8 bytes from the most frequently allocated struct vs an 3 bytes and pointer chasing in using rq->engine->i915? Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200602220953.21178-1-chris@chris-wilson.co.uk
2020-06-03drm/udl: Don't call get/put_pages on imported dma-bufDaniel Vetter
There's no direct harm, because for the shmem helpers these are noops on imported buffers. The trouble is in the locks these take - I want to change dma_buf_vmap locking, and so need to make sure that we only ever take certain locks on one side of the dma-buf interface: Either for exporters, or for importers. Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: Dave Airlie <airlied@redhat.com> Cc: Sean Paul <sean@poorly.run> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200511093554.211493-6-daniel.vetter@ffwll.ch
2020-06-03drm/virtio: Call the right shmem helpersDaniel Vetter
drm_gem_shmem_get_sg_table is meant to implement obj->funcs->get_sg_table, for prime exporting. The one we want is drm_gem_shmem_get_pages_sgt, which also handles imported dma-buf, not just native objects. v2: Rebase, this stuff moved around in commit 2f2aa13724d56829d910b2fa8e80c502d388f106 Author: Gerd Hoffmann <kraxel@redhat.com> Date: Fri Feb 7 08:46:38 2020 +0100 drm/virtio: move virtio_gpu_mem_entry initialization to new function Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: David Airlie <airlied@linux.ie> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: virtualization@lists.linux-foundation.org Link: https://patchwork.freedesktop.org/patch/msgid/20200511093554.211493-5-daniel.vetter@ffwll.ch
2020-06-03drm/doc: Some polish for shmem helpersDaniel Vetter
- Move the shmem helper section to the drm-mm.rst file, next to the vram helpers. Makes a lot more sense there with the now wider scope. Also, that's where the all the other backing storage stuff resides. It's just the framebuffer helpers that should be in the kms helper section. - Try to clarify which functiosn are for implementing drm_gem_object_funcs, and which for drivers to call directly. At least one driver screwed that up a bit. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rob Herring <robh@kernel.org> Cc: Noralf Trønnes <noralf@tronnes.org> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200511093554.211493-4-daniel.vetter@ffwll.ch
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