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2018-03-15drm/amd/pp: Move helper functions to smu_help.cRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/pp: Replace rv_* with smu10_*Rex Zhu
Powerplay is for the hw ip smu, for RV, smu10 is used, so use smu10 as the prefix of the files name/function name. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/pp: Fix function parameter not correctRex Zhu
caused by "commit dcefb7668e5b4fb56099b16d1790cd3056322b03" Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/pp: Add rv_copy_table_from/to_smc to smu backend function tableRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/tegra: plane: Correct legacy blendingDmitry Osipenko
Keep old 'dependent' state of unaffected planes, this way new state takes into account current state of unaffected planes. Fixes: ebae8d07435a ("drm/tegra: dc: Implement legacy blending") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-15drm/amd/pp: Add new smu backend function smc_table_managerRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/pp: Mark internal functions as static in rv_smumgr.cRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/pp: Add rv_read_arg_from_smc to smu backend function tableRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/pp: Remove meanless return value check in RVRex Zhu
In send_message_to_smu helper functions, Print out the error code for debug if smu failed to response. The helper functions always return true, so no need to check their return value. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/pp: Delete is_smc_ram_running function on RVRex Zhu
1. There is a race condition when another ip also use same register pairs 2. check once at boot up by GetDriverIfVersion message is sufficient to check SMU health. so delete is_smc_ram_running check. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/pp: Clean up header file includeRex Zhu
smu7_smumgr.h should not be included in rv and vega, The common functions for all smu7 asics are put in smu_smumgr.c. Not include cgs interface in smumgr.c. the code used cgs interface has been deleted. Not include smu_ucode_xfer_vi.h in rv/vega Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/pp: Fix memory leak in error path in smumgrRex Zhu
Free the backend structure if we fail to allocate device memory. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/pp: Simplified the avfs btc state on smu7Rex Zhu
AVFS feature support/not support is enough to driver. so remove the complex define of the avfs btc state. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/amd/powerplay: Fix KASAN user after free on driver unload.Andrey Grodzovsky
Reusing local handle to initialize BO without resetting it to NULL is wrong since it causes amdgpu_bo_create_reserved to skip new BO creation and just reuse the given pointer for pinning. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-15drm/tegra: dc: Dedicate overlay plane to cursor on older Tegra'sDmitry Osipenko
Older Tegra's do not support RGBA format for the cursor, but instead overlay plane could be used for it. Since there is no much use for the overlays on a regular desktop and HW-accelerated cursor is much better than a SW cursor, let's dedicate one overlay plane to the mouse cursor. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-15drm/tegra: plane: Make tegra_plane_get_overlap_index() staticDmitry Osipenko
This function is not used outside of the file and can be static. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-15drm/tegra: plane: Fix RGB565 format on older TegraThierry Reding
The opaque/alpha format conversion code is currently only looking at XRGB formats because they have an equivalent ARGB format. The opaque format for RGB565 is RGB565 itself, much like the YUV formats map to themselves. Reported-by: Dmitry Osipenko <digetx@gmail.com> Fixes: ebae8d07435a ("drm/tegra: dc: Implement legacy blending") Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-15drm/bridge: dw-hdmi: Remove unused hdmi_enable_overflow_interrupts()Fabio Estevam
The cable_plugin member never receives an assignment, so it is always false, which causes hdmi_enable_overflow_interrupts() to never be called as per the logic below: if (hdmi->cable_plugin && hdmi->sink_is_hdmi) hdmi_enable_overflow_interrupts(hdmi); This has been the case since the driver was originally introduced in commit 9aaf880ed4ee ("imx-drm: Add mx6 hdmi transmitter support"). Remove the cable_plugin element and the hdmi_enable_overflow_interrupts() function that is never called. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # On R-Car H3 Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/1518812170-22687-1-git-send-email-festevam@gmail.com
2018-03-15drm/amdkfd: add missing include of mm.hOded Gabbay
This patch fixes kernel build in ARCH=frv Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
2018-03-15drm/i915/gvt: fix user copy warning by whitelist workload rb_tail fieldZhenyu Wang
This is to fix warning got as: [ 6730.476938] ------------[ cut here ]------------ [ 6730.476979] Bad or missing usercopy whitelist? Kernel memory exposure attempt detected from SLAB object 'gvt-g_vgpu_workload' (offset 120, size 4)! [ 6730.477021] WARNING: CPU: 2 PID: 441 at mm/usercopy.c:81 usercopy_warn+0x7e/0xa0 [ 6730.477042] Modules linked in: tun(E) bridge(E) stp(E) llc(E) kvmgt(E) x86_pkg_temp_thermal(E) vfio_mdev(E) intel_powerclamp(E) mdev(E) coretemp(E) vfio_iommu_type1(E) vfio(E) kvm_intel(E) kvm(E) hid_generic(E) irqbypass(E) crct10dif_pclmul(E) crc32_pclmul(E) usbhid(E) i915(E) crc32c_intel(E) hid(E) ghash_clmulni_intel(E) pcbc(E) aesni_intel(E) aes_x86_64(E) crypto_simd(E) cryptd(E) glue_helper(E) intel_cstate(E) idma64(E) evdev(E) virt_dma(E) iTCO_wdt(E) intel_uncore(E) intel_rapl_perf(E) intel_lpss_pci(E) sg(E) shpchp(E) mei_me(E) pcspkr(E) iTCO_vendor_support(E) intel_lpss(E) intel_pch_thermal(E) prime_numbers(E) mei(E) mfd_core(E) video(E) acpi_pad(E) button(E) binfmt_misc(E) ip_tables(E) x_tables(E) autofs4(E) ext4(E) crc16(E) mbcache(E) jbd2(E) fscrypto(E) sd_mod(E) e1000e(E) xhci_pci(E) sdhci_pci(E) [ 6730.477244] ptp(E) cqhci(E) xhci_hcd(E) pps_core(E) sdhci(E) mmc_core(E) i2c_i801(E) usbcore(E) thermal(E) fan(E) [ 6730.477276] CPU: 2 PID: 441 Comm: gvt workload 0 Tainted: G E 4.16.0-rc1-gvt-staging-0213+ #127 [ 6730.477303] Hardware name: /NUC6i5SYB, BIOS SYSKLi35.86A.0039.2016.0316.1747 03/16/2016 [ 6730.477326] RIP: 0010:usercopy_warn+0x7e/0xa0 [ 6730.477340] RSP: 0018:ffffba6301223d18 EFLAGS: 00010286 [ 6730.477355] RAX: 0000000000000000 RBX: ffff8f41caae9838 RCX: 0000000000000006 [ 6730.477375] RDX: 0000000000000007 RSI: 0000000000000082 RDI: ffff8f41dad166f0 [ 6730.477395] RBP: 0000000000000004 R08: 0000000000000576 R09: 0000000000000000 [ 6730.477415] R10: ffffffffb1293fb2 R11: 00000000ffffffff R12: 0000000000000001 [ 6730.477447] R13: ffff8f41caae983c R14: ffff8f41caae9838 R15: 00007f183ca2b000 [ 6730.477467] FS: 0000000000000000(0000) GS:ffff8f41dad00000(0000) knlGS:0000000000000000 [ 6730.477489] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 6730.477506] CR2: 0000559462817291 CR3: 000000028b46c006 CR4: 00000000003626e0 [ 6730.477526] Call Trace: [ 6730.477537] __check_object_size+0x9c/0x1a0 [ 6730.477562] __kvm_write_guest_page+0x45/0x90 [kvm] [ 6730.477585] kvm_write_guest+0x46/0x80 [kvm] [ 6730.477599] kvmgt_rw_gpa+0x9b/0xf0 [kvmgt] [ 6730.477642] workload_thread+0xa38/0x1040 [i915] [ 6730.477659] ? do_wait_intr_irq+0xc0/0xc0 [ 6730.477673] ? finish_wait+0x80/0x80 [ 6730.477707] ? clean_workloads+0x120/0x120 [i915] [ 6730.477722] kthread+0x111/0x130 [ 6730.477733] ? _kthread_create_worker_on_cpu+0x60/0x60 [ 6730.477750] ? exit_to_usermode_loop+0x6f/0xb0 [ 6730.477766] ret_from_fork+0x35/0x40 [ 6730.477777] Code: 48 c7 c0 20 e3 25 b1 48 0f 44 c2 41 50 51 41 51 48 89 f9 49 89 f1 4d 89 d8 4c 89 d2 48 89 c6 48 c7 c7 78 e3 25 b1 e8 b2 bc e4 ff <0f> ff 48 83 c4 18 c3 48 c7 c6 09 d0 26 b1 49 89 f1 49 89 f3 eb [ 6730.477849] ---[ end trace cae869c1c323e45a ]--- By whitelist guest page write from workload struct allocated from kmem cache. Reviewed-by: Hang Yuan <hang.yuan@linux.intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> (cherry picked from commit 5627705406874df57fdfad3b4e0c9aedd3b007df)
2018-03-15drm/i915/gvt: Correct the privilege shadow batch buffer addressfred gao
Once the ring buffer is copied to ring_scan_buffer and scanned, the shadow batch buffer start address is only updated into ring_scan_buffer, not the real ring address allocated through intel_ring_begin in later copy_workload_to_ring_buffer. This patch is only to set the right shadow batch buffer address from Ring buffer, not include the shadow_wa_ctx. v2: - refine some comments. (Zhenyu) v3: - fix typo in title. (Zhenyu) v4: - remove the unnecessary comments. (Zhenyu) - add comments in bb_start_cmd_va update. (Zhenyu) Fixes: 0a53bc07f044 ("drm/i915/gvt: Separate cmd scan from request allocation") Cc: stable@vger.kernel.org # v4.15 Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Yulei Zhang <yulei.zhang@intel.com> Signed-off-by: fred gao <fred.gao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-03-15Merge tag 'drm-intel-fixes-2018-03-14' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes - 1 display fix for bxt - 1 gem fix for fences - 1 gem/pm fix for rps freq * tag 'drm-intel-fixes-2018-03-14' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915: Kick the rps worker when changing the boost frequency drm/i915: Only prune fences after wait-for-all drm/i915: Enable VBT based BL control for DP
2018-03-14drm/amdgpu/sdma4: Remove unused header file from sdma_v4_0.cFeifei Xu
Remove mmhub header files inclusion which not used. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu/sdma4: use num_instances for clock/powergating configAlex Deucher
Rather then relying on the asic type for the second instance. Makes it more consistent with the rest of the code. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
2018-03-14drm/amdgpu: remove trailing whitespace from soc15ip.hAlex Deucher
no intended functional change. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu/powerplay/vega10: fix memory leak in error pathAlex Deucher
Free the backend structure if we fail to allocate device memory. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu/dce: Don't turn off DP sink when disconnectedMichel Dänzer
Turning off the sink in this case causes various issues, because userspace expects it to stay on until it turns it off explicitly. Instead, turn the sink off and back on when a display is connected again. This dance seems necessary for link training to work correctly. Bugzilla: https://bugs.freedesktop.org/105308 Cc: stable@vger.kernel.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/pp: remove redundant pointer internal_bufColin Ian King
The pointer internal_buf is assigned a value but the pointer is never read, hence it is redundant and can be removed. Cleans up clang warning: drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/smu7_smumgr.c:630:2: warning: Value stored to 'internal_buf' is never read Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu: move getting pcie info to common codeAlex Deucher
No need to replicate it in several places. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu/soc15: always load the psp moduleAlex Deucher
Regardless of whether the user has selected psp fw loading or not. It's still needed for GPU reset among other things. There are already guards in place to avoid setting up the full psp if PSP fw loading is not enabled. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu: use adev->firmware to determine whether to load the PSP moduleAlex Deucher
The per device firmware load method is limited to what makes sense for that asic rather than whatever arbitrary value may have been set by the user. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu: move firmware loading type setup to common codeAlex Deucher
No need to replicate it in several places. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu/psp: add a few more fw load type checksAlex Deucher
We already checked and returned early in most of the IP functions, fill in the rest as well. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: Check msg->size before starting aux transferShirish S
This patch adds an essential check related to the size of the payload to be transferred via aux channel. Without this check dal_ddc_service_read_dpcd_data() is fed with inappropriate payload size leading to deadlocks. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: clean up dcn pplib notification callDmytro Laktyushkin
We have unused variables being populated when notifying pplib. This change amends that. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: Fixed dim around 1sec when resume from S3 (v2)Yongqiang Sun
root cause: DMCU try to perform a smoothness brightness change.Incorrect initial brightness level causes the 1 sec dim. Change: Cache brightness level in stream, and clear it when edp backlight on. If brightness level in stream is 0, set brightness with ramp value is 0. DMCU will set the brightness without smoothness transition. v2: squash in null pointer fix (Harry) Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu/dce: Don't turn off DP sink when disconnectedMichel Dänzer
Turning off the sink in this case causes various issues, because userspace expects it to stay on until it turns it off explicitly. Instead, turn the sink off and back on when a display is connected again. This dance seems necessary for link training to work correctly. Bugzilla: https://bugs.freedesktop.org/105308 Cc: stable@vger.kernel.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu: save/restore backlight level in legacy dce codeAlex Deucher
Save/restore the backlight level scratch register in S3/S4 so the backlight level comes back at the previously requested level. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=199047 Fixes: 4ec6ecf48c64d (drm/amdgpu: drop scratch regs save and restore from S3/S4 handling) Acked-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/radeon: fix prime teardown orderChristian König
We unmapped imported DMA-bufs when the GEM handle was dropped, not when the hardware was done with the buffere. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> CC: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu: fix prime teardown orderChristian König
We unmapped imported DMA-bufs when the GEM handle was dropped, not when the hardware was done with the buffere. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> CC: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: Use actual TG instance instead of pipe instanceJerry (Fangzhi) Zuo
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: Check for HW blocks in HWSS, rather than DC core for cursorHarry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amdgpu: Move IH clientid defs to separate fileOak Zeng
This is preparation for sharing client ID definitions between amdgpu and amdkfd Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: update dce_calcs to latest versionDmytro Laktyushkin
Bw spreadsheet was updated while dce_calcs was not Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: Set disp clk in a safe way to avoid over high dpp clk. (v2)Yongqiang Sun
Increase clock, if current dpp div is 0 and request dpp div is 1, request clk is higher than maximum dpp clk as per dpm table. set dispclk to the value of maximum supported dpp clk set div to 1 set dispclk to request value. Decrease clock, currrent dpp div is 1 and request dpp div is 0, current clk is higher than maximum dpp clk as per dpm table. set dispclk to the value of maximum supported dpp clk set div to 0 set dispclk to request value. v2: squash in !DCN build fix Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: add support for regkey "LCDFreeSyncDefault"Samson Tam
Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: Correct the plane enumeration order (v2)Shirish S
The order of planes is given by the order they are enumerated by kms. Planes with a higher ID appears above planes with a lower ID. Currently the planes are enumerated in the wrong order, putting the nv12 only plane after the two RGBA planes. This patch corrects the plane enumeration order such that all the overlay planes are initialized first then the primary planes. Due to this change in order the dc_add_plane_to_context() shall receive the planes in reverse order hence this patch reverses the parsing of planes in DM side itself. v2: drop local reverse macro for upstream Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: Fix handling of linear transfer functionVitaly Prosyak
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: dal 3.1.38Tony Cheng
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-14drm/amd/display: Add variable refresh rate parameters to DC structuresAnthony Koo
Time stamping will be part of surface, and will be updated when address is flipped. FreeSync parameters will be attached to stream, as it adjusts the timing dynamically. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-28 02:07:22 +0000