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2019-04-08mtd: rawnand: Use nanddev_mtd_max_bad_blocks()Boris Brezillon
nanddev_mtd_max_bad_blocks() is implemented by the generic NAND layer and is already doing what we need. Reuse this function instead of having our own implementation. While at it, get rid of the ->max_bb_per_die and ->blocks_per_die fields which are now unused. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Move all page cache related fields to a sub-structBoris Brezillon
Looking at the field names it's hard to tell what ->data_buf, ->pagebuf and ->pagebuf_bitflips are for. Clarify that by moving those fields in a sub-struct named pagecache. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Provide a helper to get chip->data_bufBoris Brezillon
We plan to move cache related fields to a pagecache struct in nand_chip but some drivers access ->pagebuf directly to invalidate the cache before they start using ->data_buf. Let's provide an helper that returns a pointer to ->data_buf after invalidating the cache. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Initialize the nand_device objectBoris Brezillon
In order to use some of the nanddev_xxx() helpers, we need to initialize the nand_device object embedded in nand_chip using nanddev_init(). This requires implementing nand_ops. We also drop useless mtd->xxx initialization when they're already taken case of by nanddev_init(). Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Fill memorg during detectionBoris Brezillon
If we want to use the generic NAND layer, we need to have the memorg struct appropriately filled. Patch the detection code to fill this struct. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08mtd: spinand: Implement mtd->_max_bad_blocksBoris Brezillon
We just have to use nanddev_mtd_max_bad_blocks(). Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: nand: Add max_bad_eraseblocks_per_lun info to memorgBoris Brezillon
NAND datasheets usually give the maximum number of bad blocks per LUN and this number can be used to help upper layers decide how much blocks they should reserve for bad block handling. Add a max_bad_eraseblocks_per_lun to the nand_memory_organization struct and update the NAND_MEMORG() macro (and its users) accordingly. We also provide a default mtd->_max_bad_blocks() implementation. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: meson: set oob layout opsLiang Yang
Specify the oob layout operation to avoid no oob scheme defined for some nand flash. Fixes: 8fae856c5350 ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") Signed-off-by: Liang Yang <liang.yang@amlogic.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08mtd: rawnand: vf610: Avoid a potential NULL pointer dereferenceAditya Pakki
of_match_device can return NULL if there is no matching device. Avoid a potential NULL pointer dereference by checking for the return value and passing the error upstream. Signed-off-by: Aditya Pakki <pakki001@umn.edu> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08mtd: rawnand: ingenic: Move BBTs out of ECC areaPaul Cercueil
The generic layout for BBT markers will most likely overlap with our ECC bytes in the OOB, so move the BBT markers outside the OOB area. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08mtd: rawnand: ingenic: Add ooblayout for the Qi Ben NanonotePaul Cercueil
The Ben Nanonote from Qi Hardware expects a specific OOB layout on its NAND. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08mtd: rawnand: ingenic: Add support for the JZ4725BPaul Cercueil
The boot ROM of the JZ4725B SoC expects a specific OOB layout on the NAND, so we use it unconditionally in the ingenic-nand driver. Also add the jz4725b-bch driver to support the JZ4725B-specific BCH hardware. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08mtd: rawnand: ingenic: Add support for the JZ4740Paul Cercueil
Add support for probing the ingenic-nand driver on the JZ4740 SoC from Ingenic, and the jz4740-ecc driver to support the JZ4740-specific ECC hardware. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08mtd: rawnand: ingenic: Make use of ecc-engine propertyPaul Cercueil
Use the 'ecc-engine' standard property instead of the custom 'ingenic,bch-controller' custom property, which is now deprecated. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08mtd: rawnand: ingenic: Separate top-level and SoC specific codePaul Cercueil
The ingenic-nand driver uses an API provided by the jz4780-bch driver. This makes it difficult to support other SoCs in the jz4780-bch driver. To work around this, we separate the API functions from the SoC-specific code, so that these API functions are SoC-agnostic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-05mtd: cfi: fix deadloop in cfi_cmdset_0002.c do_write_bufferLiu Jian
In function do_write_buffer(), in the for loop, there is a case chip_ready() returns 1 while chip_good() returns 0, so it never break the loop. To fix this, chip_good() is enough and it should timeout if it stay bad for a while. Fixes: dfeae1073583("mtd: cfi_cmdset_0002: Change write buffer to check correct value") Signed-off-by: Yi Huaijie <yihuaijie@huawei.com> Signed-off-by: Liu Jian <liujian56@huawei.com> Reviewed-by: Tokunori Ikegami <ikegami_to@yahoo.co.jp> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-04-01spi-nor: s25fl512s supports region lockingJonas Bonn
Both the BP[0-2] bits and the TBPROT bit are supported on this chip. Tested and verified on a Cypress s25fl512s. Signed-off-by: Jonas Bonn <jonas@norrbonn.se> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-01mtd: spi-nor: intel-spi: Avoid crossing 4K address boundary on read/writeAlexander Sverdlin
It was observed that reads crossing 4K address boundary are failing. This limitation is mentioned in Intel documents: Intel(R) 9 Series Chipset Family Platform Controller Hub (PCH) Datasheet: "5.26.3 Flash Access Program Register Access: * Program Register Accesses are not allowed to cross a 4 KB boundary..." Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms): "5.1.4 Address For other memory transactions, the address may start or end at any byte boundary. However, the address and payload length combination must not cross the naturally aligned address boundary of the corresponding Maximum Payload Size. It must not cross a 4 KB address boundary." Avoid this by splitting an operation crossing the boundary into two operations. Fixes: 8afda8b26d01 ("spi-nor: Add support for Intel SPI serial flash controller") Cc: stable@vger.kernel.org Reported-by: Romain Porte <romain.porte@nokia.com> Tested-by: Pascal Fabreges <pascal.fabreges@nokia.com> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: spi-nor: Fix comment of spi_nor_find_best_erase_type()Alexander Sverdlin
Erase types are sorted *smallest* type first, refer to spi_nor_sort_erase_mask(). Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: spi-nor: Print all JEDEC ID bytes on errorGeert Uytterhoeven
If identification of an SPI NOR FLASH fails, the JEDEC ID is printed, which is stored in the first 3 bytes of the ID read from the FLASH. However, the extended JEDEC ID, which is stored in the remaining bytes, also matters, as it is used for identification of some FLASH types. Print all (currently 6) ID bytes read to ease failure analysis and debugging. Suggested-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: ingenic: Rename jz4780_bch_init to jz4780_bch_resetPaul Cercueil
The jz4780_bch_init name was confusing, as it suggested that its content should be executed once at init time, whereas what the function really does is reset the hardware for a new ECC operation. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: ingenic: Rename jz4780_nand driver to ingenic_nandPaul Cercueil
The jz4780_nand driver will be modified to handle all the Ingenic JZ47xx SoCs that the upstream Linux kernel supports (JZ4740, JZ4725B, JZ4770, JZ4780), so it makes sense to rename it. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: ingenic: Use SPDX license notifiersPaul Cercueil
Use SPDX license notifiers instead of GPLv2 license text in the headers. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: Move drivers for Ingenic SoCs to subfolderPaul Cercueil
Before adding support for more SoCs and seeing the number of files for these drivers grow, we move them to their own subfolder to keep it tidy. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: meson: fix a potential memory leak in meson_nfc_read_bufMartin Blumenstingl
meson_nfc_dma_buffer_setup() is called with the "info" buffer which is allocated a few lines before using kzalloc(). If meson_nfc_dma_buffer_setup() fails we need to free the allocated "info" buffer instead of only freeing it upon success. Fixes: 8fae856c53500a ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: meson: add missing ENOMEM check in meson_nfc_read_buf()Martin Blumenstingl
kzalloc() can return NULL if memory could not be allocated. Check the return value of the kzalloc() call in meson_nfc_read_buf() to make it consistent with other memory allocations within the meson_nand driver. Fixes: 8fae856c53500a ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: atmel: switch to SPDX license identifiersTudor Ambarus
Adopt the SPDX license identifiers to ease license compliance management. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: atmel: add sam9x60 nand controller supportTudor Ambarus
The sam9x60 board defines the CCFG_EBICSA register under SFR, and not as a MATRIX register, as previous boards do. NAND Flash I/Os are connected to D16–D23, thus SFR_CCFG_EBICSA.NFD0_ON_D16 is set to 1. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: atmel: add generic name for EBICSA regmapTudor Ambarus
The sam9x60 board defines the CCFG_EBICSA register under SFR, and not as a MATRIX register, as previous boards do. Add a more generic name for the EBICSA regmap, as a prerequisite for sam9x60 nand controller support. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: Mark expected switch fall-throughsGustavo A. R. Silva
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warning: drivers/mtd/nand/raw/diskonchip.c: In function ‘doc_probe’: ./include/linux/printk.h:303:2: warning: this statement may fall through [-Wimplicit-fallthrough=] printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/diskonchip.c:1479:4: note: in expansion of macro ‘pr_err’ pr_err("DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n"); ^~~~~~ drivers/mtd/nand/raw/diskonchip.c:1480:3: note: here default: ^~~~~~~ drivers/mtd/nand/raw/nandsim.c: In function ‘ns_init_module’: drivers/mtd/nand/raw/nandsim.c:2254:22: warning: this statement may fall through [-Wimplicit-fallthrough=] chip->bbt_options |= NAND_BBT_NO_OOB; drivers/mtd/nand/raw/nandsim.c:2255:2: note: here case 1: ^~~~ drivers/mtd/nand/raw/nuc900_nand.c: In function ‘nuc900_nand_command_lp’: ./arch/x86/include/asm/io.h:91:22: warning: this statement may fall through [-Wimplicit-fallthrough=] #define __raw_writel __writel drivers/mtd/nand/raw/nuc900_nand.c:52:2: note: in expansion of macro ‘__raw_writel’ __raw_writel((val), (dev)->reg + REG_SMCMD) ^~~~~~~~~~~~ drivers/mtd/nand/raw/nuc900_nand.c:196:3: note: in expansion of macro ‘write_cmd_reg’ write_cmd_reg(nand, NAND_CMD_READSTART); ^~~~~~~~~~~~~ drivers/mtd/nand/raw/nuc900_nand.c:197:2: note: here default: ^~~~~~~ drivers/mtd/nand/raw/omap_elm.c: In function ‘elm_context_restore’: drivers/mtd/nand/raw/omap_elm.c:512:4: warning: this statement may fall through [-Wimplicit-fallthrough=] elm_write_reg(info, ELM_SYNDROME_FRAGMENT_4 + offset, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ regs->elm_syndrome_fragment_4[i]); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/omap_elm.c:514:3: note: here case BCH8_ECC: ^~~~ drivers/mtd/nand/raw/omap_elm.c:517:4: warning: this statement may fall through [-Wimplicit-fallthrough=] elm_write_reg(info, ELM_SYNDROME_FRAGMENT_2 + offset, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ regs->elm_syndrome_fragment_2[i]); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/omap_elm.c:519:3: note: here case BCH4_ECC: ^~~~ drivers/mtd/nand/raw/omap_elm.c: In function ‘elm_context_save’: drivers/mtd/nand/raw/omap_elm.c:466:37: warning: this statement may fall through [-Wimplicit-fallthrough=] regs->elm_syndrome_fragment_4[i] = elm_read_reg(info, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ ELM_SYNDROME_FRAGMENT_4 + offset); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/omap_elm.c:468:3: note: here case BCH8_ECC: ^~~~ drivers/mtd/nand/raw/omap_elm.c:471:37: warning: this statement may fall through [-Wimplicit-fallthrough=] regs->elm_syndrome_fragment_2[i] = elm_read_reg(info, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ ELM_SYNDROME_FRAGMENT_2 + offset); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mtd/nand/raw/omap_elm.c:473:3: note: here case BCH4_ECC: ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enabling -Wimplicit-fallthrough. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: rawnand: gpmi: Introduce GPMI_IS_MXS() macroFabio Estevam
Introduce a GPMI_IS_MXS() macro to take into account the cases when mx23 or mx28 are used, which helps readability. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-03-21mtd: spinand: Use the spi-mem dirmap APIBoris Brezillon
Make use of the spi-mem direct mapping API to let advanced controllers optimize read/write operations when they support direct mapping. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Stefan Roese <sr@denx.de>
2019-03-13Merge tag 'upstream-5.1-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs Pull UBI and UBIFS updates from Richard Weinberger: - A new interface for UBI to deal better with read disturb - Reject unsupported ioctl flags in UBIFS (xfstests found it) * tag 'upstream-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: ubi: wl: Silence uninitialized variable warning ubifs: Reject unsupported ioctl flags explicitly ubi: Expose the bitrot interface ubi: Introduce in_pq()
2019-03-05ubi: wl: Silence uninitialized variable warningDan Carpenter
This condition needs to be fipped around because "err" is uninitialized when "force" is set. The Smatch static analysis tool complains and UBsan will also complain at runtime. Fixes: 663586c0a892 ("ubi: Expose the bitrot interface") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Tested-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-03-04Merge tag 'spi-v5.1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "A fairly quiet release for SPI, the biggest thing is the conversion to use GPIO descriptors which is now 90% done but still needs some stragglers converting. Summary: - Support for inter-word delays - Conversion of the core and most drivers to use GPIO descriptors for GPIO controlled chip selects - New drivers for NXP FlexSPI and QuadSPI, SiFive and Spreadtrum" * tag 'spi-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (104 commits) spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3 spi: sifive: Remove redundant dev_err call in sifive_spi_probe() spi: sifive: Remove spi_master_put in sifive_spi_remove() spi: spi-gpio: fix SPI_CS_HIGH capability spi: pxa2xx: Setup maximum supported DMA transfer length spi: sifive: Add driver for the SiFive SPI controller spi: sifive: Add DT documentation for SiFive SPI controller spi: sprd: Add a prefix for SPI DMA channel macros spi: sprd: spi: sprd: Add DMA mode support dt-bindings: spi: Add the DMA properties for the SPI dma mode spi: sprd: Add the SPI irq function for the SPI DMA mode dt-bindings: spi: imx: Add an entry for the i.MX8QM compatible spi: use gpio[d]_set_value_cansleep for setting chipselect GPIO spi: gpio: Advertise support for SPI_CS_HIGH spi: sh-msiof: Replace spi_master by spi_controller spi: sh-hspi: Replace spi_master by spi_controller spi: rspi: Replace spi_master by spi_controller spi: atmel-quadspi: add support for sam9x60 qspi controller dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 spi: atmel-quadspi: add support for named peripheral clock ...
2019-03-04Merge tag 'mtd/for-5.1' of git://git.infradead.org/linux-mtdLinus Torvalds
Pull MTD updates from Boris Brezillon: "Core MTD changes: - Use struct_size() where appropriate - mtd_{read,write}() as wrappers around mtd_{read,write}_oob() - Fix misuse of PTR_ERR() in docg3 - Coding style improvements in mtdcore.c SPI NOR changes: Core changes: - Add support of octal mode I/O transfer - Add a bunch of SPI NOR entries to the flash_info table SPI NOR controller driver changes: - cadence-quadspi: * Add support for Octal SPI controller * write upto 8-bytes data in STIG mode - mtk-quadspi: * rename config to a common one * add SNOR_HWCAPS_READ to spi_nor_hwcaps mask - Add Tudor as SPI-NOR co-maintainer NAND changes: NAND core changes: - Fourth batch of fixes/cleanup to the raw NAND core impacting various controller drivers (Sunxi, Marvell, MTK, TMIO, OMAP2). - Check the return code of nand_reset() and nand_readid_op(). - Remove ->legacy.erase and single_erase(). - Simplify the locking. - Several implicit fall through annotations. Raw NAND controllers drivers changes: - Fix various possible object reference leaks (MTK, JZ4780, Atmel) - ST: * Add support for STM32 FMC2 NAND flash controller - Meson: * Add support for Amlogic NAND flash controller - Denali: * Several cleanup patches - Sunxi: * Several cleanup patches - FSMC: * Disable NAND on remove() * Reset NAND timings on resume() SPI-NAND drivers changes: - Toshiba: * Add support for all Toshiba products. - Macronix: * Fix ECC status read. - Gigadevice: * Add support for GD5F1GQ4UExxG" * tag 'mtd/for-5.1' of git://git.infradead.org/linux-mtd: (64 commits) mtd: spi-nor: Fix wrong abbreviation HWCPAS mtd: spi-nor: cadence-quadspi: fix spelling mistake: "Couldnt't" -> "Couldn't" mtd: spi-nor: Add support for en25qh64 mtd: spi-nor: Add support for MX25V8035F mtd: spi-nor: Add support for EN25Q80A mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC mtd: spi-nor: split s25fl128s into s25fl128s0 and s25fl128s1 mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode mtd: spi-nor: Add support for mx25u3235f mtd: rawnand: denali_dt: remove single anonymous clock support mtd: rawnand: mtk: fix possible object reference leak mtd: rawnand: jz4780: fix possible object reference leak mtd: rawnand: atmel: fix possible object reference leak mtd: rawnand: fsmc: Disable NAND on remove() mtd: rawnand: fsmc: Reset NAND timings on resume() mtd: spinand: Add support for GigaDevice GD5F1GQ4UExxG mtd: rawnand: denali: remove unused dma_addr field from denali_nand_info mtd: rawnand: denali: remove unused function argument 'raw' mtd: rawnand: denali: remove unneeded denali_reset_irq() call ...
2019-03-04Merge branch 'spi-5.1' into spi-nextMark Brown
2019-02-25Merge tag 'nand/for-5.1' of git://git.infradead.org/linux-mtd into mtd/nextBoris Brezillon
NAND core changes: - Fourth batch of fixes/cleanup to the raw NAND core impacting various controller drivers (Sunxi, Marvell, MTK, TMIO, OMAP2). - Checking the return code of nand_reset() and nand_readid_op(). - Removing ->legacy.erase and single_erase(). - Simplifying the locking. - Several implicit fall through annotations. Raw NAND controllers drivers changes: - Fixing various possible object reference leaks (MTK, JZ4780, Atmel). - ST: * Adding support for STM32 FMC2 NAND flash controller. - Meson: * Adding support for Amlogic NAND flash controller. - Denali: * Several cleanup patches. - Sunxi: * Several cleanup patches. - FSMC: * Disabling NAND on remove(). * Resetting NAND timings on resume(). SPI-NAND drivers changes: - Toshiba: * Adding support for all Toshiba products. - Macronix: * Fixing ECC status read. - Gigadevice: * Adding support for GD5F1GQ4UExxG.
2019-02-25Merge tag 'spi-nor/for-5.1' of git://git.infradead.org/linux-mtd into mtd/nextBoris Brezillon
SPI NOR Changes Core changes: - Add support of octal mode I/O transfer - Add a bunch of SPI NOR entries to the flash_info table SPI NOR controller driver changes: - cadence-quadspi: * Add support for Octal SPI controller * write upto 8-bytes data in STIG mode - mtk-quadspi: * rename config to a common one * add SNOR_HWCAPS_READ to spi_nor_hwcaps mask MAINTAINERS: - Add Tudor as SPI-NOR co-maintainer
2019-02-24ubi: Expose the bitrot interfaceRichard Weinberger
Using UBI_IOCRPEB and UBI_IOCSPEB userspace can force reading and scrubbing of PEBs. In case of bitflips UBI will automatically take action and move data to a different PEB. This interface allows a daemon to foster your NAND. Signed-off-by: Richard Weinberger <richard@nod.at>
2019-02-24ubi: Introduce in_pq()Richard Weinberger
This function works like in_wl_tree() but checks whether an ubi_wl_entry is currently in the protection queue. We need this function to query the current state of an ubi_wl_entry. Signed-off-by: Richard Weinberger <richard@nod.at>
2019-02-21mtd: spi-nor: cadence-quadspi: fix spelling mistake: "Couldnt't" -> "Couldn't"Colin Ian King
There is a spelling mistake in a dev_error message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-21mtd: spi-nor: Add support for en25qh64Roger Pueyo Centelles
The Eon EN25QH64 is a 64 Mbit SPI NOR flash memory chip found on recent wireless routers. Its 32, 128 and 256 Mbit siblings are already supported. Tested on a COMFAST CF-E120A v3 router board. Signed-off-by: Roger Pueyo Centelles <roger.pueyo@guifi.net> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-21mtd: spi-nor: Add support for MX25V8035FFrieder Schrempf
This adds support for the Macronix MX25V8035F, a 8Mb SPI NOR chip. It is used on i.MX6UL/ULL SoMs by Kontron Electronics GmbH (N631x). It was only tested with a single data line connected, by writing and reading random data with dd. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-21mtd: spi-nor: Add support for EN25Q80AFrieder Schrempf
This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip. It is used on i.MX6 boards by Kontron Electronics GmbH (N60xx, N61xx). It was only tested with a single data line connected, by writing and reading random data with dd. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-13mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controllerVignesh R
Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an integrated PHY. IP register layout is very similar to existing QSPI IP except for additional bits to support Octal and Octal DDR mode. Therefore, extend current driver to support Octal mode. Only Octal SDR read (1-1-8)mode is supported for now. Tested with mt35xu512aba Octal flash on TI's AM654 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-13mtd: spi-nor: split s25fl128s into s25fl128s0 and s25fl128s1Ahmet Celenk
Due to two different versions (S25FL128SAGBHI200 and S25FL128SAGBHI210) of the s25fl128s qspi memory, the single "s25fl128s" device entry must be split into two to match the correct JEDEC ID's for each version. Solves paging related issues of S25FL128SAGBHI210 chips. Signed-off-by: Ahmet Celenk <ahmet.celenk@procenne.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-13mtd: powernv_flash: Fix device registration errorAneesh Kumar K.V
This change helps me to get multiple mtd device registered. Without this I get sysfs: cannot create duplicate filename '/bus/nvmem/devices/flash0' CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.0.0-rc2-00557-g1ef20ef21f22 #13 Call Trace: [c0000000b38e3220] [c000000000b58fe4] dump_stack+0xe8/0x164 (unreliable) [c0000000b38e3270] [c0000000004cf074] sysfs_warn_dup+0x84/0xb0 [c0000000b38e32f0] [c0000000004cf6c4] sysfs_do_create_link_sd.isra.0+0x114/0x150 [c0000000b38e3340] [c000000000726a84] bus_add_device+0x94/0x1e0 [c0000000b38e33c0] [c0000000007218f0] device_add+0x4d0/0x830 [c0000000b38e3480] [c0000000009d54a8] nvmem_register.part.2+0x1c8/0xb30 [c0000000b38e3560] [c000000000834530] mtd_nvmem_add+0x90/0x120 [c0000000b38e3650] [c000000000835bc8] add_mtd_device+0x198/0x4e0 [c0000000b38e36f0] [c00000000083619c] mtd_device_parse_register+0x11c/0x280 [c0000000b38e3780] [c000000000840830] powernv_flash_probe+0x180/0x250 [c0000000b38e3820] [c00000000072c120] platform_drv_probe+0x60/0xf0 [c0000000b38e38a0] [c0000000007283c8] really_probe+0x138/0x4d0 [c0000000b38e3930] [c000000000728acc] driver_probe_device+0x13c/0x1b0 [c0000000b38e39b0] [c000000000728c7c] __driver_attach+0x13c/0x1c0 [c0000000b38e3a30] [c000000000725130] bus_for_each_dev+0xa0/0x120 [c0000000b38e3a90] [c000000000727b2c] driver_attach+0x2c/0x40 [c0000000b38e3ab0] [c0000000007270f8] bus_add_driver+0x228/0x360 [c0000000b38e3b40] [c00000000072a2e0] driver_register+0x90/0x1a0 [c0000000b38e3bb0] [c00000000072c020] __platform_driver_register+0x50/0x70 [c0000000b38e3bd0] [c00000000105c984] powernv_flash_driver_init+0x24/0x38 [c0000000b38e3bf0] [c000000000010904] do_one_initcall+0x84/0x464 [c0000000b38e3cd0] [c000000001004548] kernel_init_freeable+0x530/0x634 [c0000000b38e3db0] [c000000000011154] kernel_init+0x1c/0x168 [c0000000b38e3e20] [c00000000000bed4] ret_from_kernel_thread+0x5c/0x68 mtd mtd1: Failed to register NVMEM device With the change we now have root@(none):/sys/bus/nvmem/devices# ls -al total 0 drwxr-xr-x 2 root root 0 Feb 6 20:49 . drwxr-xr-x 4 root root 0 Feb 6 20:49 .. lrwxrwxrwx 1 root root 0 Feb 6 20:49 flash@0 -> ../../../devices/platform/ibm,opal:flash@0/mtd/mtd0/flash@0 lrwxrwxrwx 1 root root 0 Feb 6 20:49 flash@1 -> ../../../devices/platform/ibm,opal:flash@1/mtd/mtd1/flash@1 Fixes: 1cbb4a1c433a ("mtd: powernv: Add powernv flash MTD abstraction driver") Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-13mtd: Use mtd->name when registering nvmem deviceAneesh Kumar K.V
With this patch, we use the mtd->name instead of concatenating the name with '0'. Fixes: c4dfa25ab307 ("mtd: add support for reading MTD devices via the nvmem API") Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-02-10mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG modePurna Chandra Mandal
cadence-quadspi controller allows upto eight bytes of data to be written in software Triggered Instruction generator (STIG) mode of operation. Lower 4 bytes are written through writedatalower and upper 4 bytes by writedataupper register. This patch allows all the 8 bytes to be written. Signed-off-by: Purna Chandra Mandal <purna.chandra.mandal@intel.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
generated by cgit (git 2.34.1) at 2025-09-12 21:19:15 +0000