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2024-10-22phy: sparx5-serdes: add constants to match dataDaniel Machon
We need to handle a few different constants that differ for Sparx5 and lan969x. Add a new struct: sparx5_serdes_consts for this purpose. We populate it with an initial field for the number of SERDES'es: sd_max. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-2-d695bcb57b84@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-22phy: sparx5-serdes: add support for private match dataDaniel Machon
In order to reuse the existing Sparx5 SERDES driver for lan969x, we add support for private match data, with initial fields for the iomap and imap_size. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-1-d695bcb57b84@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21phy: bcm-ns-usb2: drop support for old binding variantRafał Miłecki
The old binding was incorrectly designed and ended up being deprecated 3 years ago. Finally it has been dropped so relevant code it not needed anymore. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20240913044557.28315-2-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21phy: tegra: xusb: Add error pointer check in xusb.cDipendra Khadka
Add error pointer check after tegra_xusb_find_lane(). Fixes: e8f7d2f409a1 ("phy: tegra: xusb: Add usb-phy support") Signed-off-by: Dipendra Khadka <kdipendra88@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20240930191101.13184-1-kdipendra88@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-21phy: freescale: imx8m-pcie: Do CMN_RST just before PHY PLL lock checkRichard Zhu
When enable initcall_debug together with higher debug level below. CONFIG_CONSOLE_LOGLEVEL_DEFAULT=9 CONFIG_CONSOLE_LOGLEVEL_QUIET=9 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 The initialization of i.MX8MP PCIe PHY might be timeout failed randomly. To fix this issue, adjust the sequence of the resets refer to the power up sequence listed below. i.MX8MP PCIe PHY power up sequence: /--------------------------------------------- 1.8v supply ---------/ /--------------------------------------------------- 0.8v supply ---/ ---\ /-------------------------------------------------- X REFCLK Valid Reference Clock ---/ \-------------------------------------------------- ------------------------------------------- | i_init_restn -------------- ------------------------------------ | i_cmn_rstn --------------------- ------------------------------- | o_pll_lock_done -------------------------- Logs: imx6q-pcie 33800000.pcie: host bridge /soc@0/pcie@33800000 ranges: imx6q-pcie 33800000.pcie: IO 0x001ff80000..0x001ff8ffff -> 0x0000000000 imx6q-pcie 33800000.pcie: MEM 0x0018000000..0x001fefffff -> 0x0018000000 probe of clk_imx8mp_audiomix.reset.0 returned 0 after 1052 usecs probe of 30e20000.clock-controller returned 0 after 32971 usecs phy phy-32f00000.pcie-phy.4: phy poweron failed --> -110 probe of 30e10000.dma-controller returned 0 after 10235 usecs imx6q-pcie 33800000.pcie: waiting for PHY ready timeout! dwhdmi-imx 32fd8000.hdmi: Detected HDMI TX controller v2.13a with HDCP (samsung_dw_hdmi_phy2) imx6q-pcie 33800000.pcie: probe with driver imx6q-pcie failed with error -110 Fixes: dce9edff16ee ("phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support") Cc: stable@vger.kernel.org Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> v2 changes: - Rebase to latest fixes branch of linux-phy git repo. - Richard's environment have problem and can't sent out patch. So I help post this fix patch. Link: https://lore.kernel.org/r/20241021155241.943665-1-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitionsLorenzo Bianconi
Fix the following register definitions for REG_CSR_2L_RX{0,1}_REV0 registers: - CSR_2L_PXP_VOS_PNINV - CSR_2L_PXP_FE_GAIN_NORMAL_MODE - CSR_2L_PXP_FE_GAIN_TRAIN_MODE Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-4-8291729a87f8@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in ↵Lorenzo Bianconi
airoha_pcie_phy_init_ssc_jcpll() Fix typo configuring REG_CSR_2L_JCPLL_SDM_HREN register in airoha_pcie_phy_init_ssc_jcpll routine. Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-3-8291729a87f8@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in airoha_pcie_phy_init_csr_2l()Lorenzo Bianconi
Fix typos configuring REG_PCIE_PMA_TX_RESET register in airoha_pcie_phy_init_csr_2l routine for lane0 and lane1 Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-2-8291729a87f8@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in ↵Lorenzo Bianconi
airoha_pcie_phy_init_clk_out() Fix typo configuring REG_CSR_2L_PLL_CMN_RESERVE0 register in airoha_pcie_phy_init_clk_out routine. Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-1-8291729a87f8@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLLAndy Yan
RST_PHY/RST_ROPLL/RST_LCPLL are used for debug only on rk3588, and they are not exported on rk3576, no need to request it in driver. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20240920093629.7410-1-andyshrk@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: phy-rockchip-samsung-hdptx: Depend on CONFIG_COMMON_CLKCristian Ciocaltea
Ensure CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX depends on CONFIG_COMMON_CLK to fix the following link errors when compile testing some random kernel configurations: m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.o: in function `rk_hdptx_phy_clk_register': drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1031:(.text+0x470): undefined reference to `__clk_get_name' m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1036:(.text+0x4ba): undefined reference to `devm_clk_hw_register' m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1040:(.text+0x4d2): undefined reference to `of_clk_hw_simple_get' m68k-linux-ld: drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:1040:(.text+0x4da): undefined reference to `devm_of_clk_add_hw_provider' Fixes: c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202409180305.53PXymZn-lkp@intel.com/ Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240923-sam-hdptx-link-fix-v1-1-8d10d7456305@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: add NXP PTN3222 eUSB2 to USB2 redriverDmitry Baryshkov
The NXP PTN3222 is the single-port eUSB2 to USB2 redriver that performs translation between eUSB2 and USB2 signalling schemes. It supports all three data rates: Low Speed, Full Speed and High Speed. The reset state enables autonegotiation of the PHY role and of the data rate, so no additional programming is required. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Konrad Dybcio <konradybcio@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org> Tested-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20240830-nxp-ptn3222-v2-2-4c6d8535cf6c@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: Switch back to struct platform_driver::remove()Uwe Kleine-König
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/phy/ to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. While touching these files, make indention of the struct initializer consistent in several files. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20241009065307.504930-2-u.kleine-koenig@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: ti: phy-j721e-wiz: fix usxgmii configurationSiddharth Vadapalli
Commit b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver") added support for USXGMII mode. In doing so, P0_REFCLK_SEL was set to "pcs_mac_clk_divx1_ln_0" (0x3) and P0_STANDARD_MODE was set to LANE_MODE_GEN1, which results in a data rate of 5.15625 Gbps. However, since the USXGMII mode can support up to 10.3125 Gbps data rate, the aforementioned fields should be set to "pcs_mac_clk_divx0_ln_0" (0x2) and LANE_MODE_GEN2 respectively. The signal corresponding to the USXGMII lane of the SERDES has been measured as 5 Gbps without the change and 10 Gbps with the change. Hence, fix the configuration accordingly to support USXGMII up to 10G. Fixes: b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20241012053937.3596885-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: starfive: jh7110-usb: Fix link configuration to controllerJan Kiszka
In order to connect the USB 2.0 PHY to its controller, we also need to set "u0_pdrstn_split_sw_usbpipe_plugen" [1]. Some downstream U-Boot versions did that, but upstream firmware does not, and the kernel must not rely on such behavior anyway. Failing to set this left the USB gadget port invisible to connected hosts behind. Link: https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/sys_syscon.html#sys_syscon__section_b3l_fqs_wsb [1] Fixes: 16d3a71c20cf ("phy: starfive: Add JH7110 USB 2.0 PHY driver") Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20241015070444.20972-2-minda.chen@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: edp: Add support for eDP PHY on SA8775PSoutrik Mukhopadhyay
Add support for eDP PHY v5 found on the Qualcomm SA8775P platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com> Link: https://lore.kernel.org/r/20241004103046.22209-4-quic_mukhopad@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: edp: Introduce aux_cfg array for version specific aux settingsSoutrik Mukhopadhyay
In order to support different HW versions, introduce aux_cfg array to move v4 specific aux configuration settings. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com> Link: https://lore.kernel.org/r/20241004103046.22209-3-quic_mukhopad@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: qmp-pcie: drop bogus x1e80100 qref suppliesJohan Hovold
The PCIe PHYs on x1e80100 do not a have a qref supply so stop requesting one. This also avoids the follow warning at boot: qcom-qmp-pcie-phy 1bfc000.phy: supply vdda-qref not found, using dummy regulator Fixes: 9dab00ee9544 ("phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100") Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE") Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241015121406.15033-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: rockchip: usbdp: add rk3576 device match dataFrank Wang
This adds RK3576 device match data support. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241014020342.15974-2-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Remove unnecessary LUT entriesAdam Ford
The lookup table contains entries which use the integer divider instead of just the fractional divider. Since the set and round functions check both the integer divider values and the LUT values, it's no longer necessary to keep the integer divider values in the lookup table, as can be dynamically calcuated. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Link: https://lore.kernel.org/r/20240914112816.520224-6-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Use closest dividerAdam Ford
Currently, if the clock values cannot be set to the exact rate, the round_rate and set_rate functions use the closest value found in the look-up-table. In preparation of removing values from the LUT that can be calculated evenly with the integer calculator, it's necessary to ensure to check both the look-up-table and the integer divider clock values to get the closest values to the requested value. It does this by measuring the difference between the requested clock value and the closest value in both integer divider calucator and the fractional clock look-up-table. Which ever has the smallest difference between them is returned as the closest rate. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20240914112816.520224-5-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Support dynamic integerAdam Ford
There is currently a look-up table for a variety of resolutions. Since the phy has the ability to dynamically calculate the values necessary to use the intger divider which should allow more resolutions without having to update the look-up-table. If the lookup table cannot find an exact match, fall back to the dynamic calculator of the integer divider. Previously, the value of P was hard-coded to 1, this required an update to the phy_pll_cfg table to add in the extra value into the table, so if the value of P is calculated to be something else by the PMS calculator, the calculated_phy_pll_cfg structure can be used instead without having to keep track of which method was used. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20240914112816.520224-4-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookupAdam Ford
The value of 'S' is writen to two places, PHY_REG3[7:4] and PHY_REG21[3:0]. There is a lookup table which contains the value of PHY_REG3. Rather than using a switch statement based on the pixel clock to search for the value of 'S' again, just shift the contents of PHY_REG3[7:4] >> 4 and place the value in PHY_REG21[3:0]. Doing this can eliminate an entire function. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Link: https://lore.kernel.org/r/20240914112816.520224-3-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Replace register defines with macroAdam Ford
There are 47 registers defined as PHY_REG_xx were xx goes from 00 to 47. Simplify this by replacing them all with a macro which is passed the register number to return the proper register offset. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Link: https://lore.kernel.org/r/20240914112816.520224-2-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: qmp-combo: move driver data initialisation earlierJohan Hovold
Commit 44aff8e31080 ("phy: qcom-qmp-combo: clean up probe initialisation") removed most users of the platform device driver data, but mistakenly also removed the initialisation despite the data still being used in the runtime PM callbacks. The initialisation was soon after restored by commit 83a0bbe39b17 ("phy: qcom-qmp-combo: add support for updated sc8280xp binding") but now happens slightly later during probe. This should not cause any trouble currently as runtime PM needs to be enabled manually through sysfs and the platform device would not be suspended before the PHY has been registered anyway. Move the driver data initialisation to avoid a NULL-pointer dereference on runtime suspend if runtime PM is ever enabled by default in this driver. Fixes: 44aff8e31080 ("phy: qcom-qmp-combo: clean up probe initialisation") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240911115253.10920-5-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: qmp-usbc: fix NULL-deref on runtime suspendJohan Hovold
Commit 413db06c05e7 ("phy: qcom-qmp-usb: clean up probe initialisation") removed most users of the platform device driver data from the qcom-qmp-usb driver, but mistakenly also removed the initialisation despite the data still being used in the runtime PM callbacks. This bug was later reproduced when the driver was copied to create the qmp-usbc driver. Restore the driver data initialisation at probe to avoid a NULL-pointer dereference on runtime suspend. Apparently no one uses runtime PM, which currently needs to be enabled manually through sysfs, with these drivers. Fixes: 19281571a4d5 ("phy: qcom: qmp-usb: split USB-C PHY driver") Cc: stable@vger.kernel.org # 6.9 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240911115253.10920-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: qmp-usb-legacy: fix NULL-deref on runtime suspendJohan Hovold
Commit 413db06c05e7 ("phy: qcom-qmp-usb: clean up probe initialisation") removed most users of the platform device driver data from the qcom-qmp-usb driver, but mistakenly also removed the initialisation despite the data still being used in the runtime PM callbacks. This bug was later reproduced when the driver was copied to create the qmp-usb-legacy driver. Restore the driver data initialisation at probe to avoid a NULL-pointer dereference on runtime suspend. Apparently no one uses runtime PM, which currently needs to be enabled manually through sysfs, with these drivers. Fixes: e464a3180a43 ("phy: qcom-qmp-usb: split off the legacy USB+dp_com support") Cc: stable@vger.kernel.org # 6.6 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240911115253.10920-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: qmp-usb: fix NULL-deref on runtime suspendJohan Hovold
Commit 413db06c05e7 ("phy: qcom-qmp-usb: clean up probe initialisation") removed most users of the platform device driver data, but mistakenly also removed the initialisation despite the data still being used in the runtime PM callbacks. Restore the driver data initialisation at probe to avoid a NULL-pointer dereference on runtime suspend. Apparently no one uses runtime PM, which currently needs to be enabled manually through sysfs, with this driver. Fixes: 413db06c05e7 ("phy: qcom-qmp-usb: clean up probe initialisation") Cc: stable@vger.kernel.org # 6.2 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240911115253.10920-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: rockchip: inno-usb2: Add usb2 phys support for rk3576William Wu
The RK3576 SoC has two independent USB2.0 PHYs, and each PHY has one port. This adds device specific data for it. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241016073713.14133-4-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: rockchip: inno-usb2: convert clock management to bulkFrank Wang
Since some Rockchip SoCs (e.g RK3576) have more than one clock, this converts the clock management from single to bulk method to make the driver more flexible. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241016073713.14133-1-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: stm32: Remove unneeded semicolonYang Li
This patch removes an unneeded semicolon after a switch statement. ./drivers/phy/st/phy-stm32-combophy.c:226:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=11403 Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20241017040657.33992-1-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3Qiang Yu
Currently driver supports only x4 lane based functionality using tx/rx and tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3, PCIe3 related QMP PHY provides additional programming which are available as txz and rxz based register set. Hence add txz and rxz based registers usage and programming sequences. As soon as software programs the txz and rxz based register set, hardware shall "broadcast" the same settings to the tx/rx pair of registers for all the 8 lanes, which saves the effort of software programming them one by one. There might be some tx and/or rx registers on some lanes need minor tweaks, program them after programming the txz and rxz reigster set. In addition, x1e80100 uses QMP PHY ver 6.30 for PCIe Gen4 x8, hence add two new header files to reflect the new register offsets. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20241017030412.265000-5-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-11phy: qcom: qmp: Add qmp configuration for QCS8300Krishna Kurapati
Add qmp configuration for QCS8300. It is similar to SA8775P and SC8280XP except for some Lane configuration settings specific to QCS8300. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241009195348.2649368-5-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-11phy: ti: gmii-sel: Enable USXGMII mode for J7200Siddharth Vadapalli
TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1. Add USXGMII mode to the extra_modes member of J7200's SoC data. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20241010144845.2555983-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-11phy: usb: disable COMMONONN for dual modeJustin Chen
The COMMONONN bit suspends the phy when the port is put into a suspend state. However when the phy is shared between host and device in dual mode, this no longer works cleanly as there is no synchronization between the two. Fixes: 5095d045a962 ("phy: usb: Turn off phy when port is in suspend") Signed-off-by: Justin Chen <justin.chen@broadcom.com> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20241010185344.859865-1-justin.chen@broadcom.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: stm32: Add support for STM32MP25 COMBOPHY.Christian Bruel
Addition of the COMBOPHY driver found on STM32MP25 platforms This single lane PHY is shared (exclusive) between the USB3 and PCIE controllers. Supports 5Gbit/s for PCIE gen2 or 2.5Gbit/s for PCIE gen1. Supports wakeup-source capability to wakeup system using remote-wakeup capable USB device Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20240930170847.948779-3-christian.bruel@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: mvebu-cp110-utmi: support swapping d+/d- lanes by dts propertyJosua Mayer
CP11x UTMI PHY supports swapping D+/D- signals via digital control register 1. Add support for the "swap-dx-lanes" device-tree property, which lists the port-ids that should swap D+ and D-. The property is evaluated in probe and applied before power-on during mvebu_cp110_utmi_port_setup. Signed-off-by: Josua Mayer <josua@solid-run.com> Link: https://lore.kernel.org/r/20241002-mvebu-utmi-phy-v4-1-83783dc89b9d@solid-run.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control registerBartosz Wawrzyniak
Fix the value of SIERRA_DEQ_OPENEYE_CTRL_PREG and add a definition for SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG. This fixes the SGMII single link register configuration. Fixes: 7a5ad9b4b98c ("phy: cadence: Sierra: Update single link PCIe register configuration") Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com> Link: https://lore.kernel.org/r/20241003123405.1101157-1-bwawrzyn@cisco.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: phy-rockchip-inno-usb2: Use dev_err_probe() in the probe pathDragan Simic
Improve error handling in the probe path by using function dev_err_probe() instead of function dev_err(), where appropriate. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/d4ccd9fc278fb46ea868406bf77811ee507f0e4e.1725524803.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: phy-rockchip-inno-usb2: Handle failed extcon allocation betterDragan Simic
Return the actual error code upon failure to allocate extcon device, instead of hardcoding -ENOMEM. Use dev_err_probe() to also log appropriate messages, which is fine because the containing function is used in the probe path. Helped-by: Heiko Stubner <heiko@sntech.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/cc4995aa3e569be6bc23ca126b41fba82d50eeee.1725524802.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: phy-rockchip-inno-usb2: Perform trivial code cleanupsDragan Simic
Perform a few trivial code cleanups, e.g. to obey the reverse Christmas tree rule, to avoid use of "{ ... }" code blocks where they aren't really needed, or to avoid line wrapping by using the 100-column width better. No intended functional changes are introduced by these code cleanups. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/adce7309f6fd9e1191c53bab552a8531d1a71216.1725524802.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: usb: update Broadcom driver table to use designated initializersSam Edwards
The Broadcom USB PHY driver contains a lookup table (`reg_bits_map_tables`) to resolve register bitmaps unique to certain versions of the USB PHY as found in various Broadcom chip families. Historically, this table was just kept carefully in sync with the "selector" enum every time the latter changed to ensure consistency. However, a recent commit [1] introduced two new enumerators but did not adjust the array for BCM4908, thus breaking the xHCI controller (and boot process) on this platform and revealing the fragility of this approach. Since these arrays are a little sparse (many elements are zero) and the position of the array elements is significant only insofar as they agree with the enumerators, designated initializers are a better fit than positional initializers here. Convert this table accordingly. [1] 4536fe9640b6 ("phy: usb: suppress OC condition for 7439b2") Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Justin Chen <justin.chen@broadcom.com> Link: https://lore.kernel.org/r/20241004034131.1363813-3-CFSworks@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: usb: Fix missing elements in BCM4908 USB init arraySam Edwards
The Broadcom USB PHY driver contains a lookup table (`reg_bits_map_tables`) to resolve register bitmaps unique to certain versions of the USB PHY as found in various Broadcom chip families. A recent commit (see 'fixes' tag) introduced two new elements to each chip family in this table -- except for one: BCM4908. This resulted in the xHCI controller not being initialized correctly, causing a panic on boot. The next patch will update this table to use designated initializers in order to prevent this from happening again. For now, just add back the missing array elements to resolve the regression. Fixes: 4536fe9640b6 ("phy: usb: suppress OC condition for 7439b2") Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Justin Chen <justin.chen@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20241004034131.1363813-2-CFSworks@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-09-23Merge tag 'phy-for-6.12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New hw support: - Rcar usb2 support for RZ/G3S SoC - Nuvoton MA35 SoC USB 2.0 PHY driver Removed: - obsolete qcom,usb-8x16-phy bindings Updates: - 4 lane PCIe support for Qualcomm X1E80100 - Constify structure in subsystem update - Subsystem simplification with scoped for each OF child loop update - Yaml conversion for Qualcomm sata phy, Hiilicon hi3798cv200-combphy bindings" * tag 'phy-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (40 commits) phy: renesas: rcar-gen3-usb2: Add support for the RZ/G3S SoC dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings phy: renesas: rcar-gen3-usb2: Add support to initialize the bus phy: ti: j721e-wiz: Simplify with scoped for each OF child loop phy: ti: j721e-wiz: Drop OF node reference earlier for simpler code phy: ti: gmii-sel: Simplify with dev_err_probe() phy: ti: am654-serdes: Use scoped device node handling to simplify error paths phy: qcom: qmp-pcie-msm8996: Simplify with scoped for each OF child loop phy: mediatek: xsphy: Simplify with scoped for each OF child loop phy: mediatek: tphy: Simplify with scoped for each OF child loop phy: hisilicon: usb2: Simplify with scoped for each OF child loop phy: cadence: sierra: Simplify with scoped for each OF child loop phy: broadcom: brcm-sata: Simplify with scoped for each OF child loop phy: broadcom: bcm-cygnus-pcie: Simplify with scoped for each OF child loop phy: nuvoton: add new driver for the Nuvoton MA35 SoC USB 2.0 PHY dt-bindings: phy: nuvoton,ma35-usb2-phy: add new bindings phy: qcom: qmp-pcie: Configure all tables on port B PHY phy: airoha: adjust initialization delay in airoha_pcie_phy_init() dt-bindings: phy: socionext,uniphier: add top-level constraints phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100 ...
2024-09-18Merge tag 'for-v6.12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply Pull power supply and reset updates from Sebastian Reichel: "Power-supply core: - introduce power_supply_show_enum_with_available() helper - change usb_types from an array into a bitmask - fix early usage of power_supply_property_is_writeable() resulting in sysfs files not being writable - fix missing temp1_max_alarm attribute in power-supply's hwmon devices Drivers: - max1720x: expose nvmem device - brcmstb: cleanup driver to use latest APIs - max77693: expose input and charging current limit - max17042_battery: fix state of charge reading for devices without current sensing - axp20x_battery: add AXP717 support - axp20x_battery: fix min/max voltage properties - axp20x_usb_power: add AXP717 support - axp20x_usb_power: add DT based input current limit Documentation updates Misc minor cleanups and fixes" * tag 'for-v6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply: (38 commits) power: supply: hwmon: Fix missing temp1_max_alarm attribute power: supply: Drop use_cnt check from power_supply_property_is_writeable() power: supply: ab8500: Constify struct kobj_type power: supply: max1720x: fix a double free on error in probe() power: supply: axp20x_battery: add support for AXP717 power: supply: axp20x_usb_power: Add support for AXP717 dt-bindings: power: supply: axp20x: Add AXP717 compatible dt-bindings: power: supply: axp20x: Add AXP717 compatible power: supply: axp20x_usb_power: Fix spelling mistake "reqested" -> "requested" power: supply: Change usb_types from an array into a bitmask power: supply: sysfs: Move power_supply_show_enum_with_available() up power: supply: sysfs: Add power_supply_show_enum_with_available() helper power: supply: rt9467-charger: Remove "usb_type" property write support power: supply: ucs1002: Adjust ucs1002_set_usb_type() to accept string values power: supply: "usb_type" property may be written to power: supply: max1720x: add read support for nvmem mfd: axp20x: Add ADC, BAT, and USB cells for AXP717 power: supply: core: constify psy_tzd_ops power: reset: brcmstb: Do not go into infinite loop if reset fails power: reset: brcmstb: Use devm_register_sys_off_handler() ...
2024-09-03power: supply: Change usb_types from an array into a bitmaskHans de Goede
The bit_types array just hold a list of valid enum power_supply_usb_type values which map to 0 - 9. This can easily be represented as a bitmap. This reduces the size of struct power_supply_desc and further reduces the data section size by drivers no longer needing to store the array. This also unifies how usb_types are handled with charge_behaviours, which allows power_supply_show_usb_type() to be removed. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20240831142039.28830-7-hdegoede@redhat.com Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2024-08-30phy: renesas: rcar-gen3-usb2: Add support for the RZ/G3S SoCClaudiu Beznea
Add support for the Renesas RZ/G3S SoC. The support is similar with the rest of RZ/G2 devices with the except that the RZ/G3S needs bus initialization due to hardware limitation. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240822152801.602318-13-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-30phy: renesas: rcar-gen3-usb2: Add support to initialize the busClaudiu Beznea
The Renesas RZ/G3S need to initialize the USB BUS before transferring data due to hardware limitation. As the register that need to be touched for this is in the address space of the USB PHY, and the UBS PHY need to be initialized before any other USB drivers handling data transfer, add support to initialize the USB BUS. As the USB PHY is probed before any other USB drivers that enables clocks and de-assert the reset signals and the BUS initialization is done in the probe phase, we need to add code to de-assert reset signal and runtime resume the device (which enables its clocks) before accessing the registers. As the reset signals are not required by the USB PHY driver for the other USB PHY hardware variants, the reset signals and runtime PM was handled only in the function that initialize the USB BUS. The PHY initialization was done right after runtime PM enable to have all in place when the PHYs are registered. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/r/20240822152801.602318-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-30phy: ti: j721e-wiz: Simplify with scoped for each OF child loopKrzysztof Kozlowski
Use scoped for_each_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240826-phy-of-node-scope-v1-11-5b4d82582644@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-30phy: ti: j721e-wiz: Drop OF node reference earlier for simpler codeKrzysztof Kozlowski
Drop OF node reference immediately after using it in syscon_node_to_regmap(), which is both simpler and typical/expected code pattern. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240826-phy-of-node-scope-v1-10-5b4d82582644@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-19 11:42:55 +0000